Impact of Physical Cell Placement

on Physical Design Flow

Project Report

Submitted in Partial Fulfillment of the

Requirements for the Degree of

MASTER OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING

By
Anjali Yadav
(19MECE16)

Department of Electronics and Communication Engineering,

Institute of Technology,
Nirma University,
Ahmedabad 382 481

May 2021
 CERTIFICATE

Attach a photocopy of the certificate received from the company.

The certificate should be on the letterhead of the company.

i
 Acknowledgement

This project has given me the opportunity to implement parts of what I have learned in the past few
months. It wouldn’t have been possible without the help and support of many people. I would like to
take an opportunity and express my gratitude and sincere thanks to them. I want to thank my head of
department, Dr. Dhaval Pujara, post-graduate co-ordinator, Dr. Nagendra Gajjar and internal guide, Dr.
Sachin Gajjar, for the guidance, encouragement and support they have provided me throughout the
project. Also, I want to thank my manager and project guide in the Eximius Design India (Pvt) Ltd., Mr.
Nirmit Patel and Mr. Ravi Dhandha respectively. It might not have been possible to reach this far
without their directions. Their professional insights and experience were invaluable in my project work.
I would like to thank my university, Nirma University and my department, Institute of Technology, for
giving me opportunity to be part of such a nice firm where I am able to do such a nice project for my
dissertation. Lastly, I can never be excessively appreciative to my adoring guardians for their hard work.
I will always remain in debt of what my parents have provided me with. They have always encouraged
me to gain knowledge despite the prejudices existing on our society for the girls. Itis because of them
and their efforts I have reached this far.

(Anjali Yadav)
(19MECE16)

ii
 ABSTRACT

The complexity of SoC design and its fabrication is increasing due to modern technology node. Hence
more efforts should be given into doing physical design of these SoC. Many challenges have arisen in
terms of design, technology and tools as the number of transistors per chip are increasing. Hence,
optimization and automation of the circuits have also become complex. To deal with these problems
EDA tools such as Fusion Compiler, Innovus, IC compiler II, etc are used. The process of converting a
circuit representation of the design into physical layout is known as physical design, which describes the
cell placement, floor planning and routing for communication between cells and macros. All the semi-
conductor giants follow the basic physical design flow to meet various criteria like power, performance
and area. Physical cell is one of the part of these constraints. The main aim of this project is to get
detailed review of the impacts of different physical cells. By adding physical cells to the design, changes
occur in terms of power, area and performance. To study these impact Fusion Compiler is used as a tool.
Impact of tap cells, end-cap cells , filler cells and de-cap cells are studied. For any physical cell it is
important to be placed in correct orientation otherwise it leads to increase in number of DRC value. This
increase occur due to change in position of vts_n which leads to n-well discontinuity. Other impact such
as area and power are studied for these physical cells. For tap cells, it is seen that there is increase in
number of DRC around 3.35% as we decrease the number of well-tap cells used within the design.
Similar changes occur for filler cell, de-cap cell and end-cap cell with respect to DRC count. Mainly in
tap-cell and filler cell, DRC occurs due to n-well discontinuity. For de-cap cells, there is decrease in
dynamic power when decap cells are increased but after a certain number of increase in de-cap cells,
dynamic power also increases. Hence, the dynamic power increase or decrease depends on the number
of de-cap cells used within the design. The study also helps us to realize that if physical cells are absent
within the design then there would degradation in the quality of the chip.

iii
 INDEX
Chapter Title Page No.
No.
Acknowledgement ii
Abstract iii
Index iv
List of Figures vi
List of Tables vii
Nomenclature viii
1 Introduction 1
1.1 Company Profile 1
1.2 Group Profile 2
1.3 Introduction 3
1.4 Scope of the Training 3
1.5 Gantt Chart 4
1.6 Organization of the Rest of the Thesis 4
2 Literature Review 5
2.1 Floorplan 5
2.2 Placement 8
2.3 Clock Tree Synthesis 8
2.4 Routing 8
2.5 Static Timing Analysis 9
2.6 Physical Cell 9
3 Software Application 13

3.1 Fusion Compiler 13

4 Simulation and Results 16

4.1 Tap Cells 16

4.2 End-Cap Cells 18
4.3 Filler Cells 19

iv
 4.4 De-Cap Cells 22
5 Conclusions and Future Scope 24

5.1 Conclusion 24
5.2 Future Scope 24
References 25

v
 LIST OF FIGURES
Figure Title Page
No. No.

1 ASIC Flow 5

2 Physical Design Flow 6

3 Tapping the VDD with Nwell and VSS with Psub externally 9

4 End-Cap cells with Site-row 10

5 Filler and De-Cap Cells 11

6 De-cap Cells 12

7 Classic Front-end/Back-end Flow 13

8 Unified RTL-to-GDS II Flow 14

9 Compile_fusion Seven Stages 15

10 Orientation of Selected Tap Cells 16

11 Tap Cells in the Design 17

12 Orientation of Selected End-Cap Cells 18

13 End-Cap Cells in the Design 19

14 Orientation of Selected Filler Cell 20

15 Filler Cells in the Design 21

16 COD.H.R.5 and OD.R.9 Design Rule Check 22

17 De-Cap Cells in the Design 23

vi
 LIST OF TABLES
Table Title Page
No.
No.

1 Result of Change in Orientation of Tap Cells 17

2 Results of Change in Tap Cells Count 17

3 Result of Change in Orientation of End-Cap Cells 18

4 Results of Change in End-Cap Cells Count 19

5 Result of Change in Orientation of Filler Cells 20

6 Results of Change in Filler Cells Count 21

7 Result of Change in Space between Standard Cell 22

8 Results of Change in De-Cap Cells Count 23

vii
 NOMENCLATURE

Abbreviations

SOC System on Chip

IP Intellectual Property

ASIC Application Specific Integrated Circuit

TSMC Taiwan Semiconductor Manufacturing Company limited

VLSI Very Large-Scale Integration

TTM Time-To-Market

RTL Register-Transfer Level

GDS Graphic Design System

DC Design Compiler

CTS Clock Tree Synthesis

DMA Direct Memory Access

DDR Double Data Rate

PLL Phase- Locked Loop

UART Universal Asynchronous Receiver-Transmitter

SPI Serial Peripheral Interface

I2C Inter-Integrated Circuit

ADC Analog to Digital Converter

DAC Digital to Analog Converter

viii
Chapter 1
Introduction
1.1 Company Profile
In August 2013, Eximius Design was founded. It is headquartered in San Jose, CA. Apart
from CA it has design centers in India, Malaysia, and Singapore. It is recently acquired by Wipro
Limited. Eximius client list consists of some of fortune 100 enterprises and high-profile startups.
It is an engineering services company mainly aiming on ASIC design, FPGA design, Systems,
and Software engineering. Variety of innovative products are developed by its unique team of
engineers in past 25+ years. The unique challenge that comes while handling projects in terms of
project designing is very well understood by the founding team hence, it has been a part of 6
successful startups.

Eximius blends the product development experience of its leadership team with the customer
focus of its highly skilled engineers to deliver End-to-End Solutions and Services from “Concept
to Launch”. As part of its engagements, Eximius has led the development, from inception to
productization, of hundreds of designs spanning across the technology industry. It provides end-
to-end solutions and services for building smarter, smaller, and faster-connected products for
various use cases of IoT, Industry 4.0, Edge Computing, Cloud, 5G, and Artificial Intelligence.
Their expertise spans across SOC, IP, ASIC, FPGA, Hardware System, and Software domains.
Its clientele includes companies across semiconductors, cloud and hyper-scale infrastructure,
consumer electronics and automotive segments. It has joined the TSMC program, which focuses
on chip implementation services and system level design solutions to help lower design barriers
for customers adopting TSMC technology.

The Eximius design model is flexible. The Eximius design team helps in developing an ASIC
from a white-board discussion, to companies that don’t have their own ASIC team. This
company can also transfer an FPGA to an ASIC or to shrink process geometries. To help
customers meet their goals efficiently, they equip their customers with one or more phases of an
ASIC design (e.g. verification or physical implementation). It grasps the entire product design
cycle. It works for following industries:

1
 1. Semiconductor: A complete spectrum of solutions is provided by Eximius for
Semiconductor and Embedded Systems Design. RTL, design verification, DFT, and
FPGA Design and Development are services that are given by the company. The
Communication, bare-metal firmware and embedded software development, multimedia
integration, and system verification and validation are part of embedded system solutions.
2. Automotive: To develop innovative wireless, multimedia, AI, and compute technologies
into today’s connected cars for automotive companies, help is provided by Eximius. By
Using VLSI design, Embedded Platform Engineering, Multimedia, Connectivity, and
System Verification & Validation, it helps Automotive OEMs and Tier 1 companies
reduce their Time-To-Market (TTM) and improve on quality. Also, it helps customers for
ADAS by using AI which is one of the focus of the company.
3. Aerospace: Eximius offers a comprehensive range of Product Engineering services based
on RTCA DO-254, DO-178C, ARP 4754 & ARP 4761 to OEMs, Tier1 Suppliers &
Aircraft Manufacturers. The Company has capabilities in Flight Control & Flight
Management Systems, Electrical Power Generation & Distribution Systems, Breaking
Systems & Motor Drive Electronics. The Company follows AS9100 RevC Quality
Process.
4. Storage and Datacenter: Eximius design helps to take storage and cloud companies
concept to mass production. Eximius design helps with its Front-end design, Back end
design, Verification, Storage protocol expertise, firmware development expertise, test
automation, Cloud customization, and DevOps.
5. Digital Living and Consumer electronics: Many companies are employing cognitive
technologies, to make a digital home a reality. Eximius with its focus on Artificial
intelligence, Platform Engineering, and Connectivity is assured to support companies on
their vision of enabling cognitive technologies in the Intelligent Digital Mesh.

1.2 Group Profile

I am currently working in the Physical Design domain. All process nodes from 130 to 28 nm
have been built by the physical design team in last 10 years. The team has decades of experience
in developing products for a variety of sectors, including consumer products, enterprise
networking, microprocessors, cloud computing and data centers. It helps in making the right

2
 product and doing the right tradeoffs in terms of power, performance, and area. By keeping in
mind the performance, power and area, the team can help in developing an efficient design, just
from a product idea The Eximius design team helps in developing an ASIC from a white-board
discussion, to companies that don’t have their own ASIC team. The team develops ASIC
microarchitecture, identifies functionality that can be easily acquired, provides estimates for die-
size, power, development cost and a schedule to build, debug and deliver a product for the
customers.

A wide range of third-party IP blocks from ASIC suppliers and IP vendors has been
taken, to integrate in the products that has been developed by the team. It includes ARM9,
ARM11 and Cortex-A9 family of cores, PCIe and Ethernet serial interfaces, SPI, I2C, UART,
NOR and NAND peripheral interfaces, ADC/DAC and PLL blocks, and DMA and DDR
controllers.

1.3 Introduction
In this project we would study about the impact of different physical cells on physical
design flow. By adding physical cells to the design, changes occur in terms of power, area, and
performance. These cells are added into design, but they don’t appear into timing path report.
Also, they are not present in design netlist.

1.4 Scope of the Project

The main objective of the project is to understand the impact of physical cells in terms of
power, area, and performance in physical design flow. This project includes study on tap cells,
end-cap cells, filler cells and boundary cells. This project mainly focuses on number of DRC
occurring, change in area and power due to changes made in physical cell counts.

3
1.5 Gantt Chart

1.6 Organization of the Rest of the Thesis

In chapter 1 introduction, basic idea of the project is explained. It explains the purpose of
the project. In chapter 2 literature review, physical design flow is explained in detail. It also
describes about physical cells and its types. In chapter 3, gives basic understanding of Fusion
Compiler tool. Chapter 4 shows the simulation and results done within the project. Chapter 5
gives the conclusion and future work of the project.

4
Chapter 2
Literature Review
2.1 Floorplanning

[1]
Physical design is process of transforming netlist into layout . It is also called as Place
and Route (PnR). Placement of logical cells, clock tree synthesis (CTS) and routing are main
steps in physical design. Timing, power, design, and technology constraints are achieved during
the physical design process. Further these designs are needed to optimize in accordance to area,
power, and performance. Physical Design is part of ASIC flow as shown in figure 1. Now,
floorplanning is the second step in physical design which comes after import design as shown in
figure 2. One of the important and critical steps in physical design is floorplan. If floorplan is
good, then quality of chip and design implementation becomes good and easy respectively.
Implementation process like place, cts, route and timing closure becomes easy if floorplan is
good.

Functional
System Architectural
and Logical
Specification Design
Design

Physical
Physical
Verification Circuit Design
Design
and Sign off

Packaging and
Fabrication Chip
Testing

Figure 1 ASIC Flow

5
 Clock Tree Routing
Partitioning Synthesis Stage

Floor Placement Timing

Planning Stage
Closure

Figure 2 Physical Design Flow

A bad floorplan creates issue like congestion, timing, noise, ir, and routing issues. It also
leads to using more area, power, and affects reliability, life of the IC and at the end increase in
overall cost of the IC. For good floorplanning it is necessary to understand basic design,
connection of different blocks in partitions, data flow of the design, guidelines for special analog
hard IPs in the design.
Requirements of good floorplan are [1]: -
1) Basic design understanding
2) Data flow diagram
3) Integration guidelines
4) Needs of IO/Pin placements
5) Special requirements of full chip floorplan
6) Multi Voltage /Low Power requirements
7) Understanding of power domains and Voltage area.
Different types of floorplan techniques are: -
1) Abutted: - All interblock pin connection is done using FTs
2) Non-Abutted: - All interblock pin connection is done by routing in channels.
3) Mix of both: - It is partially abutted with some channels
Different types of implementation flow in floorplan are: -
6
1) Flat implementation: - These designs have no subblocks and it only has leaf cells. It takes
less run time in comparison with Hierarchical flow.
Flat-based approach gives advantages in terms of
1. Better Qor.
2. Floorplanning becomes easy with respect to pin placement and the block shape.
3. Few design resources are saved.
Disadvantage of this approach are: -
1. More memory is required.
2. Runtime of design increases.
3. STA constraints require to do more efforts.
4. Verification constraints forms a big effort to do.
2) Hierarchical Implementation: - This implementation divides a floorplan region into sub-
regions. These sub-region problems are then solved independently. By implementing hierarchy
in the form of a multi wave cluster tree, the number of floor planning option is limited and
allows the floor planner to operate on one hierarchical call at a time. The advantage of this type
of implementation are: -
1. It is resistant for change in design
2. Timing can be closed.
3. It can bring consistency.
This flow requires iterations and engineering time. In comparison to flat, this flow has flat run
time and needs less memory for EDA.
Steps to do the floorplan are given as follows [1]: -
1. Size & shape of the block (Usually provided by FC floorplan)
2. Voltage area creation (Power domains)
3. IO placement
4. Creating standard cell rows
5. Macro-placement
6. Adding routing & placement blockages (as required)
7. Adding power switches (Daisy chain)
8. Creating Power Mesh
9. Adding physical cells (Well taps, End Caps, etc.)
10. Placing & qualifying pushdown cells
7
 11. Creating bounds / plan groups / density screens

2.2 Placement
Placement is the process, where for each cell of the black a suitable physical location is
found. In this stage not only, standard cells are placed also, the design gets optimized. Placement
of cells can be dependent on different criteria such as timing driven, congestion driven, power
optimization, etc. Convergence of timing and routing depends very much on quality of
placement. Goals of placement stage are as follows: -
1) Optimization of power, area, and timing.
2) Design should be routable.
3) Pin density, cell density and congestion hot-spots should be as low as possible.
4) Within the design minimal timing DRCs should be present.

2.3 Clock Tree Synthesis

Clock Tree Synthesis (CTS) is a process where it is made sure that all the sequential
elements within the design get equally distributed clock. It is also process of balancing clock
skew, distributing clock signal to clock pins depending upon physical information and meeting
timing and power requirement by minimizing insertion delay. To establish the tree structure
exact location of cells are required hence CTS process is done after placement stage

2.4 Routing
Routing is the process where physical connections are built between block, as it is
defined by the logical connections. Placed cells are connected with metal so that the connectivity
can be reflected in Verilog netlist. Layers are connected using ‘vias’. Global and detailed routing
are two different types of routing that are used within the stage. Also, there are four stages of
routing. They are as follows: -
1) Global routing
2) Track Assignment
3) Detailed routing
4) Search and Repair

8
2.5 Static Timing Analysis
Static Timing Analysis (STA) is a process where the calculation of the expected timing of
the digital circuit is done, without doing any simulation. It checks for timing violation at every
path in the design. But this analysis is not much effective for asynchronous interfaces or
different timing domain interfaces. In this analysis static delays are considered for each path and
then these delays are compared with the path’s required maximum and minimum values.

2.6 Physical Cells

These cells are not standard cells or spare cells. These cells are kept in design to achieve
better qor, avoid congestion and to reduce IR drop. In design netlist, these cells are not present.
Invented for finishing the chip so, they do not appear in timing path reports. These cells are kept
in halos or near standard cell depending upon the type of physical cells. Following are different
type of physical cells [4]: –

1. Tap Cells [5]

Figure 3 Tapping the VDD with N-well and VSS with Psub externally [9]

Well tap cells help in limiting resistance between power or ground connections to wells
of the substrate. To avoid latch – up problem these cells are inserted. The placer put these cells

9
with respect to specified distances and automatically place these cells to their legal locations
(which are the core sites). Taps Cells are used to connect substrate with Vdd and n-wells with
ground as shown in figure 3. The rules for this cell are technology dependent, so it may need to
have well tap for every X microns. It does not contain any logical function, just two connections.
These cells are used for topless cells. In topless cells, well tapping is absent inside the standard
cell hence, it is provided by well tap cells. These cells are placed in pre-placement stage after the
macro-placement and power rail creation. In each row of placement, well tap cells are placed in a
regular interval. These cells are placed in checkerboard pattern so that maximum coverage is
provided for well tap.

2. End Cap Cells [6]

It is also known as boundary cell. During the manufacturing of chip, there are chances
that gate of standard cells, which are placed at boundary gets damaged. Hence, end cap cells
used to avoid damage at boundary. These cells have fixed attribute hence, they cannot be moved
during the optimization. It is kept at both ends of each placement row as shown in figure 4. Also,
to make integration with other blocks, these cells are placed at the top and bottom row of the
block level. Few other reasons for using end cap cells are as follows:
• To make the alignment, proper with the other blocks.
• Few standard cell libraries have end cap cells that work as de-cap cell also.
• For avoiding the base layer DRC at the boundary

Figure 4 End-Cap cells with Site-row [9]

10
 These cells are also called preplaced cell. These are placed before the placement of the
standard cell. These cells are placed after the macro placement and site row creation. These cells
can be added during GUI interface or tool commands.

3. Filler Cells [7]

To establish the continuity of the N-well and the implant layers on the standard cell rows,
filler cells are used. They are also used for some of the small cells that don’t have substrate
connection due to thin cells. Here the abutment of cells by inserting filler cells, connect the
substrate of small cells to power ground net. These cells fill empty space between cells and
aligns the width of each row of standard cells as shown in figure 5.

Figure 5 Filler and De-Cap Cells [9]

11
4. De-cap Cells [8]
De-cap Cells are device that are made of capacitors for storing charge as shown in figure
6. It is used to support the sudden current requirement in the power delivery network. If this
current requirement is not considered, then there may be power drop or ground bounce. This
would lend to an effect on delay of standard cells. Hence de-cap cells are inserted throughout the
design. This dynamic IR drop happens at the active edge of the clock. These cells are placed in
the pre-placement stage, that is after the power planning and before the standard cell placement.
This cell can also be placed at the post route stage. Disadvantage of this cell is that these are
leaky. Hence leading towards increase in the leakage power of design. When current
requirements are high, these cells get discharged and gives boost to the power grid.

Figure 6 De-cap Cells[10]

12
Chapter 3
Software Application
3.1 Fusion Compiler
In this project we are using Fusion complier [11][12] tool for implementing floorplan stage
of physical design. It allows the flow to run using two flavours, depending upon the preference:
1)Classic front-end/Back-end: - It targets a traditional hand off between a front-end
(synthesis) and a back-end (place and route) engineer. It mirrors the traditional design complier,
ICC2 flow Physical Synthesis is done by using “Compile_fusion to initial_opto” and final
placement and optimization is done by using “place-opt” command as seen in figure 7.

Figure 7 Classic Front-end/Back-end Flow

13
 2)Unified RTL-to-GDS II: - In this process physical synthesis, final placement and
optimization stages occur using “compile_fusion” command. Later the flow is continued using
clock-opt, route-auto, route-opt and eco-opt as seen in figure 8. In compile_fusion command

Figure 8 Unified RTL-to-GDS II Flow

mapping and area-based optimization is done followed by logic-based delay optimization. Also,
placement buffer-tree creation and physical optimization for timing, power area is done. In
clock-opt command clock tree synthesis and post-CTS optimization is done. For routing and
post-route optimization, route-auto/route-opt commands are used. For built-in sign-off timing
closure with PrimeTime and StarRC, eco-opt command is used. Compile_fusion command helps
in streamlined flow with fewer iterations of placement and optimization as compared to the
traditional DC and ICC2 flows. This command unifies all pre-route optimization onto common
14
engines, which enables consistent costing in optimization algorithms. Also, it shares the best
synthesis and P&R technologies throughout the full pre-route flow. The compile_fusion
command runs all stages by default. The end result is a legally placed and optimized netlist,
which is then ready for clock-opt. There are seven stages of this command as shown in the below
figure 9.

Figure 9 Compile_fusion Seven Stages

In fusion complier, it is important to keep consistent scenario settings, otherwise QoR

problem emerges. This load gives up to 20% better power, performance, and area. Also it gives
two times faster time-to-result. It removes the requirement of adding excessive design margins
and removes later stage convergence problem while performing sign off stage. It also consists of
physically-aware synthesis. To drive highest frequencies it has advanced CTS. To remove too
many design iterations signoff timings, parasitic extraction and power analysis are done in this
tool. For best utilization, from synthesis to post-route stage advanced area recovery algorithms
are used. This tool process is certified from leading foundries for FinFET and multi-patterning
aware design. For overall convergence this tool performs accurate congestion estimation and
prediction using route-driven estimate. For maximum throughput this tool uses pervasive
parallelization with multi-threaded and distributed processing technologies.

15
Chapter 4
Simulation and Results
To study the impact of physical cells by doing practical, first we need to have a design and
basic knowledge about the design. Also, it is important to do macro placements and standard cell
placements. Here, while studying the impact of the physical cells whole placement and route
flow is performed. So, below are the steps that has been done to study about the physical cell
placement.
4.1 Tap Cells:
I. Change in Orientation of Physical Cells
To understand the impact of change in orientation on whole design, here some tap cells are
placed with different orientation. Here first few cells were placed in MY (as shown in figure 10)
direction, later these cells were changed to R0.

Figure 10 Orientation of Selected Tap Cells

And then the outcome of both the design is compared in terms of total number of DRC
occurred as shown in the table1. Exp_1 shows the result of MY direction and Exp_2 shows the
result of R0 direction. Change in direction leads to change in position of vts_n hence, leading to
discontinuity of n-well. Hence, it can be said that if orientation of physical cells are not kept
properly in the design then there is rise in number of DRC count within the design. In this case,
DRC count increases by 0.01%.

16
 Table 1 Result of Change in Orientation of Tap Cells

Exp_1 Exp_2

DRC Count 253400 253150

II. Change in Physical Cell Count

In this part of the experiment, total cell count of the tap cells is changed to understand
impact in terms of utilization ratio and area. Total number of tap cells present within the design
for one of the experiments is shown in the figure 11.

Figure 11 Tap Cells in the Design

By inserting less or more tap cells within the design, analysis of the results is done. The
results show that as we increase tap cell counts, utilization ratio decreases and tap cell area
increases. Also, it can be seen there is decrease in number of DRC count. Here, increase in DRC
count by decreasing cell count is nearly 3.35% (By taking average of the changes between three
experiment) as shown in table 2.
Table 2 Results of Change in Tap Cells Count

Exp_1 Exp_2 Exp_3

Cell Count 3460 3630 3705

DRC Count 255130 254900 253150

Utilization Ratio 0.244 0.2428 0.2300

TAP cell area 760.20032 795.97216 810.9504

17
4.2 End-cap Cells:
I. Change in Orientation of Physical Cells
To understand the impact of change in orientation on whole design, here some end-cap cells
are placed with different orientation. Here first few cells were placed in MY (as shown in figure
12) direction, later these cells were changed to R0.

SSSssSSSSsSS

Figure 12 Orientation of Selected End-Cap Cells

And then the outcome of both the design is compared in terms of total number of DRC
occurred as shown in the table1. Exp_1 shows the result of MY direction and Exp_2 shows the
result of R0 direction. Change in direction leads to change in position of vts_n hence, leading to
discontinuity of n-well. Hence, it can be said that if orientation of physical cells are not kept
properly in the design then there is rise in number of DRC count within the design. In this case,
DRC count increases by 66%.
Table 3 Result of Change in Orientation of End-Cap Cells

Exp_1 Exp_2

DRC Count 762216 253150

II. Change in Physical Cell Count

In this part of the experiment, total cell count of the end-cap cells is changed to understand
impact in terms of utilization ratio and area. Total number of end-cap cells present within the
design for one of the experiments is shown in the figure13.
18
 Figure 13 End-Cap Cells in the Design

By inserting less or more end-cap cells within the design, analysis of result is done. The
results show that as we increase end-cap cell counts, utilization ratio decreases and tap cell area
increases. Also, it can be seen there is decrease in number of DRC count. Here, increase in DRC
count by decreasing cell count is nearly two times as shown in table 4.
Table 4 Results of Change in End-Cap Cells Count

Exp_1 Exp_2 Exp_3

Cell Count 13635 15400 16218

DRC Count 874200 451982 253150

Utilization Ratio 0.2640 0.2497 0.2300

DCAP cell area 1545.13136 1737.96192 1830.1952

4.3 Filler Cells:

I. Change in Orientation of Physical Cells
To understand the impact of change in orientation on whole design, here some end-cap
cells are placed with different orientation. Here first few cells were placed in MX direction, later
these cells were changed to R0 (as shown in figure 14).

19
 Figure 14 Orientation of Selected Filler Cell

And then the outcome of both the design is compared in terms of total number of DRC
occurred as shown in the table1. Exp_1 shows the result of MX direction and Exp_2 shows the
result of R0 direction. Change in direction leads to change in position of vts_n hence, leading to
discontinuity of n-well. Hence, it can be said that if orientation of physical cells are not kept
properly in the design then there is rise in number of DRC count within the design. In this case,
DRC count increases by 72.60%.
Table 5 Result of Change in Orientation of Filler Cells

Exp_1 Exp_2

DRC Count 745 204

II. Change in Physical Cell Count

In this part of the experiment, total cell count of the filler cells is changed to understand
impact in terms of utilization ratio and area. Total number of filler cells present within the design
for one of the experiments is shown in the figure 15.

20
 By inserting less or more filler cells within the design study is done. The results show that as
we increase filler cell counts, utilization ratio decreases, and filler cell area increases.

Figure 15 Filler Cells in the Design

Also, it can be seen there is decrease in number of DRC count. Here, increase in DRC count
is seen by decreasing cell count, as shown in table 6. The increase in DRC count mainly occur
due to n-well discontinuity.
Table 6 Results of Change in Filler Cells Count

Exp_1 Exp_2 Exp_3

Cell Count 225047 312213 313456

Utilization Ratio 96.140 99.983 100.000

DRC Count 8,96,979 26,440 204

III. Change in Spacing Between Standard Cell

In this part of the experiment, spacing between standard cell are changed to study the impact
of these standard cell on filler cell. When the standard cell placing would not be optimized then
there are chance that less filler cells are placed within the design.

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 Figure 16 COD.H.R.5 and OD.R.9 Design Rule Check

In some cases, improper spacing between standard cell may lead to increase in DRC as filler
cells are not been place in small spaces as shown in figure 16. Hence, his leads to n-well
discontinuity. Here only spacing of three standard cells are changed and the impact can be seen
within the result as shown in table 7.

Table 7 Result of Change in Space between Standard Cell

Exp_1 Exp_2

DRC Count 40267 204

4.4 De-cap Cells:

I. Change in Physical Cell Count
By inserting less or more de-cap cells within the design study is done. Here total number of de-
cap cells are present within the design for one of the experiments is shown in figure 17. The
results show that as we increase de-cap cell count, de-cap cell area increases. Also, it can be seen
there is decrease in number of DRC count.

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 Figure 17 De-Cap Cells in the Design

Here increase in DRC count by decreasing cell count is seen in table 8. There is increase in
DRC counts as n-well discontinuity occur at different place of design. As far as impact of de-cap
cell is considered on the total dynamic power, de-cap cells are known for reducing dynamic
power. But after a certain amount of increase in cell count, we can see increase in dynamic
power also as shown in table 8.
Table 8 Results of Change in De-Cap Cells Count

Exp_1 Exp_2 Exp_3

Cell Count 166056 263035 265024

Area(um2) 18221.04832 28359.5152 28694.45632

DRC Count 265072 139857 204

Total Dynamic Power (mW) 32.563 32.562 32.563

Net Switching Power (mW) 12.643 12.642 12.643

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Chapter 5
Conclusions and Future Scope
5.1 Conclusion
In this report, different types of physical cells were studied. That helped in understanding,
which physical cells are placed before placement stage and which are placed after routing stage.
These physical cells have impact on power, area, and performance. For tap cell, orientation is
one factor which, if not placed correctly can increase in DRC count due to discontinuity of N-
well. Other factor for tap cells is count of the cells used within the design. There is increase in
number of DRC around 3.35% as we decrease the number of well-tap cells used within the
design. For end-cap cell, if the orientation of cell is not correct then, there is increase in the
number of DRC. Here, the increase is 66% when only 21 cells were wrongly placed within the
design. Also, as the number of end-cap cells decreases within the design number of DRC
increases. For filler cell, if space optimization between standard cell is not done properly then
there is decrease in number of filler cells placed. As well as there might be increase in number of
DRC if space between two standard cells is not enough to place a filler cell. The number of DRC
value increases as orientation of filler cells are not correct as required within the design. For de-
cap cells, there is decrease in dynamic power when de-cap cells are increased but after a certain
number of increases in de-cap cells, dynamic power also increases. Hence, for all the physical
cell it is important that the orientation of the cell is correct. If these physical cells are not placed
properly or in the absence of the physical cell within the design, there would be degradation in
the quality of chip.

5.2 Future Scope

Further in this project, impact of tie-cell can be studied. Also, impact of de-cap
cells with IR drop analysis at lower technology node can be done.

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