INSTITUTE OF AERONAUTICAL ENGINEERING

(AUTONOMOUS)
Dundigal, Hyderabad – 500 043

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1 Name of the student Tangturi.Jeshwanth Goud

2 Email ID and Phone Number 24955A608@iare.ac.in,PH-8121456954

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4 Date of submission 14/12/2024

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 INSTITUTE OF AERONAUTICAL
ENGINEERING

AN ASSIGNMENT REPORT OF
COMPUTER SYSTEM AND ARCHITECTURE
COURSE CODE- AECD04
BY
JESHWANTH GOUD
24955A6608
ARTIFICIAL INTELLIGENCE AND
MACHINE LEARNING

INSTUTE OF AERONAUTICAL
ENGINEERING DUNDIGAL, HYDERABAD
–043, TELANGANA, INDIA.
1. Control memory and micro programmed organization are to be constructed
from control memory
Control memory is an essential part of micro-programmed control organization, as it stores
the micro-instructions that define the control signals. A micro-programmed control
organization consists of the following components:
1. Control Memory: A ROM or RAM stores micro-instructions that represent sequences of
control signals.
2. Address Register: Holds the address of the next micro-instruction to execute.
3. Sequencer: Determines the next address based on conditions or counters.
4. Control Data Register: Holds the micro-instruction retrieved from control memory.

Micro-programmed control makes the design of the control unit easy to implement and
flexible and easy to update. For instance, the microprogram can be changed to
accommodate other sets of instructions without changing the hardware. It is slower than
hardwired control because of the time required to access memory.

2. Identify micro program example and build a computer hardware

configuration
A microprogram is a sequence of micro-instructions stored in control memory, used to
execute machine instructions. For example, consider a CPU executing an **ADD**
instruction:

1. Fetch: Load the instruction into the instruction register (IR).

2. Decode: Determine the operation (ADD) and operands.
3. Execute:
- Read values from source registers.
- Perform addition using ALU.

The hardware configuration includes:

1. Control Memory: Stores the micro-instructions.

2. Control Unit: Generates signals based on micro-instructions.
3. Arithmetic Logic Unit (ALU): Performs computations.
4. Registers: Temporarily store data and instructions.

Microprogramming makes it easier to implement complex instruction sets and improves

flexibility.

3. Illustrate memory unit function

A memory unit serves as the central storage for data and instructions required during
computation. The key functions of a memory unit are:
1. Data Storage: It temporarily or permanently stores data and instructions. For instance,
primary memory or RAM stores data that are currently in use.
2. Read Operation: The CPU fetches data from memory to registers for processing.
3. Write Operation: Data is stored back to memory after computation.

Memory units are organized hierarchically:

- Cache Memory: Provides fast access to frequently used data.

- Primary Memory (RAM): Temporary storage for the active processes are known as the
RAM.
- Secondary Storage (HDD/SSD): Data storage for a long time.

Good memory management will result in a smooth and faster system.

4. Compare the various types of ROMs.

ROM (Read-Only Memory) is a type of non-volatile memory where data is stored
permanently. The types of ROMs are:
1. Mask ROM:
- It is programmed during manufacturing.
- Advantages: Cost-effective for large production.
- Limitation: It cannot be reprogrammed.

2. PROM (Programmable ROM):

- Programmed only once in their life cycle, post their manufacturing.
- Utilizes fuses to store information permanently.

3. EPROM (Erasable Programmable ROM):

- Erased using ultraviolet light and reprogrammed after erasure.
- Advantage: Reusable.

4. EEPROM (Electrically Erasable Programmable ROM):

- Uses electricity to erase and rewrite data.
- Used in BIOS firmware.

5. Flash Memory:
- A type of EEPROM with faster read/write operations.
- Applications: USB drives, SD cards, SSDs.

5. Describe the advantages and disadvantages of daisy chaining priority

interrupts compared to parallel priority interrupts.
In daisy chaining priority interrupts, devices are connected serially, and physical order
determines their priority:

Advantages:
1. Simple and cost-effective.
2. Requires minimal hardware.
3. Best for small systems.
Disadvantages:
1. Lower-priority devices face delays.
2. Single-point failure disrupts the chain.

In parallel priority interrupts, each device has its own interrupt line:

Advantages:
1. Faster response time.
2. Independent of device order.

Disadvantages:
1. Requires more hardware.
2. Expensive to implement.

Daisy chaining suits small systems, while parallel priority is ideal for complex, high-speed
systems.

6. Compare and contrast daisy chaining priority and parallel priority interrupt
systems.
Daisy Chaining Priority:
Advantages:
1. Simple to implement.
2. Requires less hardware.

Disadvantages:
1. High-priority devices delay lower-priority ones.
2. Single-point failure issue.

Parallel Priority:
Advantages:
1. Faster response time.
2. Independent priority assignments.

Disadvantages:
1. Complex hardware.
2. Expensive to implement.

Daisy chaining is best for small systems, while parallel priority is ideal for real-time, high-
speed systems.

7. Describe the operation of a 16-megabyte DRAM chip organized as 1M x 6

memory chips.
A 16-megabyte DRAM chip organized as 1M x 6 works as follows:
1. Each 1M x 6 chip provides 1 Megabit storage with 6 bits per row.
2. To achieve 16 MB, chips are arranged to fulfill the requirement:
 - Combining chips for byte access (6 + 6 bits = 12 bits).
- Extra bits can be used for error checking (ECC).

Row and column addresses are multiplexed to minimize address lines, balancing cost and
efficiency.

8. Explain the fundamental differences between Static RAM (SRAM) and

Dynamic RAM (DRAM) in terms of structure, performance, and use cases. In
what should be the scenarios would one of the be preferred over the other?
SRAM:
- Structure: Uses flip-flop circuits.
- Speed: Faster access time (10-20 ns).
- Power: Requires continuous power.
- Use: Cache memory.

DRAM:
- Structure: Uses capacitor-transistor combination.
- Speed: Slower due to refresh cycles (50-100 ns).
- Power: Consumes less standby power.
- Use: Main memory.

SRAM is preferred where speed is critical (e.g., CPU cache), while DRAM is used for large,
cost-effective memory (e.g., main memory).

9. Draw and describe data path modified for pipelined execution.

Data Path Modified for Pipelined Execution

In pipelined execution, the data path is divided into 5 stages to enable multiple instructions
to execute simultaneously, enhancing CPU throughput.

1. Instruction Fetch (IF):

o Fetch the instruction from memory using the Program Counter (PC).

2. Instruction Decode (ID):

o Decode the instruction and determine the source/destination registers.

3. Execute (EX):

o Perform operations using the ALU, such as arithmetic or logical operations.

4. Memory Access (MEM):

o Read or write data to/from memory for load/store instructions.

5. Write Back (WB):

Pipeline Execution Example

In each clock cycle, several instructions execute in parallel:

•Clock 1: IF1

•Clock 2: IF2 → ID1

•Clock 3: IF3 → ID2 → EX1

This pipelining increases the efficiency and completes one instruction per cycle after the
pipeline is filled.

Advantages: Improved performance and throughput.

Disadvantages: Hazards such as structural, data, and control hazards.

10. Describe instruction pipelining.

Instruction Pipelining

Instruction pipelining is the technique utilized by modern CPUs in order to provide

improved performance due to instruction processing in pipelined sequence. This divides the
whole process of executing an instruction into stages smaller in numbers, each performing a
section of the instruction. Consequently, various instructions will be different pipeline
stages, enhancing the throughput.

Pipeline Stages

1.Instruction Fetch (IF):

o The CPU fetches the instruction from memory using the Program Counter (PC) and stores
it in the Instruction Register (IR).

2. Instruction Decode (ID):

o The fetched instruction is decoded to identify the operation and source/destination

registers.

3. Execute (EX):

o The Arithmetic Logic Unit (ALU) performs computations or evaluates conditions for
branch instructions.

4. Memory Access (MEM):

o For load/store instructions, the memory is accessed to fetch or store data.

5. Write Back (WB):

Working of Instruction Pipelining

•Parallel Execution: Each stage processes a different instruction simultaneously.

•For example, during the 3rd clock cycle:

oInstruction 1 is in the MEM stage.

oInstruction 2 is in the EX stage.

oInstruction 3 is in the ID stage.

oInstruction 4 is in the IF stage.

This overlapping of stages reduces idle time and improves the instruction throughput.

Advantages of Instruction Pipelining:

1. Increased Performance: More instructions are executed in parallel, thus increasing the
throughput of instructions.

2. Better Hardware Utilization: At any instant, a hardware unit is performing one task.

3. Faster Execution: Instructions are executed faster because new instructions start
execution without waiting for the previous ones to complete.

Hazards (Pipeline Hazards):

1. Structural Hazard: It occurs when hardware resources are shared between stages.

2. Data Hazard: It occurs when instructions depend on data from previous instructions.

3.Control Hazard: This happens during branch or jump instructions, where the next
instruction is dependent on a condition.