MKT2802
Logic Circuits
Department of Mechatronics Engineering
Fall : 2024
3/25/2024 1
Combinational Circuits
• Logic circuits for digital systems may be classified as;
– Combinational
– Sequential
• A combinational circuit consists of logic gates whose outputs at any time are
determined by the current input values, i.e., arithmetic circuits
it has no memory elements
• A sequential circuit consists of logic gates whose outputs at any time are
determined by the current input values, the past input values and/or past output
values, i.e., counters
it has memory elements
3/25/2024 2
Combinational Circuits
• Each input and output variable is a binary variable
• 2n possible binary input combinations
• One possible binary value at the output for each input combination
• A truth table or Boolean functions can be used to specify input-
output relation
3/25/2024 3
Design Procedure for Combinational Circuits
The design of a combinational circuit involves the following steps:
– Specification: How the circuit operates is clearly expressed
– Formulation: Derivation of the truth table or the Boolean equations that
define the relationship between inputs and outputs
– Optimization: Algebraic or K-map optimization of the truth table and
drawing the corresponding logic diagram
– Technology Mapping: Transforming the logic diagram to a new diagram
using the available implementation technology
– Verification: Verifying the correctness of the final design
3/25/2024 4
Design Procedure for Combinational Circuits
3/25/2024 5
Design Procedure for Combinational Circuits
3/25/2024 6
Design Procedure for Combinational Circuits
3/25/2024 7
Design Procedure for Combinational Circuits
3/25/2024 8
Types of Combinational Circuits
Types of Combinational Circuits
Arithmetic circuits (adders, subtractors,…)
Codders/Decoders
Multiplexers/Demultiplexers
Comparators
And other circuits …
3/25/2024 9
Half Adder – HA
The half-adder accepts two binary digits on its inputs and produces two
binary digits on its outputs, a sum bit and a carry bit.
3/25/2024 10
Full Adder – FA
The full-adder accepts two input bits and an input carry and generates a sum
output and an output carry
3/25/2024 11
Full Adder – FA
3/25/2024 12
PARALLEL BINARY ADDERS
• Two or more full-adders are connected to form parallel binary adders.
• To add two binary numbers, a full-adder is required for each bit in the numbers. So for 2-
bit numbers, two adders are needed; for 4-bit numbers, four adders are used; and so on.
The carry output of each adder is connected to the carry input of the next higher-order
adder, as shown in Figure for a 2-bit adder.
• Notice that either a half-adder can be used for the least significant position or the carry
input of a full-adder can be made 0 (grounded) because there is no carry input to the least
significant bit position.
3/25/2024 13
Four-Bit Parallel Adders
3/25/2024 14
Adder Expansion
The 4-bit parallel adder can be expanded to handle the addition of two 8-bit numbers by
using two 4-bit adders. The carry input of the low-order adder (Co) is connected to ground
because there is no carry into the least significant bit position, and the carry output of the
low-order adder is connected to the carry input of the high-order adder, as shown in
Figure.
3/25/2024 15
Half Subtractor - HS
3/25/2024 16
Full Subtractor
3/25/2024 17
Full Subtractor – FS
3/25/2024 18
PARALLEL BINARY SUBTRACTOR
Two or more full-subtractors are connected to form parallel binary subtractors.
A half subtractor can be
used in first level!!! Since
there is no need for
borrow!!!
3/25/2024 19
Subtraction by Complement Methods
Take 2’s complement of
subtrahend number
Sum up minuend and
complemented number
Observe the result
Clear MSD, rest of the result YES Number of digit of resulted
number is the expected
grater than highest digit
result
number?
NO
Find 2’s complement of
result number and put – sign
in front of result ! This is the
expected result
3/25/2024 20
Subtraction by Complement Methods
Take 1’s complement of the
subtrahend number
Sum up them inuend and the
complemented number
Observe the result
Clear MSD, add 1 to rest of YES Number of digit of the result
the result, this is the
grater than the highest digit
expected result
number?
NO
Find 1’s complement of the
result and put – sign in front
of the result! This is the
expected result
3/25/2024 21
Subtraction by Complement Methods
3/25/2024 22
Combinational Circuits
3/25/2024 23
Binary Multiplication
3/25/2024 24
Binary Multiplication
3/25/2024 25
Decoders
3/25/2024 26
Decoders
3/25/2024 27
Decoders
3/25/2024 28
Example: 2-to-4 decoders
3/25/2024 29
Example: 2-to-4 decoders
3/25/2024 30
Example: 2-to-4 decoders
3/25/2024 31
Example: Enabled 2-to-4 decoders
3/25/2024 32
Example: 3-to-8 decoders
3/25/2024 33
Example: 3-to-8 decoders
3/25/2024 34
Example: 3-to-8 decoders
3/25/2024 35
Decoder Expansion
3/25/2024 36
Decoder Expansion
3/25/2024 37
Decoder design with NAND gates
3/25/2024 38
Combinational Circuits
3/25/2024 39
Combinational circuit implementation using decoder
3/25/2024 40
Example: Decoder Implementation of a Full Adder
3/25/2024 41
Example: Decoder Implementation of a Full Adder
3/25/2024 42
Encoders
3/25/2024 43
Example: Octal-to-binary encoder
3/25/2024 44
Combinational Circuits
3/25/2024 45
Major Limitation of Encoders
3/25/2024 46
Major Limitation of Encoders
3/25/2024 47
Example: 4-to-2 Priority Encoders
3/25/2024 48
Example: 4-to-2 Priority Encoders
The truth table can be rewritten in a more
compact form using don’t care conditions
for inputs as shown below in table
With don’t care input conditions, the
number of rows can be reduced since
rows with don’t care inputs will actually
represent more than one input
combination.
3/25/2024 49
Example: 4-to-2 Priority Encoders
3/25/2024 50
Example: 4-to-2 Priority Encoders
3/25/2024 51
Any Comment or Question???
3/25/2024 52
