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LMH6657, LMH6658
SNOSA35G – AUGUST 2002 – REVISED JULY 2015

LMH6657 and LMH6658 270-MHz Single Supply, Single and Dual Amplifiers
1 Features 3 Description
VS = 5 V, TA = 25°C, RL = 100 Ω (Typical Values
1
The LMH6657 and LMH6658 devices are low-cost
Unless Specified) operational amplifiers that operate from a single
supply with input voltage range extending below the
• −3dB BW (AV = +1) 270 MHz V−. Based on easy to use voltage feedback topology
• Supply Voltage Range 3 V to 12 V and boasting fast slew rate (700 V/µs) and high
• Slew Rate, (VS = ±5 V) 700 V/µs speed (140 MHz GBWP), the LMH6657 (Single) and
LMH6658 (dual) can be used in high speed large
• Supply Current 6.2 mA/amp
signal applications. These applications include
• Output Current +80/−90 mA instrumentation, communication devices, set-top
• Input Common-Mode Volt. 0.5 V Beyond V−, 1.7 V boxes, and so forth.
from V+ With a -3dB BW of 100 MHz (AV = +2) and DG & DP
• Output Voltage Swing (RL = 2 kΩ) 0.8 V from of 0.03% & 0.10° respectively, the LMH6657 and
Rails LMH6658 are well suited for video applications. The
• Input Voltage Noise 11 nV/√Hz output stage can typically supply 80 mA into the load
with a swing of about 1 V from either rail.
• Input Current Noise 2.1 pA√Hz/
• DG Error 0.03% For Industrial applications, the LMH6657 and
LMH6658 are excellent cost-saving choices. Input
• DP Error 0.10° referred voltage noise is low and the input voltage
• THD (5MHz) −55 dBc can extend below V− to ease amplification of low level
• Settling Time (0.1%) 37ns signals that could be at or near the system ground.
With low distortion and fast settling, LMH6657 and
• Fully Characterized for 5 V, and ±5 V LMH6658 can provide buffering for A/D and D/A
• Output Overdrive Recovery 18 ns applications.
• Output Short Circuit Protected(1) The LMH6657 and LMH6658 versatility and ease of
• No Output Phase Reversal With CMVR Exceeded use is extended even further by offering these high
slew rate, high-speed operational amplifiers in
2 Applications miniature packages such as SOT-23-5, SC70, SOIC-
8, and VSSOP-8.
• CD/DVD ROM
• ADC Buffer Amps Device Information(1)
• Portable Video PART NUMBER PACKAGE BODY SIZE (NOM)
• Current Sense Buffers SC70 (5) 2.00 mm × 1.25 mm
LMH6657
• Portable Communications SOT-23 (5) 2.90 mm × 1.60 mm
(1) Short Circuit Test is a momentary test. SOIC (8) 4.90 mm × 3.91 mm
LMH6658
See Note 3 under Absolute Maximum Ratings. VSSOP (8) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Noninverting Frequency Response, Gain Noninverting Frequency Response, Phase

0
AV = +1
0 -50 AV = +10
-1 AV = +10
AV = +5
AV = +5 -100
PHASE
GAIN

AV = +2
-3
AV = +2
-150
AV = +1
-5
VS = ±2.5V VS = ±2.5V
-200
RL = 100: RL = 100:
-7
VOUT = 200mVPP VOUT = 200mVPP

1M 10M 100M 500M 1M 10M 100M 500M

FREQUENCY (Hz) FREQUENCY (Hz)
1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6657, LMH6658
SNOSA35G – AUGUST 2002 – REVISED JULY 2015 www.ti.com

Table of Contents
1 Features .................................................................. 1 7.3 Device Functional Modes........................................ 18
2 Applications ........................................................... 1 8 Application and Implementation ........................ 19
3 Description ............................................................. 1 8.1 Application Information............................................ 19
4 Revision History..................................................... 2 9 Power Supply Recommendations...................... 20
5 Pin Configuration and Functions ......................... 3 10 Layout................................................................... 20
6 Specifications......................................................... 4 10.1 Layout Guidelines ................................................. 20
6.1 Absolute Maximum Ratings ...................................... 4 10.2 Layout Example .................................................... 21
6.2 ESD Ratings.............................................................. 4 11 Device and Documentation Support ................. 23
6.3 Recommended Operating Conditions....................... 4 11.1 Documentation Support ........................................ 23
6.4 Thermal Information .................................................. 4 11.2 Related Links ........................................................ 23
6.5 Electrical Characteristics, 5 V .................................. 5 11.3 Community Resources.......................................... 23
6.6 Electrical Characteristics, ±5 V ................................ 7 11.4 Trademarks ........................................................... 23
6.7 Typical Characteristics .............................................. 9 11.5 Electrostatic Discharge Caution ............................ 23
7 Detailed Description ............................................ 17 11.6 Glossary ................................................................ 23
7.1 Overview ................................................................. 17 12 Mechanical, Packaging, and Orderable
7.2 Feature Description................................................. 17 Information ........................................................... 23

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (April 2013) to Revision G Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

Changes from Revision E (March 2013) to Revision F Page

• Changed layout of National Data Sheet to TI format ............................................................................................................. 1

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5 Pin Configuration and Functions

DBV and DCK Package

5-Pin SOT-23 and SC70 D and DGK Package
Top View 8-Pin SOIC and VSSOP
Top View

1 5 +
OUTPUT V 1 8 +
OUT A V

A
- +
2 7
-IN A OUT B
- 2
V

+ - 3 6
+IN A B -IN B

4 + -
3 -IN
+IN
- 4 5
V +IN B

Pin Functions
PIN
NO.
I/O DESCRIPTION
NAME SOT-23 SOIC AND
AND SC70 VSSOP
OUTPUT 1 — O Output
–IN 4 — I Inverting input
+IN 3 — I Noninverting input
OUT A — 1 O Output A
–IN A — 2 I Inverting input A
+IN A — 3 I Noninverting input A
–
V 2 4 I Negative Supply
OUT B — 7 O Output B
–IN B — 6 I Inverting input channel B
+IN B — 5 I Noninverting input channel B
V+ 5 8 I Positive supply

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VIN Differential ±2.5 V
(2) (3)
Output Short Circuit Duration See
Input Current ±10 mA
Supply Voltage (V+ - V−) 12.6 V
− +
Voltage at Input/Output pins V − 0.8 V + 0.8 V
Infrared or Convection (20 sec.) 260
Soldering Information °C
Wave Soldering (10 sec.) 260
Storage temperature, Tstg –65 100 °C
Junction Temperature (4) 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
(3) Output short circuit duration is infinite for VS < 6 V at room temperature and below. For VS > 6 V, allowable short circuit duration is
1.5ms.
(4) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/ RθJA . All numbers apply for packages soldered directly onto a PCB.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (2) ±2000
V(ESD) Electrostatic discharge V
Machine Model (3) ±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±2000 V may actually have higher performance.
(2) Human body model, 1.5 kΩ in series with 100 pF.
(3) Machine Model, 0 Ω in series with 200 pF.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
+ −
Supply Voltage (V – V ) 3 12 V
Operating Temperature (1) −40 85 °C

(1) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/ RθJA . All numbers apply for packages soldered directly onto a PCB.

6.4 Thermal Information

LMH6657 LMH6658
DBV (SOT- DGK
THERMAL METRIC (1) DCK (SC70) D (SOIC) UNIT
23) (VSSOP)
5 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance (2) 265 478 190 235 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/ RθJA . All numbers apply for packages soldered directly onto a PCB.

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6.5 Electrical Characteristics, 5 V

Unless otherwise specified, all limits ensured for at TJ = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2, and RL = 100Ω (or as
specified) tied to V+/2.
PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT
GB Gain Bandwidth Product VOUT < 200 mVPP 140 MHz
AV = +1, VOUT = 200 mVPP 220 270
SSBW −3-dB BW MHz
AV = +2 or −1, VOUT = 200 mVPP 100
Frequency Response AV = +2, VOUT = 200 mVPP, 1.5
GFP dB
Peaking DC to 100 MHz
Frequency Response AV = +2, VOUT = 200 mVPP, 0.5
GFR dB
Rolloff DC to 100 MHz
LPD1° 1° Linear Phase Deviation AV = +2, VOUT = 200 mVPP, ±1° 30 MHz
GF0.1dB 0.1-dB Gain Flatness AV = +2, ±0.1 dB, VOUT = 200 mVPP 13 MHz
PBW Full Power Bandwidth −1 dB, VOUT = 3 VPP, AV = −1 55 MHz
DG Differential Gain NTSC, VCM = 2 V, RL = 150 Ω to V+/2, Pos. Video Only 0.03%
DP Differential Phase NTSC, VCM = 2 V, RL=150 Ω to V+/2 Pos. Video Only 0.1 deg
TIME DOMAIN RESPONSE
AV = +2, VOUT = 500 mVPP 3.3
tr Rise and Fall Time ns
AV = −1, VOUT = 500 mVPP 3.4
OS Overshoot, Undershoot AV = +2, VOUT = 500 mVPP 18%
ts Settling Time VO = 2 VPP, ±0.1%, RL = 500 Ω to V+/2, AV = −1 37 ns
AV = −1, VO = 3VPP (4) 470
SR Slew Rate (3) V/µs
AV = +2, VO = 3VPP (4) 420
DISTORTION AND NOISE RESPONSE
HD2 2nd Harmonic Distortion f = 5MHz, VO = 2VPP, AV = -1 −70 dBc
HD3 3rd Harmonic Distortion f = 5MHz, VO = 2VPP, AV = -1 −57 dBc
THD Total Harmonic Distortion f = 5MHz, VO = 2VPP, AV = -1 −55.5 dBc
Vn Input-Referred Voltage f = 100KHz 11
Noise nV/√Hz
f = 1KHz 19
In Input-Referred Current f = 100KHz 2.1
Noise pA/√Hz
f = 1KHz 7.5
XTLKA Cross-Talk Rejection f = 5MHz, RL (SND) = 100Ω 69
dB
(LMH6658) RCV: RF = RG = 1k
STATIC, DC PERFORMANCE
VO = 1.25V to 3.75V, 85 95
RL = 2k to V+/2
VO = 1.5V to 3.5V, 75 85
AVOL Large Signal Voltage Gain dB
RL = 150Ω to V+/2
VO = 2V to 3V, 70 80
RL = 50Ω to V+/2
CMRR ≥ 50dB −0.2 −0.5
Input Common-Mode At the temperature extremes −0.1
CMVR V
Voltage Range 3 3.3
At the temperature extremes 2.8
±1.1 ±5
VOS Input Offset Voltage mV
At the temperature extremes ±7
Input Offset Voltage See (5) ±2
TC VOS μV/C
Average Drift

(1) All limits are ensured by testing or statistical analysis.

(2) Typical values represent the most likely parametric norm.
(3) Slew rate is the "worst case" of the rising and falling slew rates.
(4) Output Swing not limited by Slew Rate limit.
(5) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
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Electrical Characteristics, 5 V (continued)

Unless otherwise specified, all limits ensured for at TJ = 25°C, V+ = 5 V, V− = 0 V, VCM = VO = V+/2, and RL = 100Ω (or as
specified) tied to V+/2.
PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT
See (6) −5 −20
IB Input Bias Current μA
At the temperature extremes −30
Input Bias Current See (5) 0.01
TC IB nA/°C
Average Drift
50 300
IOS Input Offset Current nA
At the temperature extremes 500
Common-Mode Rejection VCM Stepped from 0V to 3.0V 72 82
CMRR dB
Ratio
Positive Power Supply V+ = 4.5V to 5.5V, VCM = 1V 72 82
+PSRR dB
Rejection Ratio
Supply Current (per No load 6.2 8.5
IS mA
channel) At the temperature extremes 10
MISCELLANEOUS PERFORMANCE
RL = 2k to V+/2 4.1 4.25
At the temperature extremes 3.8
Output Swing RL = 150Ω to V+/2 4 4.19
VOH V
High At the temperature extremes 3.7
RL = 75Ω to V+/2 3.85 4.15
At the temperature extremes 3.5
RL = 2k to V+/2 900 800
At the temperature extremes 1100
Output Swing RL = 150Ω to V+/2 970 870
VOL mV
Low At the temperature extremes 1200
R L = 75Ω to V+/2 990 885
At the temperature extremes 1250
VOUT = 1V from either Sourcing 40 85
IOUT Output Current rail mA
Sinking –40 105
Sourcing to V+/2 100 155
Output Short At the temperature extremes 80
ISC mA
CircuitCurrent (7) Sinking to V+/2 100 220
At the temperature extremes 80
Common-Mode Input 3
RIN MΩ
Resistance
Common-Mode Input 1.8
CIN pF
Capacitance
ROUT Output Impedance f = 1MHz, AV = +1 0.06 Ω

(6) Positive current corresponds to current flowing into the device.

(7) Short circuit test is a momentary test. See Note 3 under Absolute Maximum Ratings.

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6.6 Electrical Characteristics, ±5 V

Unless otherwise specified, all limits ensured for at TJ = 25°C, V+ = 5 V, V− = −5 V, VCM = VO, and RL = 100 Ω (or as
specified) tied to 0 V.
PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT
GB Gain Bandwidth Product VOUT < 200 mVPP 140 MHz
AV = +1, VOUT = 200 mVPP 220 270
SSBW −3-dB BW MHz
AV = +2 or −1, VOUT = 200 mVPP 100
Frequency Response AV = +2, VOUT = 200 mVPP, 1
GFP dB
Peaking DC to 100 MHz
Frequency Response AV = +2, VOUT = 200 mVPP, 0.9
GFR dB
Rolloff DC to 100 MHz
LPD1° 1° Linear Phase Deviation AV = +2, VOUT = 200mVPP, ±1° 30 MHz
GF0.1dB 0.1-dB Gain Flatness AV = +2, ±0.1 dB, VOUT = 200 mVPP 20 MHz
PBW Full Power Bandwidth −1 dB, VOUT = 8 VPP, AV = −1 30 MHz
DG Differential Gain NTSC, RL = 150 Ω, Pos. or Neg. Video 0.03%
DP Differential Phase NTSC,RL = 150 Ω, Pos. or Neg. Video 0.1 deg
TIME DOMAIN RESPONSE
AV = +2, VOUT = 500 mVPP 3.3
tr Rise and Fall Time ns
AV = −1, VOUT = 500 mVPP 3.3
OS Overshoot, Undershoot AV = +2, VOUT = 500 mVPP 16%
VO = 5 VPP, ±0.1%, RL =500 Ω, 35 ns
ts Settling Time
AV = −1
AV = −1, VO = 8 VPP 700
SR Slew Rate (3) V/µs
AV = +2, VO = 8 VPP 500
DISTORTION AND NOISE RESPONSE
HD2 2nd Harmonic Distortion f = 5 MHz, VO = 2 VPP, AV = -1 −70 dBc
rd
HD3 3 Harmonic Distortion f = 5 MHz, VO = 2 VPP, AV = -1 −57 dBc
THD Total Harmonic Distortion f = 5 MHz, VO = 2 VPP, AV = -1 −55.5 dBc
Input-Referred Voltage f = 100 KHz 11
Vn nV/√Hz
Noise f = 1 KHz 19
Input-Referred Current f = 100 KHz 2.1
In pA/√Hz
Noise f = 1 KHz 7.5
Cross-Talk Rejection f = 5 MHz, RL (SND) = 100 Ω 69
XTLKA dB
(LMH6658) RCV: RF = RG = 1 k
STATIC, DC PERFORMANCE
VO = −3.75 V to 3.75 V, RL = 2 k 87 100
AVOL Large Signal Voltage Gain VO = −3.5 V to 3.5 V, RL = 150 Ω 80 90 dB
VO = −3 V to 3 V, RL = 50 Ω 75 85
CMRR ≥ 50 dB −5.2 −5.5
Input Common-Mode At the temperature extremes −5.1
CMVR V
Voltage Range 3 3.3
At the temperature extremes 2.8
±1 ±5
VOS Input Offset Voltage mV
Apply at the temperature extremes ±7
(4)
Input Offset Voltage See ±2 μV/C
TC VOS
Average Drift

(1) All limits are ensured by testing or statistical analysis.

(2) Typical values represent the most likely parametric norm.
(3) Slew rate is the "worst case" of the rising and falling slew rates.
(4) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
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Electrical Characteristics, ±5 V (continued)

Unless otherwise specified, all limits ensured for at TJ = 25°C, V+ = 5 V, V− = −5 V, VCM = VO, and RL = 100 Ω (or as
specified) tied to 0 V.
PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT
(5)
See −5 −20
IB Input Bias Current μA
At the temperature extremes −30
(4)
Input Bias Current See 0.01 nA/°C
TCIB
Average Drift
50 300
IOS Input Offset Current nA
At the temperature extremes 500
Common-Mode Rejection VCM Stepped from −5 V to 3 V 75 84
CMRR dB
Ratio
Positive Power Supply V+ = 4.5 V to 5.5 V, VCM = −4 V 75 82 dB
+PSRR
Rejection Ratio
Negative Power Supply V− = −4.5 V to −5.5 V 78 85 dB
−PSRR
Rejection Ratio
Supply Current (per No load 6.5 9
IS mA
channel) At the temperature extremes 11
MISCELLANEOUS PERFORMANCE
RL = 2 k 4.1 4.25
At the temperature extremes 3.8
Output Swing RL = 150 Ω 4 4.2
VOH V
High At the temperature extremes 3.7
RL = 75 Ω 3.85 4.18
At the temperature extremes 3.5
RL = 2 k −4.05 −4.19
At the temperature extremes −3.8
Output Swing RL = 150 Ω −3.9 −4.05
VOL V
Low At the temperature extremes −3.65
R L = 75 Ω −3.8 −4
At the temperature extremes −3.5
VOUT = 1 V from Sourcing 45 100
IOUT Output Current either rail mA
Sinking –45 –110
Sourcing to 120 180
Ground
Output Short Circuit At the temperature extremes 100
ISC mA
Current (6) Sinking to 120 230
Ground
At the temperature extremes 100
Common-Mode Input 4
RIN MΩ
Resistance
Common-Mode Input 1.8
CIN pF
Capacitance
ROUT Output Impedance f = 1 MHz, AV = +1 0.06 Ω

(5) Positive current corresponds to current flowing into the device.

(6) Short circuit test is a momentary test. See Note 3 under Absolute Maximum Ratings.

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6.7 Typical Characteristics

AV = -1
AV = -2
0 0
-1 AV = +10 -1
AV = -10
AV = +5
GAIN

GAIN
-3 -3
AV = +2 AV = -5

AV = +1
-5 -5
VS = ±2.5V VS = ±2.5V
RL = 100: RL = 100:
-7 -7
VOUT = 200mVPP VOUT = 200mVPP

1M 10M 100M 500M 1M 10M 100M 500M

FREQUENCY (Hz) FREQUENCY (Hz)

Figure 1. Noninverting Frequency Response, Gain Figure 2. Inverting Frequency Response, Gain
0 0
AV = +1 AV = -2

-50 -50 AV = -10

AV = +10
AV = -1
AV = -5
AV = +5
-100 -100
PHASE
PHASE

AV = +2

-150 -150
AV = -1
VS = ±2.5V VS = ±2.5V AV = -2
-200 -200
RL = 100: RL = 100:
VOUT = 200mVPP VOUT = 200mVPP AV = -5

1M 10M 100M 500M 1M 10M 100M 500M

FREQUENCY (Hz) FREQUENCY (Hz)

Figure 3. Noninverting Frequency Response, Phase Figure 4. Inverting Frequency Response, Phase

VS = ±5V 140
25°C
RL = 100:

100 130
PHASE
PHASE (°)
GAIN (dB)

80 85°C -40°C
Im = 35.2°
fu (MHz)

60
120
20 40
GAIN
10 20
0 0 110
133MHz VS = ±5V
RL = 100:
100
100k 1M 10M 100M 1G
-5 -4 -3 -2 -1 0 1 2 3 4 5
FREQUENCY (Hz)
VCM (V)

Figure 5. Open Loop Gain/Phase vs. Frequency Figure 6. Unity Gain Frequency vs. VCM

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Typical Characteristics (continued)

45 5
VS = ±5V VS = ±2.5V, AV = -1
4.5
RL = 100: RL = 100:
40 4 f = 50MHz
-40°C
3.5 f = 40MHz

OUTPUT (VPP)
f = 30MHz
35 3
25°C f = 20MHz
PM (°)

2.5
30 2
85°C 1.5
f = 60MHz
25 1
f = 70MHz
0.5 f = 80MHz
20 0
-5 -4 -3 -2 -1 0 1 2 3 4 5 0.5 1 1.5 2 2.5 3 3.5
VCM (V) INPUT (VPP)

Figure 7. Phase Margin vs. VCM Figure 8. Output vs. Input

10 100
VS = ±5V f = 20MHz VS = ±5V
9 90
AV = -1
8 f = 1MHz
RL = 100:
80
7
OUTPUT (VPP)

f = 40MHz 70
CMRR (dB)

6 f = 30MHz
f = 50MHz
5 60
4
50
3
40
2 f = 60MHz
f = 70MHz 30
1
f = 80MHz
0 20
1 2 3 4 5 6 7 8 9 10 1k 10k 100k 1M 10M 100M
INPUT (VPP) FREQUENCY (Hz)

Figure 9. Output vs. Input Figure 10. CMRR vs. Frequency

90 0.03 100
+PSRR RF = RG = 750:
80 0.025 RL = 150:

0.02 VS = ±5V 75
70 NTSC
-PSRR
DP (milli_deg)

0.015
PSRR (dB)

DG (%)

60
0.01 50
50 DG
0.005
40
0 25
30 DP
-0.005

20 -0.01 0
10 100 1k 10k 100k 1M 10M 100M -100 -80 -60 -40 -20 0 20 40 60 80 100
FREQUENCY (Hz) IRE (%)

Figure 11. PSRR vs. Frequency Figure 12. DG/DP vs. IRE

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Typical Characteristics (continued)

140 70 120

110
120 60
100
NOISE VOLTAGE (nV/ Hz)

NOISE CURRENT (pA/ Hz)

100 50 90

CT (dB)
80
80 40
VOLTAGE 70
60 30 60
50
40 20
VS = ±5V
CURRENT 40
20 10 SND: RL = 100:
30 RCV = R = R = 1k
F G
0 0 20
10 100 1k 10k 100k 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 13. Noise vs. Frequency Figure 14. Crosstalk Rejection vs. Frequency

100 -40
AV = +1 f = 500KHz
AV = -1
-50
10 VS = ±5V
THD
RL = 100:
-60
1
THD (dBc)
ROUT (:)

HD3
-70

0.1
-80

HD2
0.01 -90

0.001 -100
100 1k 10M 100M 1G 0 1 2 3 4 5 6 7 8 9
10k 100k 1M
FREQUENCY (Hz) VOUT (VPP)

Figure 15. Output Impedance vs. Frequency Figure 16. HD vs. VOUT
-40 -20
THD VS = ±2.5V
-45 -30 AV = +2
-50 10MHz, 150:
-40
-55
HD3 -50
THD (dBc)

THD (dBc)

-60 10MHz, 1k:

HD2 -60
-65
-70
-70 f = 5MHz 1MHz, 150:
-75 AV = -1 -80
VS = ±5V
-80 -90
RL = 100: 1MHz, 1k:
-85 -100
0 1 2 3 4 5 6 7 8 9 0 0.5 1 1.5 2 2.5 3
VOUT (VPP) VOUT (VPP)

Figure 17. HD vs. VOUT Figure 18. THD vs. VOUT

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Typical Characteristics (continued)

-20 -20
VOUT = 2VPP VOUT = 5VPP
-30 AV = -1 -30 AV = -1
VS = ±5V THD THD
VS = ±5V
-40 RL = 100: -40
RL = 100:
HD (dBc)

HD (dBc)
-50 -50

-60 -60
HD2
-70 HD2 -70
HD3
-80 -80
HD3
-90 -90
100 1k 10k 100k 100 1k 10k 100k
FREQUENCY (KHz) FREQUENCY (KHz)

Figure 19. HD vs. Frequency Figure 20. HD vs. Frequency

10 10
VS = ±2.5V 85°C VS = ±2.5V
125°C 125°C
85°C
VOUT FROM V (V)
VOUT FROM V (V)

25°C
-

-40°C
+

-40°C
25°C -40°C
1 1
-40°C

125°C 125°C
85°C

0.1 0.1
0 50 100 150 200 0 50 100 150 200 250
IOUT (mA) IOUT (mA)

Figure 21. VOUT vs. ISOURCE Figure 22. VOUT vs. ISINK

10 10
VS = ±5V VS = ±5V
125°C
125°C
85°C
VOUT FROM V (V)

VOUT FROM V (V)

25°C
-40°C
+

25°C -40°C
25°C
1 1
-40°C

125°C
125°C
85°C 85°C

0.1 0.1
0 50 100 150 200 0 50 100 150 200 250
IOUT (mA)
IOUT (mA)

Figure 23. VOUT vs. ISOURCE Figure 24. VOUT vs. ISINK

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Typical Characteristics (continued)

200 250
25°C -40°C
180
160 200

140 25°C
ISOURCE (mA)

85°C, 125°C
150

ISINK (mA)
120
85°C, 125°C
100
80 100

60
-40°C
40 50

20
0 0
2 4 6 8 10 12 14 2 4 6 8 10 12 14
VS (V) VS (V)

Figure 25. Short Circuit Current Figure 26. Short Circuit Current
40 40

0.1% 0.1%
35 35
SETTLING TIME (ns)

30 30
SETTLING TIME (ns)

1%
25 25

20 20 1%
AV = -1 AV = -1
15 VS = ±2.5V 15 VS = ±5V
RL = 500: RL = 500:
10 10
0 0.5 1 1.5 2 2.5 0 1 2 3 4 5 6
VOUT (VPP) VOUT (VPP)

Figure 27. Settling Time vs. Output Step Amplitude Figure 28. Settling Time vs. Output Step Amplitude

140 +4
AV = -1
85°C
120 VS = 10V +2
ZL = 500: || CL
SETTLING TIME (ns)

100 RSERIES = 20: 0

'VOS (mV)

80 -2 25°C -40°C
POSITIVE
60 -4

40 -6
NEGATIVE VS = ±2.5V
20 -8
RL = 150:
0 -10
10 100 1k 10k -2 -1 0 1 2
CL (pF) VOUT (V)

Figure 29. 0.1% Settling Time vs. Cap Load Figure 30. ΔVOS vs. VOUT

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Typical Characteristics (continued)

2 8
85°C 25°C 85°C
1 7
0 25°C
6
-1
-40°C
-40°C 5
-2

IS (mA)
'VOS (mV)

-3 4
-4 3
-5
2
-6
VS = ±5V
1 -
-7 R = 150:
L VCM = V +0.5V
-8 0
-5 -4 -3 -2 -1 0 1 2 3 4 5 2 4 6 8 10 12 14
VOUT (V) VS (V)

Figure 31. ΔVOS vs. VOUT Figure 32. IS /Amp vs. VS

9 10

85°C 9
8
8 85°C
7 25°C
7
25°C
IS (mA)

6 6
IS (mA)

-40°C
-40°C
5 5

4
4
3
3 2
VS = ±2.5V VS = ±5V
2 1
-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 -6 -5 -4 -3 -2 -1 0 1 2 3 4
VCM (V) VCM (V)

Figure 33. IS/Amp vs. VCM Figure 34. IS/Amp vs. VCM

0 0
-40°C 25°C
UNIT 1
-0.5 -0.5
UNIT 1

-1 -1
VOS (mV)
VOS (mV)

-1.5 -1.5
UNIT 2
UNIT 2 -2
-2
UNIT 3 UNIT 3
-2.5 -2.5

-3 -3
2 4 6 8 10 12 14 2 4 6 8 10 12 14
VS (V) VS (V)

Figure 35. VOS vs. VS (for 3 Representative Units) Figure 36. VOS vs. VS (for 3 Representative Units)

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Typical Characteristics (continued)

0 -1.1
85°C
UNIT 1 -1.2
-0.5 85°C
-1.3
-1 -40°C
-1.4

VOS (mV)
VOS (mV)

-1.5 -1.5
UNIT 2 -1.6
-2
25°C
UNIT 3 -1.7
-2.5
-1.8
VS = ±5V
-3 -1.9
2 4 6 8 10 12 14 -6 -5 -4 -3 -2 -1 0 1 2 3 4
VS (V) VCM (V)

Figure 37. VOS vs. VS (for 3 Representative Units) Figure 38. VOS vs. VCM (A Typical Unit)

6 0.16

85°C 0.14
5
25°C 0.12
25°C
4
IOS (PA)
0.1
-40°C
IB (PA)

3 0.08
-40°C
0.06
2
0.04
85°C
1
0.02

0 0
2 4 6 8 10 12 14 2 4 6 8 10 12 14
VS (V) VS (V)

Figure 39. |IB| vs. VS Figure 40. IOS vs. VS

0.1 V/DIV

0.1 V/DIV

VS = ±2.5V VS = ±2.5V
AV = +1 AV = +2
RL = 100: RL = 100:

2 ns/DIV 5 ns/DIV

Figure 41. Small Signal Step Response Figure 42. Small Signal Step Response

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Typical Characteristics (continued)

0.1 V/DIV

0.1 V/DIV
VS = ±5V VS = ±5V
AV = +1 AV = +2
RL = 100: RL = 100:

2 ns/ DIV 5 ns/DIV

Figure 43. Small Signal Step Response Figure 44. Small Signal Step Response

0.4 V/DIV
1 V/DIV

VS = ±5V VS = ±2.5V

AV = +1 AV = +2

RL = 100: RL = 100:

10 ns/DIV 5 ns/DIV

Figure 45. Large Signal Step Response Figure 46. Large Signal Step Response
1 V/DIV

VS = ±5V
AV = +2
RL = 100:

10 ns/DIV

Figure 47. Large Signal Step Response

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7 Detailed Description

7.1 Overview
7.1.1 Large Signal Behavior
The LMH6657 and LMH6658 are large-bandwidth, fast slew rate, voltage feedback operational ampplifers ideal
for high-speed, large signal applications. The low input referred voltage noise in conjunction with an input voltage
range, which extends below V–, eases the adoption of this part in applications having a tiny signal at or near
system ground, as well as other high-speed, low-distortion, and low-noise systems. Also, the large Gain
Bandwidth Product allows high gain operation that does not compromise speed.

7.2 Feature Description

The LMH6657 and LMH6658 input stage is designed to provide excess overdrive when needed. This occurs
when fast input signal excursions cannot be followed by the output stage. In these situations, the device
encounters larger input signals than would be encountered under normal closed loop conditions. The LMH6657
and LMH6658 input stage is designed to take advantage of this "input overdrive" condition. The larger the
amount of this overdrive, the greater is the speed with which the output voltage can change. Here is a plot of
how the output slew rate limitation varies with respect to the amount of overdrive imposed on the input:
800
VS = ±5V
700

600
SLEW RATE (V/Ps)

500

400

300

200

100

0
0.00 1.00 2.00 3.00
INPUT OVERDRIVE (V)

Figure 48. Plot Showing the Relationship Between Slew Rate and Input Overdrive

To relate the explanation above to a practical example, consider the following application example. Consider the
case of a closed loop amplifier with a gain of −1 amplifying a sinusoidal waveform. From the plot of Output vs.
Input (Figure 8), with a 30-MHz signal and 7VPP input signal, it can be seen that the output will be limited to a
swing of 6.9 VPP. From the frequency Response plot it can be seen that the inverting gain of −1 has a −32°
output phase shift at this frequency.
It can be shown that this setup will result in about 1.9 VPP differential input voltage corresponding to 650 V/μs of
slew rate from Figure 48, above (SR = VO(pp) × π × f = 650V/μs)
Note that the amount of overdrive appearing on the input for a given sinusoidal test waveform is affected by the
following:
• Output swing
• Gain setting
• Input/output phase relationship for the given test frequency
• Amplifier configuration (inverting or noninverting)
Due to the higher frequency phase shift between input and output, there is no closed form solution to input
overdrive for a given input. Therefore, Figure 48 is not very useful by itself in determining the output swing.
The following plots aid in predicting the output transition time based on the amount of swing required for a given
gain setting.

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Feature Description (continued)

18 18
RL = 100: AV = +10, POS RL = 100: AV = -10, NEG
16 16

14 AV = +10, NEG 14
AV = -10, POS
12 AV = +1, POS 12
AV = +6, POS AV = -5, NEG

Tr (ns)
10
Tr (ns)

10
8 8 AV = -1, POS
6 AV = +6, NEG AV = +2, POS 6 AV = -5, POS

4 4 AV = -1, NEG
2 AV = +2, NEG 2
AV = +1, NEG
0 0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0
VO (VPP) VO (VPP)

Figure 49. Output 20%-80% Transition vs. Output Voltage Figure 50. Output 20%-80% Transition vs. Output Voltage
Swing (Noninverting Gain) Swing (Inverting Gain)

Beyond a gain of 5 or so, the LMH6657/6658 output transition would be limited by bandwidth. For example, with
a gain of 5, the −3dB BW would be around 30MHz corresponding to a rise time of about 12ns (10% - 90%).
Assuming a near linear transition, the 20%-80% transition time would be around 9ns which matches the
measured results as shown in Figure 49.
When the output is heavily loaded, output swing may be limited by current capability of the device. Refer to
Output Current Capability section for more details.

7.3 Device Functional Modes

7.3.1 Output Phase Reversal
This is a problem with some operational amplifiers. This effect is caused by phase reversal in the input stage due
to saturation of one or more of the transistors when the inputs exceed the normal expected range of voltages.
Some applications, such as servo control loops among others, are sensitive to this kind of behavior and would
need special safeguards to ensure proper functioning. The LMH6657 and LMH6658 is immune to output phase
reversal with input overload. With inputs exceeded, the LMH6657 and LMH6658 output will stay at the clamped
voltage from the supply rail. Exceeding the input supply voltages beyond the Absolute Maximum Ratings of the
device could however damage or otherwise adversely effect the reliability or life of the device.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Output Characteristics

8.1.1.1 Output Current Capability

The LMH6657/6658 output swing for a given load can be determined by referring to the Output Voltage vs.
Output Current plots in Typical Characteristics. Characteristic Tables show the output current when the output is
1V from either rail. The plots and table values can be used to predict closed loop continuous value of current for
a given load. If left unchecked, the output current capability of the LMH6657 and LMH6658 could easily result in
junction temperature exceeding the maximum allowed value specified under Absolute Maximum Ratings. Proper
heat sinking or other precautions are required if conditions as such exist.
Under transient conditions, such as when the input voltage makes a large transition and the output has not had
time to reach its final value, the device can deliver output currents in excess of the typical plots mentioned above.
Plots shown in Figure 51 and Figure 52 depict how the output current capability improves under higher input
overdrive voltages:

10 10
VS = ±5V VS = ±5V
25°C 25°C
VOUT FROM V (V)

VOUT FROM V (V)

+

1 20mV 1 -20mV

-500mV
500mV

0.1 0.1
0 50 100 150 200 0 50 100 150 200 250
IOUT (mA) IOUT (mA)

Figure 51. VOUT vs. ISOURCE (for Various Overdrive) Figure 52. VOUT vs. ISINK (for Various Overdrive)

The LMH6657 and LMH6658 output stage is designed to swing within approximately one diode drop of each
supply voltage by utilizing specially designed high speed output clamps. This allows adequate output voltage
swing even with 5-V supplies and yet avoids some of the issues associated with rail-to-rail output operational
amplifiers. Some of these issues are:
• Supply current increases when output reaches saturation at or near the supply rails
• Prolonged recovery when output approaches the rails
The LMH6657 and LMH6658 output is exceedingly well-behaved when it comes to recovering from an overload
condition. As can be seen from Figure 53, the LMH6657 and LMH6658 will typically recover from an output
overload condition in about 18 ns, regardless of the duration of the overload.

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Application Information (continued)

OUTPUT

2 V/DIV
INPUT

VS = ±5V, AV = +6, RF = 1k
RG = 200:RL = OPEN

20 ns/DIV

Figure 53. Output Overload Recovery

8.1.1.2 Driving Capacitive Loads

The LMH6657 and LMH6658 can drive moderate values of capacitance by utilizing a series isolation resistor
between the output and the capacitive load. Typical Characteristics shows the settling time behavior for various
capacitive loads and 20 Ω of isolation resistance. Capacitive load tolerance will improve with higher closed loop
gain values. Applications such as ADC buffers, among others, present complex and varying capacitive loads to
the operational amplifier; best value for this isolation resistance is often found by experimentation and actual trial
and error for each application.

8.1.1.3 Distortion
Applications with demanding distortion performance requirements are best served with the device operating in
the inverting mode. The reason for this is that in the inverting configuration, the input common-mode voltage
does not vary with the signal and there is no subsequent ill effects due to this shift in operating point and the
possibility of additional non-linearity. Moreover, under low closed loop gain settings (most suited to low
distortion), the noninverting configuration is at a further disadvantage of having to contend with the input common
voltage range. There is also a strong relationship between output loading and distortion performance (that is, 1
kΩ vs. 100 Ω distortion improves by about 20 dB at 100 KHz) especially at the lower frequency end where the
distortion tends to be lower. At higher frequency, this dependence diminishes greatly such that this difference is
only about 4 dB at 10 MHz. But, in general, lighter output load leads to reduced HD3 term and thus improves
THD.

9 Power Supply Recommendations

The LMH665x can operate off a single-supply or with dual supplies. The input CM capability of the parts (CMVR)
extends all the way down to the V- rail to simplify single-supply applications. Supplies should be decoupled with
low-inductance, often ceramic, capacitors to ground less than 0.5 inches from the device pins. TI recommends
the use of ground plane, and as in most high-speed devices, it is advisable to remove ground plane close to
device sensitive pins such as the inputs.

10 Layout

10.1 Layout Guidelines

Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and
possible circuit oscillations. See Application Note OA-15, Frequent Faux Pas in Applying Wideband Current
Feedback Amplifiers (SNOA367) for more information. TI suggests the following evaluation boards as a guide for
high frequency layout and as an aid in device testing and characterization:

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Layout Guidelines (continued)

Table 1. Evaluation Board Guide
DEVICE PACKAGE EVALUATION BOARD PIN
LMH6657MF SOT-23-5 LMH730216
LMH6657MG SC-70 LMH730165
LMH6658MA 8-Pin SOIC LMH730036
LMH6658MM 8-Pin VSSOP LMH730123

Another important parameter in working with high speed/high performance amplifiers, is the component values
selection. Choosing external resistors that are large in value will effect the closed loop behavior of the stage
because of the interaction of these resistors with parasitic capacitances. These capacitors could be inherent to
the device or a by-product of the board layout and component placement. Either way, keeping the resistor values
lower, will diminish this interaction to a large extent. On the other hand, choosing very low value resistors will
load down nodes and will contribute to higher overall power dissipation.

10.2 Layout Example

SC-70 Board Layout (Actual size = 1.5 in × 1.5 in)

Figure 54. Layer 1 Silk

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Layout Example (continued)

SC-70 Board Layout (Actual size = 1.5 in × 1.5 in)

Figure 55. Layer 2 Silk

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation
See Application Note OA-15, Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers, SNOA367

11.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
LMH6657 Click here Click here Click here Click here Click here
LMH6658 Click here Click here Click here Click here Click here

11.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LMH6657MF/NOPB ACTIVE SOT-23 DBV 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A85A

LMH6657MFX/NOPB ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A85A

LMH6657MG NRND SC70 DCK 5 1000 Non-RoHS Call TI Level-1-260C-UNLIM -40 to 85 A76
& Green
LMH6657MG/NOPB ACTIVE SC70 DCK 5 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A76

LMH6658MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH66

58MA
LMH6658MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH66
58MA
LMH6658MM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A88A

LMH6658MMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 A88A

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

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(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

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TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6657MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6657MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6657MG SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMH6657MG/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMH6658MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMH6658MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMH6658MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

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*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH6657MF/NOPB SOT-23 DBV 5 1000 208.0 191.0 35.0
LMH6657MFX/NOPB SOT-23 DBV 5 3000 208.0 191.0 35.0
LMH6657MG SC70 DCK 5 1000 208.0 191.0 35.0
LMH6657MG/NOPB SC70 DCK 5 1000 208.0 191.0 35.0
LMH6658MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMH6658MM/NOPB VSSOP DGK 8 1000 208.0 191.0 35.0
LMH6658MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
LMH6658MA/NOPB D SOIC 8 95 495 8 4064 3.05

Pack Materials-Page 3
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75 1.45
B A
1.45 0.90
PIN 1
INDEX AREA

1 5

2X 0.95
3.05
2.75
1.9 1.9
2

4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/F 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/F 06/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/F 06/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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