RING COUNTER

What is a Ring Counter : Working, Classification & Applications

Counters are sequential circuits whose function is to count pulse, frequency and time of the
signal using a single clock signal. It is an important component of digital electronics since
entire electronic devices work on counters. They are designed by grouping a (similar or
different) set of flipflops. Counters operate in different modes of modules, which are
represented by the number of states of the cycle. There are two types of counters, they are
synchronous and asynchronous counter. The synchronous counter operates based on the input
clock signal and the asynchronous counter is independent of the input clock signal. The
synchronous counter is a shift register counter which is further classified as a ring-type and
twisted type ring counter.

What is Ring Counter?

Definition: A ring counter is also known as SISO (serial in serial out) shift register counter,
where the output of the flip flop is connected to the input of the flip flop which acts as a ring
counter. The designing of the ring counter can be done by using four D-Flip Flops with a
common clock signal and overriding input can be connected to pre-set and clear.

block-diagram-of-ring-counter

From the above diagram,

1). The number of states used is 4 (Where no of states = no of flip flops used).

2). Pre-set or Clear: The main function of this is if the input clock signal changes then the
output value is also changed.

The connections are made as follows

 One input is connected to the first flip-flop ff0-Q0,

Another input is connected to CLR of the other three flip flops like ff1, ff2, ff3.

Working Theory

For example, let us take a condition where pre-set = ‘0000’ then the outputs obtained at each
flip flop is as follows. For FF0, the output at Q0 is ‘1’, whereas in other flipflops like ff, ff2,
ff3 (which are connected to clear where CLR = 0) the outputs obtained at Q1 = Q2 = Q3 =’0′.
This can be understood by following the truth table and its output waveforms obtained when
executed using Verilog HDL code in Xilinx software.
Truth Table
ORI CLK Q0 Q1 Q2 Q3
Low Pulse 0
X 1 0 0
1 0
0 0 1 0
1 0
0 0 0 1
1 1
0 0 0 0
1 0
0 1 0 0
Where

Inputs = ORI and CLK

X = Clock can be either a positive edge or a negative edge

Outputs = Q0, Q1, Q2, Q3.

From the table, we can observe that ‘1’ is shifted diagonally from Q0 to Q3 and again will
shifts back to ‘Q0’. So this shows that it works like a ring counter.

Verilog HDL Program for Ring Counter

Module dff(q,d,c);
output q;
input d,c;
reg q;
initial
q=1’b1;
always @ (posedge c)
q=d;
end module
module dff1(q,d,clk);
output q;
input d,clk;
reg q;
initial
q=1’b0;
always @ (posedge clk)
q=d;
endmodule

module ring(q,clk);
inout [3:0]q;
input clk;
dff u1(q[0],q[3],clk);
dff1 u2(q[1],q[0],clk);
dff1 u3(q[2],q[1],clk);
dff1 u4(q[3],q[2],clk);
end module

Timing Diagram of Ring Counter

The timing diagram of the ring counter is shown below.

timing-diagram-of-ring-counter

Classification of Ring Counters

Ring counters are classified into two they are,

Straight Type

The alternative name of a straight type is ‘one hot counter’, where the output of ending flip
flop is given as a feedback to the input of starting flip flop. Where binary digit 0/1 is
circulated in ring form. Two control signals Pre-set (PR) and the clock signal (CLK) are used.
Where PR is connected to FF 0 and CLR is given to FF3. The following is the block diagram
of 4 stages straight ring counter.
 straight-ring-
counter
Truth Table of Straight Ring Type Counter

truth-table-of-straight-type
Timing Diagram of Straight Type
timing-diagram-of-straight-type
Twisted Type

The alternative name of the twisted type is switch tail/walking/Johnson type counter. The
complemented output of ending flip flop is feedback to the input of starting flip flop. Where
the stream of 1’s and 0’s flow in ring form. The twisted type counter uses two control signals
like CLK and ORI. Where CLK and ORI are common to all four flip flops. The following is
the block diagram of 4 stages twisted ring-type counter.

Truth Table of Twisted Type

ORI CLK Q0 Q1 Q2 Q3
Low Pulse 0
X 0 0 0
1
1 1 0 0 0
1
1 1 1 0 0
1 0
1 1 1 1
1 1
1 1 1 1
1
1 0 1 1 1
1
1 0 0 1 1
1 1
1 0 0 0
Timing Diagram of Twisted Type

The timing diagram of the twisted type is shown below.

timing-diagram-of-johnson-type
Difference between Ring Type Counter and Johnson Type Counter

The following are the comparison between ring counter and Johnson counter
Ring Counter Johnson Counter
The output of the last flip-flop is
The output of the last flipflop is given as input complemented and given as input to starting
to starting flip flop. flip flop.
If ‘n’ number of flip flops are used then ‘2n’
Number of states = Number of flip flops used number of states is required.
Input frequency = n Input frequency = f
Output frequency = f/n Output frequency = f/2n
n
Total unused states = ( 2 – n) Total unused states = ( 2n – 2n)
Advantages

The advantages are

 It can encode and decode the logics

 Implementation can be done using JK and D flip flops
Disadvantages

The disadvantages are

 Out of 15 states, 4 states are used

 Non-self-starting.
Applications

The following are the applications

 Frequency counter
 ADC
 Digital clocks
 Measure timers and rate, etc.