Module-5
Fundamentals of VLSI
1. Evolution of Microelectronics:
MOS (Metal Oxide Silicon) Transistor History 1925: J. Lilienfeld proposed the basic
principle of MOS FET (Field Effect Transistor). 1935: O. Heil proposed a similar structure.
1962: P.K. Weimer (RCA) first placed pMOS and nMOS transistors on the same substrate.
1963: Frank Wanlass (Fairchild) invented invertor, NOR and NAND CMOS gates. This
invention starts the era of CMOS low power applications. 1965: The first MOS calculator.
1971: Emergence of nMOS-silicon gate technology. Note: Early research on MOS
technology led to success of bipolar transistor. This in turns leads to a decline of interest in
MOS transistor. 1980: The market share of MOSFET exceeds bipolar device. Transistor was
first invented by William. B. Shockley, Walter Brattain and John Bardeen of Bell
laboratories.
In 1961, first IC was introduced. Levels of Integration:
• Small Scale Integration:- (10-100) transistors => Example: Logic gates
• Medium Scale Integration:- (100-1000) => Example: counters
• Large Scale Integration:- (1000-20000) => Example:8-bit chip
• Very Large Scale Integration:- (20000-1000000) => Example:16 & 32 bit up
• Ultra Large Scale Integration:- (1000000-10000000) => Example: Special processors,
virtual reality machines, smart sensors.
A Metal-Oxide-Semiconductor (MOS) structure is created by superimposing several layers of
conducting and insulating materials to form a sandwich-like structure. These structures are
manufactured using a series of chemical processing steps involving oxidation of the silicon,
selective introduction of dopants, and deposition and etching of metal wires and contacts.
Transistors are built on nearly flawless single crystals of silicon, which are available as thin
flat circular wafers of 15–30 cm in diameter. CMOS technology provides two types of
transistors (also called devices): an n-type transistor (nMOS) and a p-type transistor (pMOS).
Transistor operation is controlled by electric fields so the devices are also called Metal Oxide
Semiconductor Field Effect Transistors (MOSFETs) or simply FETs. Cross-sections and
symbols of these transistors are shown. The n+ and p+ regions indicate heavily doped n- or
ptype silicon. Basic starting material: Single crystal of silicon formed as wafers (4-inch, 6-
inch, 8- inch, 12-inch). MOS structure is created by superposing several layers of conducting,
insulating, and transistor-forming materials to create a sandwich-like structure by way of a
series of chemical processing steps such as: oxidation of the silicon, diffusion of impurities
into silicon to give it certain conduction characteristics, and deposition and etching of
aluminum on silicon to form interconnection.
2. Basic structures of nmos,pmos and cmos
Two types of transistors nMOS: with negatively diffused (doped) source and drain on lightly
p-doped substrate. pMOS: with positively diffused source and drain on lightly n-doped
substrate.
Four terminals of a transistor: Gate: usually formed by polycrystalline silicon (polysilicon for
short). It is a control input that affects the flow of electrical current between source and drain.
Source and Drain: Formed by diffusion. They are physically equivalent and the name
assignment depends on the direction of current flow. Source provides charges. Drain sinks
charges. Substrate: the fourth terminal of MOS transistor.
Each transistor consists of a stack of the conducting gate, an insulating layer of silicon
dioxide (SiO2, better known as glass), and the silicon wafer, also called the substrate, body,
or bulk. Gates of early transistors were built from metal, so the stack was called metal oxide
semiconductor, or MOS. Since the 1970s, the gate has been formed from polycrystalline
silicon (polysilicon), but the name stuck. (Interestingly, metal gates reemerged in 2007 to
solve materials problems in advanced manufacturing processes.) An nMOS transistor is built
with a p-type body and has regions of n-type semiconductor adjacent to the gate called the
source and drain. They are physically equivalent and for now we will regard them as
interchangeable. The body is typically grounded. A pMOS transistor is just the opposite,
consisting of p-type source and drain regions with an n-type body. In a CMOS technology
with both flavors of transistors, the substrate is either n-type or p-type. The other flavor of
transistor must be built in a special well in which dopant atoms have been added to form the
body of the opposite type.
The positive voltage is usually called VDD or POWER and represents a logic 1 value in
digital circuits. In popular logic families of the 1970s and 1980s, VDD was set to 5 volts.
Smaller, more recent transistors are unable to withstand such high voltages and have used
supplies of 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, and so forth. The low voltage is called
GROUND (GND) or VSS and represents a logic 0. It is normally 0 volts.
3. Moore’s Law
Moore’s Law is the observation that the number of transistors on an integrated circuit will
double every two years with minimal rise in cost. Intel co-founder Gordon Moore
predicted a doubling of transistors every year for the next 10 years in his original paper
published in 1965. Ten years later, in 1975, Moore revised this to doubling every two years.
This extrapolation based on an emerging trend has been a guiding principle for the
semiconductor industry for close to 60 years.
Fig 1.3 Moore’s Law
4. Field-Effect Transistors
Introduction
A field-effect transistor (FET) is a semiconductor device that uses an electric field to control
the flow of current in a semiconductor. FETs are three-terminal devices with a source, gate,
and drain. JFET transistor is a voltage-controlled device. For the FET the current I D will be a
function of the voltage VGS applied to the input circuit. The FET is a unipolar device
depending solely on either electron (n- channel) or hole ( p-channel) conduction.
MOSFET stands for Metal Oxide Silicon Field Effect Transistor or Metal Oxide
Semiconductor Field Effect Transistor. This is also called as IGFET meaning Insulated Gate
Field Effect Transistor. The FET is operated in both depletion and enhancement modes of
operation. The following figure shows how a practical MOSFET looks like.
Construction of a MOSFET
The construction of a MOSFET is a bit similar to the FET. An oxide layer is deposited on the
substrate to which the gate terminal is connected. This oxide layer acts as an insulator (sio2
insulates from the substrate), and hence the MOSFET has another name as IGFET. In the
construction of MOSFET, a lightly doped substrate, is diffused with a heavily doped region.
Depending upon the substrate used, they are called as P-type and N-type MOSFETs.
The following figure shows the construction of a MOSFET.
The voltage at gate controls the operation of the MOSFET. In this case, both positive and
negative voltages can be applied on the gate as it is insulated from the channel. With negative
gate bias voltage, it acts as depletion MOSFET while with positive gate bias voltage it acts as
an Enhancement MOSFET.
Classification of MOSFETs
Depending upon the type of materials used in the construction, and the type of operation,
the MOSFETs are classified as in the following figure.
After the classification, let us go through the symbols of MOSFET.
The N-channel MOSFETs are simply called as NMOS. The symbols for N-channel MOSFET
are as given below.
The P-channel MOSFETs are simply called as PMOS. The symbols for P-channel MOSFET
are as given below.
Structure of N- Channel MOSFET
Working of N- Channel (depletion mode) MOSFET
For now, we have an idea that there is no PN junction present between gate and channel in
this, unlike a FET. We can also observe that, the diffused channel N (between two N+
regions), the insulating dielectric SiO2 and the aluminum metal layer of the gate together
form a parallel plate capacitor. If the NMOS has to be worked in depletion mode, the gate
terminal should be at negative potential while drain is at positive potential, as shown in the
following figure.
When no voltage is applied between gate
and source, some current flows due to the
voltage between drain and source. Let some
negative voltage is applied at VGG . Then the
minority carriers i.e. holes, get attracted and
settle near SiO2 layer. But the majority
carriers, i.e., electrons get repelled.
With some amount of negative potential at V GG a certain amount of drain current ID flow
through source to drain. When this negative potential is further increased, the electrons get
depleted and the current ID decreases. Hence the more negative the applied V GG , the lesser
the value of drain current I D will be. The channel nearer to drain gets more depleted than at
source (like in FET) and the current flow decreases due to this effect. Hence it is called as
depletion mode MOSFET.
Working of N-Channel MOSFET (Enhancement Mode)
The same MOSFET can be worked in
enhancement mode, if we can change the
polarities
of the voltage VGG . So, let us consider the
MOSFET with gate source voltage V GG
being positive as shown in the following
figure.
When no voltage is applied between gate
and source, some current flows due to the
voltage between drain and source. Let some
positive voltage is applied at VGG . Then the
minority carriers i.e. holes, get repelled and the majority carriers i.e. electrons gets attracted
towards the SiO2 layer. With some amount of positive potential at V GG a certain amount of
drain current ID flows through source to drain. When this positive potential is further
increased, the current ID increases due to the flow of electrons from source and these are
pushed further due to the voltage applied at V GG . Hence the more positive the applied V GG ,
the more the value of drain current I D will be. The current flow gets enhanced due to the
increase in electron flow better than in depletion mode. Hence this mode is termed as
Enhanced Mode MOSFET.
5. VLSI Design Flow
● VLSI Full Form (Very Large Scale Integration) technology has revolutionized the
electronics industry by enabling the integration of numerous logic devices, such as
transistors and diodes, into a single chip.
● This advancement has paved the way for highly efficient and compact electronic
circuits used in various applications, from consumer electronics to aerospace and
defence.
1. Specification: Gather information
regarding the desired functionality,
performance targets, power
constraints, and any other specific
requirements.
2. Architectural design:
Designers begin the design entry
phase, where they create a high-level
representation of the circuit using
hardware description languages
(HDLs) such as Verilog or VHDL.
3. Functional design or Behavioural
design:
This represents the functional units
involved of the VLSI design and the
interconnections between them. The functionality of all units is specified on the basis of their
input, output, and time is taken for conduction.
4. Logic Design: Register Transfer Level [RTL] can be expressed in Hardware Description
Language such as Verilog, or VHDL. This logic design takes care of the word widths,
register allocation, and also the control flow of the fabrication process.
5. Circuit Design: In this step, the logic blocks of the desired design are replaced by the
electronic circuits, which are consists of electronic devices such as resistors, capacitors, and
transistors.
6. Physical Design:
This step involves placing the gates and routing the interconnections to meet the timing and
area constraints
7. Fabrication: After the actual layout and verification of the desired design, the design is
sent for manufacturing. The handoff of the desired design to the manufacturing process is
called tapeout.
8.Packaging and Testing: After fabricating, packaging should be done carefully in such a
way that the chips should ensure all the design specifications without any damage. The
package of the desired design is then sealed and then sent to the end-users or clients.
