Computer Organization & Architecture

Subject Code: 23CSAI35

 MODULE-2

Input/output Organization:
Accessing I/O Devices, Interrupts – Interrupt Hardware,
Enabling and Disabling Interrupts, Handling Multiple
Devices, Direct Memory Access: Bus Arbitration,
Text book 2: 4.1, 4.2.1, 4.2.2, 4.2.3, 4.4, 4.5, 4.6
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4.2 Interrupts

In case of program controlled I/O,

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4.2.3 Handling Multiple Devices
A processor can have number of devices connected to it , which are capable of initiating
interrupts. At this time processor should resolve these issues with different approaches. The
simplest way to identify the interrupting device is to have the interrupt service routine poll all
the I/O devices connected to the bus. Polling method is simple but time must be spent in
detecting IRQ bit set for all devices including the devices which may not be requesting any
service, which is unnecessary and waste of resource.
To overcome the above drawback there are other approaches to handle interrupts by multiple
devices.
They are
1) Vectored Interrupts
2) Interrupt Nesting

1) Vectored Interrupts

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Interrupt Nesting
When several devices are involved in interrupt, the execution of current interrupt service routine
continues to completion before processor accepts any other interrupt from other devices.

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Simultaneous Requests

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4.4 Direct Memory Access

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4.4.1 Bus Arbitration

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Centralized Arbitration

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Distributed Arbitration

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5.4 Speed , Size and Cost

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SIMM, a single in-line memory module. DIMM, dual in-line memory module. Rambus
memory modules are a subset of DIMMs, but are normally referred to as RIMMs.

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Cache Memory

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Mapping Function

Direct Mapping

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Problems on Direct Mapping
Problem 1. Consider a direct mapped cache of size 16 KB with block size 256 bytes. The size of main memory is 128 KB.
Find-
1.Number of bits in tag
2.Tag directory size
Given-
•Cache memory size = 16 KB
•Block size = Frame size = Line size = 256 bytes
Consider that the memory is byte addressable.
•Main memory size = 128 KB
We have,
Size of main memory
= 128 KB
= 217 bytes
Thus, Number of bits in physical address = 17 bits

Number of Bits in Block Offset-

We have,
Block size
= 256 bytes
= 28 bytes
Thus, Number of bits in block offset = 8 bits
Number of Bits in Line Number-

Total number of lines in cache

= Cache size / Line size
= 16 KB / 256 bytes
= 214 bytes / 28 bytes
= 26 lines
Thus, Number of bits in line number = 6 bits 46
Number of Bits in Tag-

Number of bits in tag

= Number of bits in physical address – (Number of bits in line number + Number of bits in block offset)
= 17 bits – (6 bits + 8 bits)
= 17 bits – 14 bits
= 3 bits
Thus, Number of bits in tag = 3 bits

Tag Directory Size-

Tag directory size
= Number of tags x Tag size
= Number of lines in cache x Number of bits in tag
= 26 x 3 bits
= 192 bits
= 24 bytes
Thus, size of tag directory = 24 bytes
Problem 2.
Consider a direct mapped cache of size 512 KB with block size 1 KB. There are 7 bits in the tag. Find-
1.Size of main memory
2.Tag directory size
•Cache memory size = 512 KB
•Block size = Frame size = Line size = 1 KB
•Number of bits in tag = 7 bits
We consider that the memory is byte addressable.

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Number of Bits in Block Offset-
We have,
Block size
= 1 KB = 210
= 210 bytes
Thus, Number of bits in block offset = 10 bits

Number of Bits in Line Number-

Total number of lines in cache
= Cache size / Line size
= 512 KB / 1 KB
= 29 lines
Thus, Number of bits in line number = 9 bits

Number of Bits in Physical Address-

Number of bits in physical address
= Number of bits in tag + Number of bits in line number +
Number of bits in block offset
= 7 bits + 9 bits + 10 bits
= 26 bits
Thus, Number of bits in physical address = 26 bits
Tag Directory Size-
Size of Main Memory- Tag directory size
We have, = Number of tags x Tag size
Number of bits in physical address = 26 bits = Number of lines in cache x Number of bits in tag
Thus, Size of main memory = 29 x 7 bits
= Type equation here. = 3584 bits
= 226 = 448 bytes
= 220 * 26 Thus, size of tag directory = 448 bytes
= MB 64
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= 64 MB
Problem-03:
Consider a direct mapped cache with block size 4 KB. The size of main memory is 16 GB
and there are 10 bits in the tag. Find-
1. Size of cache memory
2. Tag directory size
Size of cache memory = 16 MB

Thus, size of tag directory = 5120 bytes

Problem-04:
Consider a direct mapped cache of size 32 KB with block size 32 bytes. The CPU
generates 32 bit addresses. The number of bits needed for cache indexing and the number
of tag bits are respectively-
Number of bits in block offset = 5 bits
Number of bits in line number = 10 bits

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Associative Mapping

Consider a cache consisting of 128 blocks of

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https://www.youtube.com/watch?v=uU2KpJqy2Ns 59
 Draw backs of Associative mapping:
1) Increased Hit Latency
2) Increased hardware components
3) Increased heat

https://www.youtube.com/watch?v=uwnsMaH-iV0 60
Hit latency = Delay due to n bit comparator for searching the correct tag line + Propagation
Delay due to OR gate

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Set Associative Mapping

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The cache memory is split in to number of sets. Example set 0, 1, 2 ….m.
The main memory lines can be mapped to any of the cache line belonging to that particular set.
Example set0.
Since all the sets are of equal size, the way is specified based on the number of lines in the
cache. That means if one set consists of k number of lines then it is called k-way set
associative mapping.

By looking at the particular set we can determine the location of main memory is mapped on
to. So we need not search entire cache memory block for a particular data , instead search in
the set of line. The retrieval becomes easier and we only need k comparators.

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In order to
search the
content 4 , we
need not search
entire cache,
instead we need
to search only in
set 0.
In this case we
only need 2
comparators of
3 bit.

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4.5 Buses

The device which initiates data transfer by issuing Read or Write command on the bus is
called Master or Initiator. Usually by default processor will be Master. Other devices like
DMA capability may become Master.

A device addressed by the Master is called Slave or Target.

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Synchronous Bus

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Multiple Cycle Transfer
Limitations of the synchronous bus are as follows:

1) A transfer has to be completed within one clock cycle, t2-t0, must be chosen to accommodate the
longest delay on the bus and slowest device interface. This forces all the device to operate at the speed of
slowest device.

2) The processor has no ways to detect whether the addressed device has responded. It simply assumes
that at t2, the output data have been received by I/O device or input data are available on data lines.
The error will not be detected in case of malfunction.

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Asynchronous Bus

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