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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 6, JUNE 2015 1

A High-Linearity Digital-to-Time Converter

Technique: Constant-Slope Charging
Jiayoon Zhiyu Ru, Member, IEEE, Claudia Palattella, Student Member, IEEE, Paul Geraedts, Member, IEEE,
Eric Klumperink, Senior Member, IEEE, and Bram Nauta, Fellow, IEEE

Abstract—A digital-to-time converter (DTC) controls time delay The basic element of a DTC is a variable-delay element, and
by a digital code, which is useful, for example, in a sampling oscillo- there are different ways to implement delay in CMOS. A dis-
scope, fractional-N PLL, or time-interleaved ADC. This paper pro- tributed circuit such as an ideal transmission line can theoreti-
poses constant-slope charging as a method to realize a DTC with in-
trinsically better integral non-linearity (INL) compared to the pop- cally provide true time delay while keeping the waveform undis-
ular variable-slope method. The proposed DTC chip realized in 65 torted. However, it requires unpractically long line length in
nm CMOS consists of a voltage-controlled variable-delay element CMOS technology (e.g., mm).
(DTC-core) driven by a 10 bit digital-to-analog converter. Mea- Moreover, as CMOS interconnect losses are high and frequency
surements with a 55 MHz crystal clock demonstrate a full-scale
delay programmable from 19 ps to 189 ps with a resolution from
dependent, different amplitudes and waveforms result at dif-
19 fs to 185 fs. As available oscilloscopes are not good enough to ferent delay tap-points along a transmission line, which intro-
reliably measure such high timing resolution, a frequency-domain duces zero-crossing variations when sensed by a comparator
method has been developed that modulates a DTC edge and de- [13]. Lumped circuits such as all-pass filters can approximate a
rives INL from spur strength. An INL of 0.17% at 189 ps full-scale true time delay compactly [14], [15] and maintain signal wave-
delay and 0.34% at 19 ps are measured, representing 8–9 bit effec-
tive INL-limited resolution. Output rms jitter is better than 210 fs form, but noise and dynamic range are compromised.
limited by the test setup, while the DTC consumes 1.8 mW. If the waveform is not important and delayed clock genera-
tion is the purpose, digital circuits can be used. Minimum digital
Index Terms—Constant slope, delay, delay measurement,
digital-to-time converter, DTC, INL, integral nonlinearity, gate delays are on the order of 10 ps in 65 nm CMOS. However,
phase-locked loop, PLL, variable delay, variable slope. if the difference between two gate delays is used, or if the gate
delay is tunable, much smaller delay steps can be realized, for
example in the order of 100 fs as will be presented in this work.
I. INTRODUCTION Although the absolute delay is still limited by the intrinsic gate
delay, the relative delay steps can be much smaller.

T IME delay is often defined as the time difference between

the threshold-crossing points of two clock edges. If delay
is programmable by a digital code, a digital-to-time converter
If delay tuning is linear, a high-linearity DTC can be real-
ized. A linear DTC is favored, as calibration of only two points
is sufficient, in contrast to a non-linear DTC that require multi-
(DTC) results. It is a basic building block suitable for several ap- point calibration [16]. To characterize linearity, integral nonlin-
plications, e.g., fractional-N phase-locked loops (PLL) [1]–[4], earity (INL) is an important metric for a DTC, similar to dig-
(sub-)sampling oscilloscopes [5], [6], automatic test equipment ital-to-analog converters (DAC). Non-zero DTC INL limits the
(ATE) [7], direct digital frequency synthesis (DDFS) [8], polar achievable spur level in fractional-N PLLs [1]–[3], [16] and the
transmitter [9], radar [10], phased-array system [11], and time- timing accuracy in sampling oscilloscopes.
interleaved ADC timing calibrations [12]. This paper aims at A DTC often exploits a voltage ramp generated by a current
improving the time resolution and linearity of a DTC. A nom- source charging a capacitor, and a comparator with threshold
inal full-scale delay in the order of 100 ps is targeted with fine voltage defining a time delay (see Fig. 1). Switched capac-
delay steps of less than 100 fs. itors [1], [2], [4] or switched current sources [3], [6], [7] can be
applied to program delay. These approaches produce a delay by
Manuscript received October 23, 2014; revised December 30, 2014; accepted varying the slope from one ramp to another, which we refer to as
March 07, 2015. This paper was approved by Associate Editor Boris Murmann. the variable-slope method (see Fig. 2(a). Using this method, 300
This work was supported by the Dutch government through project funding in fs delay resolution has been achieved in [2]. However, high res-
the frame of the SPITS Kennerswerkersregeling Project. Chip fabrication was
sponsored by NXP Semiconductors. olution does not necessarily mean high linearity. In this paper,
J. Z. Ru was with the University of Twente, Enschede, The Netherlands, and we propose a constant-slope method in which all ramps ide-
is now with Qualcomm, Irvine, CA 92618 USA (e-mail: zhiyu.ru@gmail.com). ally would have the same slope, in contrast to the variable-slope
C. Palattella, E. A. M. Klumperink, and B. Nauta are with the University of
Twente, Enschede 7500 AE, The Netherlands method (see Fig. 2(b)). To still realize variable delay, a variable
P. Geraedts was with the University of Twente, Enschede, The Netherlands, start voltage is used which can linearly program delay. We will
and is now with Teledyne DALSA. show that this method is intrinsically more linear, allowing for a
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. more linear DTC than variable slope offers. Before we do this in
Digital Object Identifier 10.1109/JSSC.2015.2414421 the next section, we first briefly discuss related previous work.

0018-9200 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
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2 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 6, JUNE 2015

Fig. 1. A voltage ramp generated by a current source charging a capacitor, and

delay defined by the ramp crossing : (a) an ideal model; (b) a practical
Fig. 3. Phase interpolation concept starting from two equal-slope signals
case.
and , where the interpolated phases have the same slope for the
part within the two dashed lines.

This paper is organized as follows: Section II explains

the constant-slope method and its advantage in linearity;
Section III describes the design of a DTC circuit using this
method; Section IV presents measurements and Section V con-
clusions.

II. CONSTANT-SLOPE METHOD

A. Constant-Slope Ramp Generation

To generate a voltage ramp with a controlled slope
Fig. 2. Principle of (a) variable-slope method in which different slopes at com- , often a current is used to charge a capacitor as shown
parator input define delay; (b) constant-slope method in which different start-
voltages at comparator input define delay. in Fig. 1, where . The delay time of this ramp
from zero voltage to the voltage is:

In [17], the nonlinearity of the variable-slope method was ob- (1)

served but not explained. The use of a high-gain comparator to
improve INL was proposed in [17], but no measurement results As shown by (1), if we want one variable to control delay, we
were reported. can either vary the slope (“variable slope”) at fixed voltage
In [5], delay is controlled by tuning the threshold voltage of , or keep the slope fixed and vary voltage . In practice,
a comparator, which would result in linear delay control if the however, a single ramp often has a changing slope as shown in
slope of the ramp is constant over the threshold tuning range. Fig. 1(b), therefore varying does not always give a linearly-
Practically this is challenging, as the current produced by a cur- controlled delay.
rent source as shown in Fig. 1 depends on the voltage across Instead, we can vary the start-voltage as shown in
it, and hence on the capacitor voltage . Moreover, the com- Fig. 4 between 0 and . To generate a linearly-controlled
delay, it is sufficient if the part below is constant-slope,
parator in [5] works at a varying common-mode voltage, leading
while for the part above it suffices to have a con-
to a varying speed of the comparator, i.e., an extra INL source.
stant-shape.1 As the trajectory above is shared for all
Another way to realize variable delay is by phase interpola-
ramps and adds a fixed amount of delay, it does not affect the
tion, which can be implemented using current sources [18], [19],
linearity of the delay control function. Similarly, the same ramp
resistors [20], [21] or delay lines [22]. The basic concept of in-
start-up behavior between and adds a delay offset to all
terpolation and example waveforms are shown in Fig. 3, where
ramps which does not hurt linearity either.
the middle parts are constant-slope, assuming and have
A constant-shape above ensures that at different ,
the same slope. However, phase interpolation is functionally dif-
the delay between two ramps keeps constant, and it also ren-
ferent as it requires two edges to be present, between which it
ders INL benefits as described below.
can place a new edge. In contrast, this work aims to produce a
delayed edge after one incoming critical edge that triggers one B. Advantage of Constant-Slope Method on INL
charging process. We will use simple models to gain intuitive understanding.
The main new contributions of this paper are threefold: The delay function in Fig. 2 contains two distinct actions:
1) a concept to define a constant-slope method and to identify 1) ramp generation and 2) threshold comparison. The ramp
its fundamental advantages in terms of INL compared to a generation produces a ramp with controlled slope, while the
variable-slope method; 2) a new circuit topology in which
the start voltage controls the delay of only one critical edge, 1Being constant-shape between two ramps is equivalent to having the same

leading to high linearity and low jitter; 3) measurement results (local) slope at equal ramp voltage. This property allows for an alternative but
important interpretation of the name “constant slope”, namely that the (local)
demonstrating a fine resolution and a small INL, for which a slope is constant when comparing ramps of different delay settings at equal ramp
new measurement method was devised. voltage.
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RU et al.: A HIGH-LINEARITY DIGITAL-TO-TIME CONVERTER TECHNIQUE: CONSTANT-SLOPE CHARGING 3

Fig. 5. Delay mechanism for constant-slope method: the start voltage lin-
Fig. 4. Illustration of constant-slope method using practical ramps which ide-
early affects delay , while the comparator response is identical for ramp and
ally would start with a constant-slope part at least to then share a con-
because it “sees” the same shape of both ramps.
stant-shape part beyond .

the input voltage rises to , the output voltage begins to

threshold comparison defines a decision threshold and
change as the comparator starts to discharge the output node (a
produces an output edge when crossing the threshold. The
comparator with inverted output is assumed here).
variable-slope-induced INL comes from the behavior of a
If , the start-voltage part of the ramp does not
practical comparator.
affect the comparator response. Only the part of the ramp within
One source of delay INL is the comparator bandwidth limit,
the input window affects the output. In Fig. 5, if the ramps
which can be modeled by adding an network at the com-
and have the same shape between and , they evoke
parator output. It can be derived that, in case of an input ramp
the same response at the output. Hence their propagation delays
signal, the propagation delay of an network of any order
through the comparator are equal, and both edges would also
contains nonlinear functions of the input ramp time [23], [24],
have a constant shape at the output of the comparator, no matter
e.g., exponential and logarithmic functions. Assuming linear
what the bandwidth is. Therefore the time shift between two
ramp generation, the ramp time would vary linearly with code,
edges at the output is the same as at the input, and there is ideally
however the propagation delay would vary nonlinearly with
no error. Furthermore, unlike the variable-slope case, because
code due to its nonlinear function versus input ramp time in an
all edges have the same shape also at the output, INL errors
RC network. Since poles are ubiquitous in circuits related to
are also avoided in later stages, e.g., buffer stages that further
parasitic resistance and capacitance in transistors and intercon-
steepen the output edge.
nects, this is a source of INL in a DTC.
If a comparator passes through different operating modes
Another source of delay INL can be explained by the
during its transition as modeled in [25], the constant-slope
example of using an inverter as comparator. The nonlinear rela-
method still renders benefits in INL. The reason is again that,
tionship between an inverter's delay and its input ramp time has
apart from a different start voltage, both ramps in Fig. 5 have the
been modeled in [25] by equations using empirical parameters
same shape within the critical input window of the comparator
obtained from simulation fitting. Three operating modes were
whose response to both ramps is then very similar. Hence
distinguished in an inverter's response to an input ramp signal:
each operating mode, e.g., the short circuit or output discharge
overshoot recovery, short circuit, and output discharge [25].
modes discussed above, renders the same contribution to the
During overshoot recovery, the output recovers from overshoot
output edge for ramp and . The overshoot depends on the
due to an initial input switching event; the short-circuit mode
start-voltage level, however as long as the start voltages are
occurs when both the PMOS and NMOS conduct (but with
well below the “comparator input window” then the overshoot
different currents so non-zero output slope), resulting in “short
at the output can recover before the input reaches that window,
circuiting” of the supply; the output-discharge mode refers to
so its contribution to delay can be negligible.
the mode with only the NMOS on. For different input slopes,
To intuitively summarize, any (correlated) differences be-
the three modes contribute differently to the output transition
tween ramps at the comparator input tend to cause INL error.
time, which is another source of INL in a DTC. This mecha-
The proposed constant-slope method modulates delay by
nism applies to any comparator that passes through different
changing the start voltage while keeping the critical threshold
operating modes during its input and output transitions.
part of a ramp unaltered. Thus all ramps have the same shape
To avoid the INL error associated with variable slope, we
in the “comparator input window”, leading to the same prop-
propose the constant-slope method in which the ramps keep a
agation delay through a comparator or buffer stage, which
constant shape above , whose effect on a comparator
minimizes INL errors. In variable-slope method, the slope is
is modeled in Fig. 5. Two rising ramps and at the input of
different among all ramps in the “comparator input window,”
the comparator have different start voltages but the same shape
so it may introduce significant INL through comparator as
above . A delay difference is sensed by the comparator to
shown in the next sub-section.
produce two corresponding falling edges at the output.
Actually, the output of a practical comparator responds to a
C. Simulation
range of input voltages and modelling it as a simple comparator
with one exact threshold is somewhat simplistic. Instead of a The setup in Fig. 6 is used to simulate the INL for an ideal
threshold, it is perhaps better to talk about a “comparator input input ramp signal. Circuit simulations were done in a 65 nm
window”, for example between and in Fig. 5. When CMOS technology at 1.2V supply. In clocking applications, a
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4 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 6, JUNE 2015

Fig. 6. INL simulation bench to compare the variable and constant slope
methods.

Fig. 8. Simulated INL for the constant-slope method at 100 ps full-scale delay:
only 15 fs maximum INL is found compared to 1.4 ps in Fig. 7.

Fig. 9. Block diagram of the implemented DTC ( -Noise Buffer).

Fig. 7. Simulated INL for the variable-slope method with 110 ps full-scale
delay: 1.4 ps maximum INL results. III. DTC DEMONSTRATOR CHIP DESIGN
To demonstrate good INL in practice, a DTC chip has been
implemented in 65 nm CMOS with 1.2 V supply. Fig. 9 shows
simple inverter is often used to implement the threshold com- the block diagram of the chip. The DTC-core is a voltage-con-
parison and can also act as a buffer to produce a steep output trolled variable-delay element, which consists of a low-noise
edge. In Fig. 6, after the first inverter acting as a comparator, a buffer (LNB), a ramp generator, and a threshold comparator.
four-stage inverter chain of identical inverters is applied to boost The amount of delay is controllable by a 10 bit DAC. The DTC
the slope to values close to the technology-dependent speed is driven by a sine-wave from a crystal oscillator (XO), and its
limit (e.g., 50 100 GV/s in 65 nm). This is for instance desired output delivers a rectangular-wave clock with a variable delay.
in sampler or phase detector applications, to precisely define the An inverting buffer with output impedance drives the off-
timing. chip transmission line for measurements. We will discuss the
To simulate the variable-slope case, 100–300 ps rise time design of the main blocks in the following subsections, and will
from GND to VDD was used, ideally resulting in 50–150 ps also discuss INL error sources.
delay at half-VDD comparator threshold, so 100 ps delay-con-
trol range. The simulation results are shown in Fig. 7 which have A. DTC-Core
an actual range of 110 ps, as the inverter threshold is not exactly Fig. 10 shows the schematic of the DTC-core. Its sub-blocks
half-VDD. 100 steps were taken over the whole delay range and are discussed below.
a maximum INL of 1.4 ps is found, which is in the same order 1) Low-Noise Buffer: The low-noise buffer converts a sine-
of magnitude as results found in literature [1], [2], [7]. wave into a rectangular-wave with low added jitter. The noise
For the constant-slope case a variable start-voltage range of the first stage is critical given the relatively low slew-rate of
from 0 to 0.2 V was used (motivated later in this paper). Map- a sine-wave from a 55 MHz crystal. As only one edge is critical,
ping this range to a 100 ps delay, the rise time is 600 ps from 0 big NMOS transistors are used for low noise while the PMOS
V to 1.2 VDD and 500 ps from 0.2 V to 1.2 VDD. Simulation is small and is controlled by its driver in such a way that simul-
results in Fig. 8 show a maximum INL of only 15 fs, about two taneous conduction of the PMOS and NMOS is reduced [26].
orders of magnitude lower than for variable slope. This clearly The driver (D1) of the PMOS is shown in Fig. 11, which pro-
demonstrates the INL advantage of the constant-slope method, duces a small duty cycle therefore low supply “short-circuit”
via the example of a simple inverter as a comparator. current. The big “poor man's cascode” NMOS in Fig. 11 (sized
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RU et al.: A HIGH-LINEARITY DIGITAL-TO-TIME CONVERTER TECHNIQUE: CONSTANT-SLOPE CHARGING 5

Fig. 10. Circuit schematic of the DTC-core: B1/B2/B3 are buffers made of two inverters all using regular- MOSFET; D1/D2 are drivers made of two inverters
using a mix of regular- and high- MOSFET as shown in Fig. 11.

Fig. 12. Pulse generator producing used in Fig. 10 with nominal 0.7 ns
width; the 20 fF contributes to which helps to fit in the overall timing
plan while the 100 fF contributes to which determines the pulse width.

Fig. 11. PMOS driver D1 consisting of two inverters using a mix of reg-
ular- and high- MOSFET to produce duty cycle; input and
output waveforms of the low-noise buffer showing its PMOS is only on for and form a current mirror with 10:1 ratio to create
duty cycle when the lower two NMOS FETs are off. a charging current, derived from an external bias current
for flexibility. The charging current can be up to a few mA,
but the average current consumption is on the order of a few
2000/0.06) helps to boost the output impedance, without re- hundred A because only draws current during the ramp,
quiring a dedicated bias voltage. Therefore the voltage gain which is only a small fraction of the clock period. A 6 pF ca-
around the zero-crossing points of the input rising edges is in- pacitor to VDD helps keep the gate voltage of stable and
creased and so is the falling-edge steepness at the output node so its current. Then the different start voltages at node
, which benefits timing jitter. have much reduced effect on and . acts as switch
2) Ramp Generator: The core of the ramp generator in that starts the ramp, but also as cascode transistor to improve
Fig. 10 consists of that produce the charging current the output resistance of the current source , and hence the
to capacitor to realize a ramp voltage. In every cycle of the linearity of the ramp voltage.
DTC, node is first reset to GND via , then pre-charged Because delay is defined as , for a linear
to via , after which a ramp takes delay, it is important to realize a constant current source and ca-
place. The timing of the reset and pre-charge of and the pacitance, during the first part of the ramp that defines delay via
ramp is controlled by three signals which are all derived from different values. At a 1.2V supply, this requirement limits
the same input: , and . Produced by LNB the in our circuit from GND up to about ,
with two buffers, delivers the critical edge that activates where still remains well in saturation and acts well as cas-
to start the ramp. The driver D2 producing is the code. When a ramp goes beyond , would gradually
same as D1 shown in Fig. 11. The pulse generator producing enter the triode region, however this does not cause INL, be-
is made of an AND gate with two inputs whose delay cause it is a common effect, i.e., the same waveform is shared
difference defines the pulse width as shown in Fig. 12. for all ramps beyond .
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6 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 6, JUNE 2015

The linear poly resistor defines based on current C. 50 Output Buffer

. The nonlinear switch resistance of has negli-
gible contribution to INL if , which can be under- To be able to measure the DTC, an output buffer is designed
stood by applying Thévenin's theorem where and are which includes an inverter and an integrated pull-up re-
in series. The linear metal capacitor in parallel to the non- sistor (see Fig. 9). When connected to an off-chip cable and
linear parasitic capacitance at node defines the slope of the equipment with to ground, the buffer output establishes a
voltage ramp. This improves linearity as the combined capaci- DC bias voltage nicely around half-VDD. The inverter is sized
tance is less dependent on voltage. to provide around swing at the matched output so that
Given a supply voltage, the usable start-voltage range is lim- the variation of inverter output resistance does not have much
ited. If the voltage range is fixed, to achieve a larger delay re- effect on the output impedance matching.
quires a lower slope (i.e., slower ramp), posting a delay-jitter
trade-off. D. Error Sources
3) Threshold Comparator: The threshold comparator uses
a simple inverter to sense the ramp voltage created at node . A DTC is usually meant to produce a well-controlled amount
The nominal threshold voltage of the inverter was designed to of delay, however non-idealities such as noise, distortion,
be around half-VDD ( 600 mV), which is much larger than process-voltage-temperature (PVT) variations, and mismatches
the 200 mV maximum . Buffer B3 (two scaled-up inverters) introduce timing errors.
steepens the output edges. For a switching circuit such as a DTC, the jitter is often lower
with higher signal slope or larger transistor size and current. The
B. Digital-to-Analog Converter jitter of the implemented DTC is dominated by the LNB due to
To save design time, an existing 10 bit current-steering DAC the low sine-wave slope at 55 MHz input.
IP-block is co-integrated on the same chip. The segmented DAC Other than jitter, the timing error of a DTC can be divided
is divided into two sub-DACs, a 5 bit binary-weighted sub-DAC into offset, linear and nonlinear errors. An offset error means a
for LSBs and a 5 bit unary-weighted sub-DAC for MSBs. For common delay shift to all delay steps while the relative delay
its performance, we rely on the specification datasheet, which from one step to another remains unchanged; a linear error
however is not very detailed. Hence, we resort to calculations means that all delay steps are scaled by the same ratio, i.e.,
and estimations to derive some of the specifications. full-scale delay changes but delay steps are still equal and there
The DAC is specified to operate at 2.5 V supply, but it can is no DNL or INL; nonlinear errors render a code dependent
also operate at 1.2 V with a more limited output voltage range. step size, leading to DNL/INL.
The DAC specification indicates a maximum INL of 2 LSB If the threshold voltage of an inverter varies over PVT, in a
( 0.2%) at an output range of 0–800 mV and a 400 MHz speed. variable-slope method, this will cause offset and linear errors
The INL should improve when only 0–200 mV output range and (so the full-scale) which can be seen in Fig. 2 by moving
55 MHz speed are used in this design. up and down, but potentially also different INL. For instance,
The DAC noise is not found in the IP's datasheet. A first-order INL in percentage changes if nonlinear errors scale differently
calculation was done assuming the thermal noise is dominant at than the full-scale delay does. On the other hand, a -shift
a low switching speed of 55 MHz. For a current-steering DAC, means that the inverter characteristic changes, which often also
its current noise can be modelled as: leads to INL change. Furthermore, a practical ramp is not a per-
fectly straight line and its slope is different at different voltage
levels (see Fig. 1(b)). When a ramp passes through an inverter
for which PVT changes the threshold, the inverter sees a dif-
ferent slope, so the nonlinear effects change, and INL values
change. Instead, for the constant-slope method only an offset in
(2)
delay occurs, which can be seen in Figs. 2 and 5. It does not
cause linear errors because the delay from one ramp to another
where is the equivalent DAC noise bandwidth defined as is the same at any voltages. As explained in Section II, it also
with and in Fig. 10, and is the intrinsically does not cause nonlinear errors by comparator no
overdrive voltage of the DAC current sources. matter what the threshold is.
The DAC current noise is converted to voltage by and As the constant-slope method minimizes the INL associated
then produces timing jitter, which can be modelled as: with comparator, the remaining error sources are mostly in ramp
generation, which can be minimized by design.
(3) In practice, the start-up behavior of a ramp is not instanta-
neous, but rather has an initial over-shoot due to capacitive cou-
In our design, is equal to 200 mV/100 ps; pling and a rounded start-up waveform because a charging cur-
; ; ; . rent is not fully turned on instantaneously. Simulation indicates
Even assuming a rather low , the result of (3) is that this effect is largely independent of the start-voltage for
43 fs, i.e., LSB for a 10 bit DAC and a 100 ps full-scale the used 0–200 mV -range. This mainly adds an offset to
delay. Note that this is at the maximum DAC output current, the delays.
i.e., the worst-case noise. A rising slope at node in Fig. 10 can be written as
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RU et al.: A HIGH-LINEARITY DIGITAL-TO-TIME CONVERTER TECHNIQUE: CONSTANT-SLOPE CHARGING 7

(4)

Equation (4) can be re-arranged to derive the delay :

(5)

Equation (5) shows this delay is proportional to an RC time

constant which is subject to PVT variations, introducing a linear
error. The DAC current and the bias current can be derived
from the same current source, so PVT variations are removed by
taking the current ratio. However, any mismatch in current mir-
rors will introduce linear errors. Many applications will require
the delay range to be aligned to another clock, e.g., a VCO pe-
riod in a PLL, which will then also calibrate these linear errors. Fig. 13. Simulated INL of the DTC-core at 100 ps full scale, with ideal DAC,
The INL for the constant-slope design is related to the using a PSP model for the 65 nm CMOS transistors.
circuit nonlinearity caused by the varying , including the
nonlinearity of current source , the nonlinearity of junction
capacitance at node , and the nonlinearity of pre-charge
switch . The former two affect the ratio and therefore
the slope, while the latter two affect the settling of due to
nonlinearity in the RC time constant. Note that these nonlin-
earities have been largely reduced by measures discussed in
Section III-A2), including cascode , linear , and linear
. Furthermore, a relatively small range of 200 mV
helps limit these nonlinear effects; also, a 55 MHz operating
frequency gives enough settling time to reduce the settling error
of .
Another source of INL comes from the DAC. The mismatch
of the DAC cells and the nonlinearity of its output impedance
affect the DAC INL and therefore , directly translating to
the delay INL as shown in (5). Note that the DAC INL similarly
hurts the delay INL in a variable-slope method. This effect re-
lates to the DAC design, and is not intrinsic nor distinctive for Fig. 14. Chip photo of the DTC realized in 65 nm CMOS with active area of
mm .
the constant or variable slope method.

E. Simulation Results
Using a PSP Model, the circuit in Fig. 10 has been simu-
lated together with an ideal DAC producing 0–200 mV as .
The input of the LNB is driven by a 55 MHz sine-wave with
1.2 swing.
The DTC INL is defined similarly to that of a DAC: assuming
the total number of bits is , the INL at digital code is then
defined as
Fig. 15. Setup for INL measurements in the time domain using an oscilloscope.
(6)

where is the measured delay at code and is the mea- due to the smaller charging time so less noise integration. The
sured full-scale delay. LNB alone is simulated to have a jitter of 81 fs, which is the
The simulated INL is shown in Fig. 13 with 200 simulation biggest contribution due to its low-slope sine-wave input.
steps at 100 ps full-scale. The maximum INL error is less than
50 fs (0.05%) and mainly due to non-ideality in the ramp gener- IV. MEASUREMENTS
ation such as the residual current-source nonlinearity. Some un- The chip design shown in Fig. 9 was fabricated in 65 nm
certainty in results is likely due to simulation accuracy at such CMOS and a chip photo is shown in Fig. 14. The active area of
small time resolution (note that the pattern is rather regular). the DTC-core and DAC is about mm , each taking roughly
The RMS jitter was also simulated within a bandwidth up to half. The chip is packaged in a 32-pin Heat-sink Very-thin Quad
half of the clock rate, resulting in 109 fs and 99 fs at of Flat-pack No-leads (HVQFN) package. All measurements were
0 mV and 200 mV, respectively. Lower jitter at higher is performed on PCB.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

8 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 6, JUNE 2015

Fig. 16. Setup for INL measurements in the frequency domain using the method of [27].

A. Delay INL Note that the start voltage now is defined by , so each
Fig. 15 shows a simplified setup used to measure DTC delay voltage level determines a position of the DTC output rising
and INL in our time-domain experiment. The chip (DUT) re- edge; a square wave at produces a delay/phase modula-
ceives a 1.2 Vpp sine-wave input from the 55 MHz crystal os- tion at the DTC output, because its rising edge jumps period-
cillator (XO) and delivers a 0.6 Vpp rectangular-wave output to ically between two positions. This phase modulation appears
a 50 oscilloscope (OSP). The crystal signal is also used as in the frequency domain as a couple of sidebands, where the
reference to trigger the sampling oscilloscope. The chip is pro- strongest occurs at an offset frequency from which
grammed from a computer via an integrated two-pin serial-bus is the carrier frequency of the DTC output (see Fig. 16). These
interface. Using this setup, we estimated the deterministic part sidebands can be measured using a spectrum analyzer. Only the
of the INL to be in the order of 150 fs at 102 ps full-scale rising edges of DTC output are programmable, therefore a fre-
delay (0.15%) and 250 fs at 304 ps full-scale (0.08%). How- quency divider by 2 is inserted between the DTC chip and the
ever, the results contain large measurement uncertainties on the spectrum analyzer, in order to discard the falling edges of the
same order as the estimated INL therefore it is difficult to assess DTC output.
the reliability of these measurements and draw conclusions. Just like the modulating signal , the phase change of the
Because the time-domain method is not good enough to di- signal at the divider output is also a square wave. By using the
rectly measure the INL of the chip, we developed an indirect standard modulation theory [28], it can be shown that the rela-
method for the characterization of the DTC-core, that avoids tive strength of the first sideband (either on the left or right side
the oscilloscope and instead uses a spectrum analyzer. The basic of the carrier, see Fig. 16) in dBc is related to the delay step pro-
idea is to periodically modulate the delay of the DTC between duced by the square wave as the following equation [27]:
two distinct values, which results in a spur [27]. Such a spur
can be measured with high fidelity in the frequency domain, as
only noise and interference in a small frequency band around the (7)
spur frequency will pollute the results. In contrast, a sub-sam-
pling oscilloscope is wideband, and hence sensitive to noise and where is the delay step of the rising edge, produced by the
interference in a wide band. voltage step of the th square wave , and is the period
The proposed measurement setup is shown in Fig. 16. of the DTC output.
The on-chip DAC is off as its serial digital interface is too To achieve high accuracy in spur measurements, it is benefi-
slow for the modulation frequency. Instead, an external DAC cial to nominally always measure the same spur strength: range
(Agilent M8190 A Arbitrary Waveform Generator) was used switching in a spectrum analyzer is avoided in that way and the
to produce a square-wave voltage that switches slowly nonlinearities in the power detector are minimized. In terms of
compared to the input XO MHz MHz . DAC codes, in one code-sweep the full code range is covered
We used 10 bits as our full-scale out of the DAC's 14 bit with 40 identical code steps. Each code step produces a square
maximum range. We measured the external DAC performance wave in terms of , where the amplitude is fixed (so nomi-
and found that its INL is below 0.5 LSB (0.05% referring to nally equal delay steps and spur strength), but DC levels are in-
10 bit full-scale) which is not the bottleneck in our DTC-INL creasing from one code step to the next. For each code step, we
measurement. measure a spur level which is then converted to a delay step
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

RU et al.: A HIGH-LINEARITY DIGITAL-TO-TIME CONVERTER TECHNIQUE: CONSTANT-SLOPE CHARGING 9

Fig. 17. Measured INL at 71 ps full-scale using the proposed method ( Fig. 19. Measured INL at 19 ps full-scale using the proposed method (
to 64.8 mV); the L and R curves refer to measurements from the left and right to 33.6 mV).
spur-sidebands respectively.

Fig. 18. Using an external voltage-mode DAC where the voltage signal
goes through an extra static switch which contributes additional INL, and
the linear is not effective to reduce the nonlinearity of compared
to using current-DAC.

via (7). Due to nonlinearity there will be variations in the mea- Fig. 20. Measured INL at 189 ps full-scale using the proposed method (
to 101.5 mV).
sured . These variations correspond to DNL
errors which can be calculated with the following equation:

(8) therefore the linear in Fig. 10 is not effective in this case

to help the nonlinear of . As shown in Fig. 18,
where is the ideal delay step produced by each square wave, goes through an extra on-chip static switch , which con-
which is estimated as the average of all measured values for tributes additional nonlinearity. Experiments show that using
a complete code-sweep. The INL is the cumulative sum of the external voltage-DAC degrades INL and limits the linear
DNL. range to about 100 mV, reducing the linear delay range, com-
Both low-frequency and high-frequency noise exist in the pared to the case with an on-chip current-DAC.
measurements. We chose to do each sweep (40 points) within The full-scale delay is varied roughly from 20 to 200 ps.
10 minutes, and then repeat the procedure 50 times, so 50 nom- The measured INL of 19 ps and 189 ps full-scales are shown
inally equal data sets result. In this way, a single INL plot of in Figs. 19 and 20, respectively. The maximum INL is 64 fs
each sweep is less sensitive to low-frequency noise, and an av- for 19 ps full-scale (normalized INL 0.34%, 8.2 bits), and
erage of 50 helps to remove high-frequency noise. 328 fs for 189 ps full-scale (normalized INL 0.17%, 9.2 bits),
The INL curve from this method for a full-scale delay of showing good linearity over a large delay range.
71 ps, using 40 delay-steps, is shown in Fig. 17. Both the left and Very different settings are used for these different full-scales,
right spur-sidebands were measured and they agree within about in terms of DAC voltage range, charging current value, and
50 fs with each other. The two y-axes in Fig. 17 indicate, respec- charging capacitor value. The different contributions to nonlin-
tively, the absolute INL in femtoseconds, and its normalized earity (such as current source, switch resistance, parasitic capac-
value to the full-scale delay, i.e., INL in percentage. The abso- itance, and DAC) will increase or decrease at different settings.
lute INL is within 235 fs. The normalized INL is within 0.33%, Therefore, different subtle nonlinearity mechanism can be dom-
corresponding to an effective resolution of inant at different full-scales, so the INL shape or even polarity
8.2 bits, when only considering the INL-limitation. can change. It is difficult to exactly pinpoint all mechanisms and
The measured INL is the combination of the chip and the ex- match them to a model. On the other hand, we repeated many of
ternal DAC, while the on-chip DAC is not involved. The ex- the measurements and find reproducible results, while the mea-
ternal DAC is a voltage-mode DAC instead of a current-DAC, sured curves from the two spur-sidebands also match each other
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

10 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 6, JUNE 2015

TABLE I
COMPARISON WITH OTHER RECENT WORK ON DTC PERFORMANCE

with the setup in Fig. 21(a). Within the PLL loop bandwidth,
the DTC noise is conveyed to its VCO output. As the VCO runs
at a much higher frequency than the reference clock (2.2 GHz
versus 55 MHz), a given timing jitter corresponds to more phase
variation making phase-noise measurements easier. The on-chip
DAC is used in the noise measurement.
At the DTC setting with about 100 ps full-scale delay, the
total measured phase noise from the DTC and the PLL together
is shown in Fig. 21(b). The in-band phase noise floor at 2 MHz
is dBc/Hz at a 2.2 GHz carrier with less than dB vari-
ation for all digital codes, while the PLL alone without DTC
showed dBc/Hz at 2 MHz [29]. This shows the DTC is
suitable for low-phase-noise applications. The integrated jitter
from 100 kHz to 100 MHz is 210 fs for the DTC and the PLL to-
gether, at a loop bandwidth of 5 MHz. Note that the DTC should
only contribute significantly to the noise within the loop band-
width due to the PLL low-pass transfer function from the refer-
ence path to the VCO output.

C. Benchmark
Table I compares this DTC with other recent work. This work
demonstrates the finest time resolution and achieves the best
Fig. 21. (a) Setup for phase noise measurement. (b) Measured phase noise of
the DTC as a reference buffer for a low-jitter PLL (reference spur at 55 MHz).
INL when benchmarked at a similar full-scale delay. To eval-
uate a DTC design, it is more appropriate to compare INL for
similar full-scale delays, because not only absolute INL but also
in all three cases. These results indicate that very competitive normalized INL often changes with full-scale delay for the same
performance can be achieved. DTC. At similar full-scale and in terms of normalized INL in
percentage, at 71 ps delay compared to [5] and [7] the INL is
B. Phase Noise and Jitter 15x better; at 189 ps delay compared to [1] and [2] the INL
As mentioned in Section III-E, the simulated jitter is about is 6x better. A recent DTC [4] shows a similar INL in per-
100 fs, which is less than the jitter of the oscilloscope we used. centage (0.18%), but our work achieves this INL at a 3x smaller
Hence a time-domain measurement was meaningless. Since the full-scale delay and 3x finer resolution. Note that achieving the
DTC is running at the crystal frequency, direct phase-noise mea- same INL in percentage at a smaller full-scale delay is more
surement is also challenging, as it represents a very low phase- difficult, as small absolute delay errors become more relevant.
noise level at 55 MHz carrier. Also the measurement should Based on information provided in Section IV-A, we expect that
only be sensitive to the rising edge of the DTC output. using the on-chip DAC would give even better INL.
In an attempt to still quantify the phase noise, we used a pre- This work is also competitive in terms of jitter, and certainly
viously published low-jitter PLL [29] as a frequency multiplier for in-band phase noise when applied in a PLL. At 1.2 VDD,
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

RU et al.: A HIGH-LINEARITY DIGITAL-TO-TIME CONVERTER TECHNIQUE: CONSTANT-SLOPE CHARGING 11

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 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

12 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 50, NO. 6, JUNE 2015

Jiayoon Zhiyu Ru (M'09) received the Bachelor April–August 2001, he extended his RF expertise during a sabbatical at the
degree from Southeast University, Nanjing, China, Ruhr Universitaet in Bochum, Germany. Since 2006, he has been an Associate
in 2002, the Master degree from Lund University, Professor, teaching Analog and RF IC Electronics courses. He participates in
Lund, Sweden, in 2004, and the Ph.D. degree from the CTIT Research Institute, guiding Ph.D. and M.Sc. projects related to RF
the University of Twente, Enschede, The Nether- CMOS circuit design with focus on software-defined radio, cognitive radio and
lands, in 2009. beamforming.
In 2004, he did the Master project with Ericsson in Dr. Klumperink served as an Associate Editor for the IEEE TRANSACTIONS
Lund, working on digital TV receiver. From 2005 to ON CIRCUITS AND SYSTEMS II (2006–2007), IEEE TRANSACTIONS ON CIRCUITS
2009, he did Ph.D. research in the IC-Design group AND SYSTEMS I (2008–2009), and IEEE JOURNAL OF SOLID-STATE CIRCUITS
of Twente, working on software-defined radios. (2011–2013). He is a member of the technical program committees of the IEEE
From 2010 to 2012, he did postdoctoral research in International Solid State Circuits Conference (ISSCC) and IEEE RFIC Sympo-
the same group on DTC and digital PLL. In 2011, he was a visiting scientist sium. He holds several patents, has authored and co-authored more than 150
at MIT. From 2012 to 2014, he was with MediaTek in Boston. He is currently internationally refereed journal and conference papers, and is a co-recipient of
with Qualcomm in San Diego, CA, USA. the ISSCC 2002 and the ISSCC 2009 Van Vessem Outstanding Paper Awards.

Claudia Palattella (S'13) received the M.Sc. degree Bram Nauta (M’91–SM’03–F’08) was born in 1964
(cum laude) in electrical engineering from the Po- in Hengelo, The Netherlands. In 1987 he received the
litecnico di Milano, Milan, Italy, in 2012. She is cur- M.Sc degree (cum laude) in electrical engineering
rently working towards the Ph.D. degree at the Inte- from the University of Twente, Enschede, The
grated Circuit Design group at University of Twente, Netherlands. In 1991 he received the Ph.D. degree
Enschede, The Netherlands. Her research interests in- from the same university on the subject of analog
clude frequency synthesis, oscillators, and discrete CMOS filters for very high frequencies.
time systems. In 1991 he joined the Mixed-Signal Circuits and
Systems Department of Philips Research, Eindhoven,
The Netherlands. In 1998 he returned to the Univer-
sity of Twente, as a Full Professor heading the IC
Design group. In 2014, he was appointed as a Distinguished Professor at the
University of Twente. His current research interest is high-speed analog CMOS
circuits, software-defined radio, cognitive radio, and beamforming.
Paul Geraedts (S’07–M’10) was born in Deventer, Dr. Nauta served as the Editor-in-Chief (2007–2010) of the IEEE JOURNAL OF
The Netherlands, in 1979. He received the M.Sc. de- SOLID-STATE CIRCUITS (JSSC), and was the 2013 program chair of the IEEE In-
gree in electrical engineering from the University of ternational Solid-State Circuits Conference (ISSCC). He served as an Associate
Twente, The Netherlands, in 2005. Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II (1997–1999),
He is currently working on analog-to-digital con- and of JSSC (2001–2006). He was in the Technical Program Committee of the
verters at Teledyne DALSA, Enschede, The Nether- Symposium on VLSI circuits (2009–2013) and is on the steering committee
lands. and program committee of the European Solid-State Circuits Conference (ES-
SCIRC). He is also a member of the ISSCC Executive Committee. He served
as Distinguished Lecturer of the IEEE, and is an elected member of the IEEE-
SSCS AdCom. He was a co-recipient of the ISSCC 2002 and 2009 Van Vessem
Outstanding Paper Awards and in 2014 he received the Simon Stevin Meester
Award, the largest Dutch national prize for achievements in technical sciences.

Eric A. M. Klumperink (M'98–SM'06) was born on

April 4, 1960, in Lichtenvoorde, The Netherlands.
He received the B.Sc. degree from HTS, Enschede,
The Netherlands, in 1982. After a short period in
industry, he joined the University of Twente in
1984, participating in analog CMOS circuit research
resulting in several publications and his Ph.D.
thesis “Transconductance Based CMOS Circuits”
(1997). In 1998, he became an Assistant Professor
at the IC-Design Laboratory in Twente and his
research focus changed to RF CMOS circuits. In