Karachi Institute of Economics &

Technology
College of Computing & Information Sciences

Digital Logic & Design

Lab Manual

Compiled by: Owais & Sabika

Karachi Institute of Economics &
Technology
College of Computing & Information Sciences

Digital Logic & Design

Lab Manual
Compiled by:
Owais & Sabika

CID: ______________ Semester: ______________

Student ID: ________________________________
Student Name: _____________________________
Instructor Name: ___________________________
2
 KARACHI INSTITUTE OF ECONOMICS & TECHNOLOGY
College of Computing & Information Sciences
Digital Logic & Design Lab Manual

Lab Course
Date Particulars Instructor Teacher
Signature Signature

Lab 1: Familiarization with digital trainer & basic logic gates

Lab 2: Basic Logic Gates

Lab 3: Basic Logic Gates & NAND Gate Application

Lab 4:Designing of digital adder and subtractor circuits.

Lab 5: 7-segment display operation

Lab 6:Designing of combinational circuits

Lab 7: Designing comparator and decoder circuits

Lab 8: Designing multiplexer & demultiplexer circuits

Lab 9:To design multivibrator circuits

Lab 10: To check Latch and Flip Flop Operation

Lab 11:Recirculating data and 2-bit binary counter

Lab 12:JK-Flipflop and Designing of decade counter

Lab 13: To check the read/write operation of RAM

Lab 14: To demonstrate binary up-down counter

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 INDEX

Table of Contents

Lab 1: Familiarization with digital trainer & basic logic gates 1

Introduction to Digital Logic Trainer AM-2000 1
Objective A: Familiarization with am-2000 trainer 3
Objective B: To check AND gate operation 5
Objective C: To check OR gate operation 7
Lab 2: Basic Logic Gates 9
Objective A:To check NOT gate operation 9
Objective B:To check NAND gate operation 11
Objective C: To check NOR gate operation 13
Lab 3: Basic Logic Gates& NAND Gate Application 15
Objective A: To check XOR gate operation 15
Objective B: construction of XOR gate by NAND gates 17
Lab 4: Designing of digital adder and subtractor circuits. 20
Objective A: To design half adder circuit byusing XOR,AND & NOT gates 20
Objective B: To design full adder circuit by using XOR,AND,OR & NOT gates 23
Objective C: To design half subtractor circuit byusing XOR,AND & NOT gates 25
Objective D: To design full subtractor circuit by using XOR,AND,OR & NOT gates 27
Lab 5:7-segment display operation 30
Objective A: To check the operation of common anode 7-segment display 30
Objective B: To check the operation of common anode BCD to 7-segment decoder 33
Lab 6: Designing of combinational circuits 36
Objective A:To generate the table of 2 by applying all design steps36
Lab 7: Designing comparator and decoder circuits 39
Objective A: To check the operation of 4-bit magnitude comparator 39
Objective B:To check the operation of 2 to 4 line decoder 42
Lab 8: Designing multiplexer & demultiplexer circuits 46
Objective A:To check the operation of 1 of 2 data selector/ multiplexer 46
Objective B: To employ a 74LS151 as a multiplexer and a 74LS138 as a demultiplexer
In a single line digital communication circuit 49
Lab 9: To design multivibrator circuits 52
Objective A: An Astable multivibrator 61
Objective B: A monostable multivibrator 61
Objective C: A bistable multivibrator 61
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Lab 10: To check Latch and Flip Flop Operation 63
Objective A:To check d-latch and flip flop operation 63
Objective B:Latching BCD data for displaying on7-segment display 68
Lab 11: Recirculating data and 2-bit binary counter 70
Objective A: To examine the recirculating data in a circular shift register 70
by using flip flop
Objective B: To design 2-bit binary synchronous counter using D-flipflop IC. 72
Lab 12: JK-Flipflop and Designing of decade counter 74
Objective A: The experiment is to use the J-K flip-flop according to its truth table 74
Objective B: To design a 4-bit synchronous decade counter using “JK-flipflop”. 77
Lab 13: To check the read/write operation of ram 80
Equipment 80
Theory 80
Procedure 81
Circuit Diagram 82
Lab 14: To demonstrate binary up-down counter 83
Fundamental Concepts 83
Up-down counter 86
MSI 193 87
Procedure

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 Preface

Logic Design in the modern era forms a major component of the Digital System Design process.
It also contributes with the derivation and synthesis of sequential and combinational switching
Circuits.

This manual contains sufficient material for the Logic Design Laboratory to supplement a
Comprehensive one-semester course in Digital Logic and Circuits. It is written to bridge the gap
between theoretical derivation of switching functions and their implementation .
We would like to explain the philosophy underlying the material presented in this manual. The
students are given situations as close as possible to reality so that they are aware of the types of
problems that occur in real systems. In line with this philosophy, the students are required to
wire-up their own circuits rather than using sophisticated black boxes with well-debugged
Circuitry hidden behind cosmetic block diagrams. In doing this, we expect students to get
exposure 10 all kinds real world problems and it will give them the patience to trace out bugs in
their own circuitry.

This manual requires no background in circuit theory or electronics and can be used for an
introductory course in Digital Logic. The logic gates are treated as black boxes that perform logic
operations.

All experiments included in this manual have been performed on the AM-2000 Logic Trainer
developed by Electrical Engineering Services. The experiments are performed using Low Power
Schottky TTL ICs.

The experiments included contain a large variety of difficulty levels. Some are as simple as
testing of gates and flip-flops, others include the design of counters, shift register and coding
circuits. The procedure for each experiment is given in small and easy to follow steps. Empty
tables are provided for convenience so that the students can fill them up while performing the
experiments. Results are also provided wherever needed for students instructor convenience.
Pin diagrams of ICs are also included where ever needed for easy reference, since the students are
not expected to be able to search for the information independently from data books/hand books
at this level.

For the convenience of the instructor and students, a list of tools and components required for
each experiment is also provided so that all the equipment can be organized before the
experiment begins.

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Course Title: Lab-1
Digital Logic & Design Familiarization with digital trainer & basic logic gates

LAB 1
Familiarization with digital trainer
& basic logic gates

Introduction to Digital Logic Trainer AM-2000:

AM-2000 logic trainer is a low cost, high performance digital logic teaching system. It is
designed to provide all the basic tools necessary to conduct logic experiments. It is also ideally
suited for developing, debugging, integrating and testing digital systems.
AM-2000 becomes a high performance 16 and 32 bits (80286 and 80386) CPU microcomputer
teaching system for PC AT computer when an interface card is added to the trainer.

Specifications

 Input voltage 220V 50 Hz AC

 Circuit type TTL compatible
 J 6 lamp monitors-transistor buffered
 8 logic switches
 2 logic switches with debouncing circuitry
 Logic probe with pulse detection
 One clock timer- 7 to 65Hz (Optional for two ranges)
 Three 7-segment decoders / drivers displays
 Output voltage= +12V -12V, and +5V at l A

Components of the AM-2000 Trainer

 Sixteen LED's with drivers

 Eight logic switches with two Outputs, each the complement of the other
 Two simple logic Switches with debouncing circuit
 Logic probe with LOW, HIGH and PULSE indicators
 Two push pull switches for generating negative-going pulse
 One timer based on NE 555 with variable control
 Three 7-segment displays with BCD decoders/drivers
 One linear variable 10 K
 One linear variable 100 K
 Computer interface card (optional)
 Two or four breadboards

1|Page
Course Title: Lab-1
Digital Logic & Design Familiarization with digital trainer & basic logic gates
Special Features of the AM-2000 Trainer

1.1 Regulated Power Supply

Power supply with short circuit protection that provides +5V, +12V and -12V with power
indicators and protection fuse. Push-in wire terminals at right hand edge of the trainer are
provided for each supply.

1.2 State Monitors

State monitors are simply light-emitting diodes, which are used to indicate the state of a logical
output. Lighted diode represents a "1" and an unlighted diode represents as "0". The input to
these monitors LED's arc available at SBB-63 board which are labeled as:
LO L1 L2 L3 L4 L5 L6 L7 L8 L9 L1O L11 L12 L13 L14 L15
In order to avoid any current loading on the various test circuits, LED's are provided with
drivers.

1.3 Logic Switches

Logic switches, S2 through S9 are speed types of switches, designed to produce two TTL
compatible logic outputs which are complement of each other. Switches SO and S 1 are simple
logic switches with each has one output and provided with debouncing circuitry. The output
from
these I 0 switches are made available at SBE-63 board and is labeled as:
SO Sl S2 S2’ S3 S3' S4 S4’ S5' S6 S6' S7 S7' S8 S8' S9 S9'

1.4 Digital Display

Three 7-segment decoders/drivers and displays are provided. Each consists of a 74LS47 BCD to
7-segment decoder/driver and S806RWB common anode display. The BCD input for these three
7-segment displays are made available at SBE-63 board and are labeled as:
8421 8421 8421
If a BCD logic input is applied to the four input tem1inals (8 4 2 1), it will be decoded and
displayed on the corresponding display.
The 7-segment display is a common anode type and cannot be directly interchanged with the
common cathode type.

1.5 Digital Logic Probe

Digital logic probe is provided for detecting and indicating logic states as well as pulses.
The indicator system consists of three LED's. A red LED lights up to indicate logic 1. While a
yellow LED lights for logic 0. A green LED comes ON for approximately 500 ms to indicate a
pulse without regard to its width.

2|Page
Course Title: Lab-1
Digital Logic & Design Familiarization with digital trainer & basic logic gates

This feature enables one to observe a short-duration pulse that would otherwise not be seen
on the logic l and 0LED's.In operation, for a logic 0 input signal, both the 0 LED and the pulse
LED will come ON. For logic 1 input only the logic l LED will be lit, the logic probe will indicate if
a negative-going pulse has occurred at the input. Pulse LED will be ON for approximately 500
ms to indicate a negative-going pulse.

1.6 Clock Timer

A 555-clock/timer circuit with a range of 7 to 65 Hz is used as a pulse source. The frequency is

adjusted by turning the variable 500K pot provided on the left hand side edge of the trainer.
The output is available at SBB-63 board, which is labeled as CLK.

Objective A: Familiarization with AM-2000 trainer

All experiments included in this manual have been performed on the AM-2000 logic trainer
using low power Schottky TTL ICs. Before starting actual experiments, let us first familiarize our
self with the use of AM-2000 trainer.

Measuring Power Supplies

Now that you're ready to experiment it may be worthwhile to become familiar with the
hardware. Connect the AM-2000 Trainer to the220V AC power source and turn ON the Trainer.
Observe +5V, +12V and -l2V LED's ON, indicating these supplies are available for
Experimentation. Verify +5V, + 12V and -12V voltages using a multimeter.

Measuring Logic Levels

Try using the LED's (LO-Ll5) to monitor the logic levels.

 Connect +5V power to the LED indicator LO. The LED should be ON indicating logic 1.
 Connect LED indicator LO to GND. The LED should be OFF indicating logic 0.

Test the Clock

Rotate the timer rate knob to counter clockwise position until extreme position is reached.
Connect the output CLK to the input of LED L0. The light should blink ON and OFF slowly. The
light blinks rapidly as the timer rate knob is rotated clockwise. It will stop blinking at some
point,and then LED will be ON indicating a higher frequency.

Measure the Logic Level coming from one of the Logic Switch (S2 to S9)

Connect the outputs S2 and S2' of switch (S2) to LO and L1 respectively. The LED's should
indicate the logic levels originating from the S2 switch.

3|Page
Course Title: Lab-1
Digital Logic & Design Familiarization with digital trainer & basic logic gates

 Set Switch S2 at a higher position, L0 should be OFF and Ll should be ON.

 Set switch S2 at a lower position. L0 should be ON and L1 should be OFF.

Measure Logic Level by using the Logic Probe

A logic probe is provided to display status of a point in a digital circuit. Connect the
Pointed probe to the input of the logic probe and make contact at the desired point. If the logic
level is low, LED marked LOW will lit and if logic level is high, the LED marked HIGH will lit.

Pulse Detection

Connect switch S2 output to the input of the logic probe. Generate negative-going pulse
by setting S2 to HIGH-LOW and then back to HIGH (1-0-1) quickly. Observe the pulse LED will
be ON for approximately 500ms indicating the detection of negative - going pulse.

BCD Logic Input

Connect Switches S2, S3, S4 and S5 to the four input marked as 8 4 2 1 on the SBB-63
board. Applied BCD input using switches, it would be decoded and displayed on the 7-Segment
Display.

 Set switch S2 at logic ' 1' and rest of the switches at 0, BCD digit '8' will be displayed.
 Set switch S3 at logic ' 1' and rest of the switches at 0, BCD digit '4' will be displayed.
 Set switch S4 at logic ' l' and rest of the switches at 0, BCD digit '2’ will be displayed.
 Set switch S5at logic ' l ' and rest of the switches at 0, BCD digit '1' will be displayed.
 Set switches at the appropriate position to display BCD numbers (0-9).

4|Page
Course Title: Lab-1
Digital Logic & Design Familiarization with digital trainer & basic logic gates

Objective B: To check the operation of AND gate according to the AND's

truth table, using the IC 74LSO8.
Components:
 74LS08 X l

Tools:
 AM2000 Trainer.
 Multimeter.
 Cutter.
 Single Core Wire.
 Tweezer.
 Pair of Pliers.

Diagram

Procedure:

1. Connect the AM2000 trainer to the 220V AC power supply.

2. Tum on the trainer and verify the voltage of the power supply using the multimeter.
It should be +SV exactly.
3. Install the IC 74LS08 on the trai11er s breadboard.
4. Wire the circuit according to the diagram in figure 1.1 by consulting AND gate IC's.
Data sheet in figure 1.2
5. Use any of the two logic switches from: S2 to S9 for inputs A and B respectively.
6. For output indication use any of the LED's from (LO- Ll5)
7. Supply the +5V and GND to the pins A and 7 of the IC.
8. Test all the possible combinations of inputs and verify the output according to the truth
table of AND gate.
9. Fill the truth table given below according to the results.

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Course Title: Lab-1
Digital Logic & Design Familiarization with digital trainer & basic logic gates

Truth Table for AND Gate

Inputs Outputs

A B AND

0 0

0 1

1 0

1 1

In Case of Trouble:

1. Check the power supply.

2. Check the VCC and GND at pins 1' and 7 of the lC.
3. Check all the wire connections…
4. Check the circuit wiring and remove the breaks.
5. Check the IC using truth table.

6|Page
Course Title: Lab-1
Digital Logic & Design Familiarization with digital trainer & basic logic gates
Objective C: To check the operation of OR gate according to the OR's truth
table, using the IC 74LS32.

Components:
l. 74LS32 X 1

Tools :
I. AM-2000 Trainer.
2. Multimeter.
3. Cutter.
4. Single Core Wire.
5. Tweezer.
6. Pair of Pliers.

Diagram:

Procedure:
1. Connect the AM-2000 trainer to the 220V AC power supply.
2. -Turn on the trainer and verify the voltage of the power supply using the multi-meter. It
should be +5V exactly.
3. Install the IC 74LS32 on trainer's breadboard.
4. Wire the circuit according to the diagram in fig.1.3 by consulting OR gate ICs data sheet in
figure 1.4.
5. Use any of the two logic switches S2 to S9 for inputs to OR gate.
6. For output indication use any of the LED's from (LO - LIS).
7. Supply the VCC= +5V and GND to the pins 14 and 7 of the IC.
8. Test all the possible combinations of inputs and verify the output according to the truth
table of OR gate.
9. Fill the truth table given below according to the results.

7|Page
Course Title: Lab-1
Digital Logic & Design Familiarization with digital trainer & basic logic gates

Truth Table for OR Gate

Inputs Outputs

A B OR

0 0

0 1

1 0

1 1

In Case of Trouble:

1. Check the power supply.

2. Check the VCC and GND at pins 14 and 7 of the IC.
3. Check all the wire connections.
4. Check the circuit wiring and remove the breaks.
5. Check the IC using truth table.

8|Page
Course Title: Lab-2
Digital Logic & Design Basic Logic Gates

LAB 2
Basic Logic Gates

Objective A: To check the operation of NOT gate according to the NOT's

truth table, using the IC 74LS04.

Component:
1. 74LS04 X 1

Tools
1. AM-2000 Trainer.
2. Multimeter.
3. Cutter.
4. Single Core Wire.
5. Tweezer.
6. Pair of Pliers.

Diagram:

Procedure:
1. Connect the AM-2000 trainer to the 220V AC power supply.
2. Turn on the trainer and verify the voltage of the power supply using the multimeter. It should
be +5V exactly.
3. Install the IC 74LS04 on the trainer's breadboard.
4. Wire the circuit according to t11e diagram in figure.2.1 by consulting NOT gate IC's data
sheet in figure 2.2.
5. Use any of the logic switches from S2 to S9 for input A.
6. For output Y use any of the LED's from (LO- L15).

9|Page
Course Title: Lab-2
Digital Logic & Design Basic Logic Gates
7. Supply the VCC= +5V and GND to the pins 14 and 7 of the IC.
8. Test all the possible combinations of inputs and verify the output according to the truth table
of NOT gate.
9. Fill the truth table 1 according to the results.

Truth Table for NOT Gate

Inputs Outputs

A NOT

In Case of Trouble:

1. Check the power supply.

2. Check the VCC and GND at pins 14 and 7 of the IC.
3. Check all the wire connections.
4. Check the circuit wiring and remove the breaks.
5. Check the IC using truth table.

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Course Title: Lab-2
Digital Logic & Design Basic Logic Gates

Objective B: To check the operation of NAND gate according to the NAND's

truth table, using the IC 74LSOO.

Components:
1. 74LSOO X 1

Tools:
1. AM-2000 Trainer.
2. Multimeter.
3. Cutter.
4. Single Core Wire.
5. Tweezer.
6. Pair of Pliers.

Diagram:

Procedure:
1. Connect the AM*2000 trainer to the 220V AC power supply.
Figure 5.1
2. Turn on the trainer and verify the voltage of the power supply using the multimeter.
It should be +SV exactly.
3. Install the IC 74LSOO on trainer's breadboard.
4. Wire the circuit according to the diagram in figure 2.3 by consulting NAND gate IC's
datasheet in figure 2.4.
5. Use any of the two logic switches from S2 to S9 for inputs to NAND gate.
6. For output indication use any of the LED's from (LO- LIS).
7. Supply tl1e VCC= +5V and GND to the pins 14 and 7 of the JC.
8. Test all the possible combinations of inputs and verify the output according to the truth table
of NAND gate.
9. Fill the truth table given below according to the results.

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Course Title: Lab-2
Digital Logic & Design Basic Logic Gates

Table # 1 Truth Table for NAND Gate

Inputs Outputs

A B NAND

0 0

0 1

1 0

1 1

In Case of Trouble:

1. Check the power supply.

2. Check the VCC and GND at pins 14 and 7 of the IC.
3. Check all the wire connections.
4. Check the circuit wiring and remove the breaks.
5. Check the JC using truth table.

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Course Title: Lab-2
Digital Logic & Design Basic Logic Gates

Objective C: To check the operation of NOR gate according to the NOR's

truth table, using the IC 74LS02.

Components:
1. 74LS02 X 1

Tools:
1. AM-2000 Trainer.
2. Multimeter.
3. Cutter.
4. Single Core Wire.
5. Tweezer.
6. Pair of Pliers.

Diagram:

Procedure:

1. Connect the AM-2000 trainer to the 220 V AC power supply.

2. Turn on the trainer and verify the voltage of the power supply using the multimeter.
It should be +5V exactly.
3. Install the IC 74LS02 on the trainer's breadboard.
4. Wire the circuit according to the diagram in figure 2.5 by consulting NOR gate ICs data sheet
in figure 2.6.
5. Use any of the two logic switches from S2 to S9 for inputs to NOR gate.
6. For output indication use any of the LED's from (LO- L15).
7. Supply the VCC= +5V and GND to the pins 14 and 7 of the IC.
8. Test all the possible combinations of inputs and verify the output according to the truth table
of NOR gate.
9. Fill the truth table given below according to the result.

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Course Title: Lab-2
Digital Logic & Design Basic Logic Gates
Truth Table for NOR Gate

Inputs Outputs

A B NOR

0 0

0 1

1 0

1 1

In Case of Trouble:

1. Check the power supply.

2. Check the VCC and GND at pins 14 and 7 of the IC.
3. Check all the wire connections
4. Check the circuit wiring and remove the breaks.
5. Check tr1e IC using truth table.

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Course Title: Lab-3
Digital Logic & Design Basic Logic gates & NAND Gate Application

LAB 3
Basic Logic Gates& NAND Gate Application
Objective A: To check the operation of XOR gate according to the XOR s
truth table, using the IC 74LS86.

Components:
1. 74LS86 X 1

Tools:
1. AM-2000 Trainer.
2. Multimeter.
3. Cutter.
4. Single Core Wire.
5. Tweezer.
6. Pair of Pliers.

Diagram:

Procedure:
1. Connect the AM-2000 trainer to the 220V AC power supply.
2. Turn on the trainer and verify the voltage of the power supply using the multimeter.
It should be +5V exactly.
3. Install the IC 74LS86 on trainer's breadboard.
4. Wire the circuit according to the diagram in figure 3.1 by consulting XOR gate IC's
Data sheet in figure 3.2
5. Use any of the two logic switch from S2 to S9 for inputs to XOR gate.
6. For output indication use any of the LED's from (L0 – L15).
7. Supply the VCC= +5V and GND to the pins 14 and 7 of the IC.
8. Test all the possible combinations of inputs and verify the output according to the Truth table
of XOR gate.
9. Fill the truth table given below according to the results.

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Course Title: Lab-3
Digital Logic & Design Basic Logic gates & NAND Gate Application

Truth Table for XOR Gate

Inputs Outputs

A B XOR

0 0

0 1

1 0

1 1

In Case of Trouble:

1. Check the power supply.

2. Check the VCC and GND at pins 14 and 7 of the fC.
3. Check all the wire connections.
4. Check the circuit wiring and remove the breaks.
5. Check the IC using truth table.

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Course Title: Lab-3
Digital Logic & Design Basic Logic gates & NAND Gate Application

Objective B: To check the operation of XOR gate according to the NAND's

truth table using the IC 74LSOO.

Components:
1 .74LSOO X 1

Tools:
1. AM-2000 Trainer.
2. Multimeter.
3. Cutter.
4. Single Core Wire.
5. Tweezer.
6. Pair of Pliers.

Diagram:

Procedure:
1. Connect the AM-2000 trainer to the 220V AC power supply.
2. Turn on the trainer and verify the voltage of the power supply using the multimeter.
It should be +5V exactly.
3. Install the lC 74LSOO on the trainer's breadboard.
4. Wire the circuit according to the diagram in figure 3.4.
5. Use any of the two logic switches from S2 to S9 for inputs A and B respectively.
6. For output indication use any of the LED's from (L0 - L 15).
7. Supply the VCC= +5V and GND to the pins 14 and 7 of the IC.
8. Text all the possible combinations of inputs and verify the output according to the truth table
of XOR gate.
9. Fill the truth table given below according to the results.

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Course Title: Lab-3
Digital Logic & Design Basic Logic gates & NAND Gate Application
Truth Table for XOR Gate

Inputs Outputs

A B XOR

0 0

0 1

1 0

1 1

sIn Case of Trouble:

1. Check the power supply.

2. Check the VCC and GND at pins 14 and 7 ofthe IC.
3. Check all the wire connections.
4. Check the circuit wiring and remove the breaks.
5. Check the IC using truth table.

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Course Title: Lab-4
Digital Logic & Design Designing Digital Adder & Subtractor circuit

LAB 4
Designing Digital Adder And Subtractor Circuits

Objective A: To design half adder circuit using XOR and AND gates.

Components:
1. 74LX86 X 1
2. 74LX08 X 1

Tools:
1. AM-2000 Trainer.
2. Multimeter.
3. Cutter.
4. Single Core Wire.
5. Tweezer.
6. Pair of Pliers.

Symbolic Diagram:

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Course Title: Lab-4
Digital Logic & Design Designing of Digital Adder & Subtractor Circuits
Circuit Diagram:

Procedure:
1. Connect the AM-2000 trainer to the 220V AC power supply.
2. Turn on the trainer and verify the voltage of the power supply using the multimeter.
It should be +5V exactly.
3. Install the IC 74LSOS & IC 74LS86 on trainer's breadboard.
4. Wire the circuit according to the diagram shown in Figure 4.2.
5. Use any of the two logic switches from S2 to S9 for inputs A and B.
6. For output sum, use LED L0and for output Carry, use LED L1.
7. Supply the VCC= +5V and GND to the pins 14 and 7 of both the IC.
8. Test all the possible combination of inputs and verify the outputs according to the Truth table
of half adder.
9. Fill the truth table given below according to the results.
I0. This experiment can also be implemented using NAND gates only by replacing XOR
Gate by its NAND gates equivalent circuit.

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Course Title: Lab-4
Digital Logic & Design Designing Digital Adder & Subtractor circuit

Truth Table for Half Adder

Inputs Outputs

A B Sum Carry out

0 0

0 1

1 0

1 1

Results:

Logic function Sum = A+ B

Co = A . B

In Case of Trouble:

1. Check the power supply.

2. Check the VCC and GND at pin 14 and 7 of the ICs.
3. Check all the wire connections.
4. Check the circuit wiring and remove the breaks.
5. Check the IC's using their respective data sheets.

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Course Title: Lab-4
Digital Logic & Design Designing Digital Adder & Subtractor circuit

Objective B: To design full adder circuit using XOR, AND & OR gates.

Components:
1. 74LS86x 1
2. 74LS08 X 1
3 74LS32 X 1

Tools:
1. AM-2000 Trainer.
2. 2: Multi meter.
3. Cutter.
4. Single Core Wire.
5. Tweezers.
6. Pair of Pliers.

Symbolic Diagram:

Procedure:

1. Connect tl1e AM-2000 trainer to the 220V AC power supply.

2. Turn on the trainer and verify the voltage of the power supply using the multimeter. It should
be +5V exactly.
3. Install the ICs on the breadboard.
4. Wire the circuit according to the diagram shown in figure 4.4.
5. Use logic switches S2, S3 and S4 for inputs A, B and Cin respectively.
6. For output sum, use LED LO and for output carry, use LED L 1.
7. Supply the VCC= +5V and GND to the pins 14 and 7 of the ICs.
8. Test all the possible combinations of inputs and verify the output according to the truth table
of adder.
9. Fill the truth table given below according to the results.
10. You can also implement this experiment using NAND gates only by replacing XOR
By its NAND gates equivalent circuit.

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Course Title: Lab-4
Digital Logic & Design Designing of Digital Adder & Subtractor Circuits

Circuit Diagram:

Truth Table for Full Adder

Inputs Outputs

A B Cin Sum Cout

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Results:
Logic function Sum = A⊕ B ⊕Cin
Cout = (A⊕B) Cin +(A.B)

24 | P a g e
Course Title: Lab-4
Digital Logic & Design Designing of Digital Adder & Subtractor Circuits
In Case of Trouble:

1. Check the power supply.

2. Check the VCC and GND at pins 14 and 7 of the lCs.
3. Check all the wire connections.
4. Check the circuit wiring and remove the breaks.
5. Check the lCs using their data sheets.

Objective C: To design half subtractor circuit using XOR, AND and NOT gates.

Components:
1. 74LS86 X 1
2. 74LS08 X 1
3. 74LS04x 1

Tools
1. AM-2000 Trainer.
2. Multimeter.
3. Cutter.
4. Single Core Wire.
5. Tweezer.
6. Pair of Pliers.

Symbolic Diagram:

Procedure:

1. Connect the AM-2000 trainer to the 220V AC power supply.

2. Turn on the trainer and verify the voltage of the power supply using the multimeter.
It should be +5 V exactly.
3. Install the IC's 74LS86, 74LS08 & 74LS04 on the trainer's breadboard.
4. Wire the circuit according to the diagram shown in figure 4.6.
5. Use logic switches S2 & S3 for inputs A & B respectively.
6. For output Di use LED L0 and for Output Bout use LED L1.
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Course Title: Lab-4
Digital Logic & Design Designing of Digital Adder & Subtractor Circuits
7. Supply the VCC= +5V and GND to the pins 14 and 7 of the ICs.
8. Test all the possible combinations of Inputs and verify the output according to the truth table
of full subtractor.
9. Fill the truth table given below according to the results.

Truth Table for Half Subtractor

Inputs Outputs

A B Diff Bo

0 0

0 1

1 0

1 1

Results:

Logic functions Sum = A + B

Co = A̅ . B

In Case of Trouble

1. Check the power supply.

2. Check the VCC and GND at pins 14 and 7 of the ICs.
3. Check all the wire connections.
4. Check the circuit wiring and remove the breaks.
5. Check the result using their data sheets.

Objective D: To design full subtractor circuit using XOR, AND, NOT & OR
gates.

Components
1. 74LS86 X 1
2. 74LS08 X 1
3. 74LS04 X 1
4. 74LS32 X 1

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Course Title: Lab-4
Digital Logic & Design Designing of Digital Adder & Subtractor Circuits
Tools
1 AM-2000 Trainer.
2. Multimeter.
3. Cutter.
4. Single Core Wire.
5. Tweezer.
6. Pair of Pliers.

Symbolic Diagram:

Circuit Diagram:

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Course Title: Lab-4
Digital Logic & Design Designing of Digital Adder & Subtractor Circuits
Procedure:

1. Connect the AM-2000 trainer to the 220V AC power supply.

2. Turn on the trainer and verify the voltage of the power supply using the multimeter.
It should be +5 V exactly.
3. Install the IC's 74LS86, 74LS32, 74LS08 & 74LS04 on the trainer's breadboard.
4. Wire the circuit according to the diagram shown in figure 12.2.
5. Use logic switches S2, S3 and S4 for inputs A, B, and Bin respectively.
6. For output Di use LED L0 and for Output Bout use LED L1.
7. Supply the VCC= +5V and GND to the pins 14 and 7 of the ICs.
8. Test all the possible combinations of Inputs and verify the output according to the truth table
of full subtractor.
9. Fill the truth table given below according to the results.
10. You can also implement this experiment using NAND gates only by replacing XOR by its
NAND gates equivalent circuit.

Truth Table for Full Subtractor

Inputs Outputs

A B Bin Diff Bout

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

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Course Title: Lab-4
Digital Logic & Design Designing Digital Adder & Subtractor circuit

Results:

Logic function Diff= A ⊕B ⊕Bin

Bout = ((A ⊕B)’ Bin) +(A’.B)

In Case of Trouble:

1. Check the power supply.

2. Check the VCC and GND at pins 14 and 7 ofthe ICs.
3. Check all the wire connections.
4. Check the circuit wiring and remove the breaks.
5. Check the ICs using their data sheets.

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Course Title: Lab-5
Digital Logic & Design 7-Segment Display Operation

LAB 5
7-Segment Display Operation
Objective A: To check the operation of common anode 7 -segment display.

Equipment:

Components
1. 7-segment display (common anode) x 1.
2. 180 ohms resistances x 8.

Tools
1. AM-2000 Trainer.
2. Multimeter.
3. Cutter.
4. Single Core Wire.
5. Tweezer.
6. Pair of Pliers.

Diagram:

Procedure:

1. Connect the AM-2000 trainer to the 220V AC power supply.

2. Turn on the trainer and verify the voltage of the power supply using the multimeter. It should
be +5V exactly.
3. Install the 7-segment display on trainer's breadboard.

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Course Title: Lab-5
Digital Logic & Design 7-Segment Display Operation
4. Wire the circuit according to the diagram shown above by consulting data sheet of
Common Anode display in figure 5.1.
5. Use logic switches S2 through S9 for inputs a through g and dp respectively.
6. Connect the common pin of7-segment display to +5V.
7. Test all the possible combinations of inputs as shown in table-1 and see the results.
8. Fill the truth table given below according to the results.

Truth Table for 7-segment display

S2 S3 S4 S5 S6 S7 S8 S9
a b c d e f g Dp Digit Displayed

Results
0-9 digits will be displayed with Dp ON.

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Course Title: Lab-5
Digital Logic & Design 7-Segment Display Operation

In Case of Trouble:
1. Check the power supply.
2. Check +5V to common pin of7-segment display.
3. Check all the wire connections.
4. Check the circuit wiring and remove the breaks.
5. Check the individual segments of 7-segrnent display by consulting its data sheet.

32 | P a g e
Course Title: Lab-5
Digital Logic & Design 7-Segment Display Operation

Objective B: To check the operation of common anode BCD to 7-Segment

decoder using IC 74LS47.

Components
1. 7-segmcnt display (common anode) x 1.
2. 180 ohms resistances x 8.
3. IC 74LS47.

Tools
1. AM-2000 Trainer
2. Multimeter.
3. Cutter.
4. Single Core Wire.
5. Tweezer.
6. Pair of Pliers.

Diagram

33 | P a g e
Course Title: Lab-5
Digital Logic & Design 7-Segment Display Operation
Procedure:

1. Connect the AM-2000 trainer to the 220V AC power supply.

2. Turn on the trainer and verify the voltage of the power supply using the Multimeter.
It should be +5V exactly.
3. Install the 7-segment display and IC 74LS47 on trainer's breadboard.
4. Wire the circuit according to the figure 5.2 as shown above.
5. Use logic switches S2 through S5 for BCD inputs (1, 2, 4 and 8) to decoder.
6. Supply the VCC = +5V and GND to the pins 16 and 8 of the lC.
7. Connect the common pin of7-segment display to +5V.
8. Enter BCD numbers from 0-9 using logic switches and see the result on to the display.
9. Fill the table given below according to the results.
10. The circuit in figure 5.2 is also provided in AM-2000 Trainer. The BCD input is available on
SBB-63 and as 8421.

Truth Table for BCD to 7-segment decoder

S5 S4 S3 S2 Display
B8 B4 B2 B1 Decimal digit

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

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Course Title: Lab-5
Digital Logic & Design 7-Segment Display Operation

Results:

0-9 digits will be displayed in sequence.

In Case of Trouble:

1. Check the power supply.

2. Check +5V to common pin of 7-segmentdisplay.
3. Check all the wire connections.
4. Check the circuit wiring and remove the breaks.
5. Check the individual segments of7-segment display by consulting its data sheet.

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Course Title: Lab-6
Digital Logic & Design Designing of combinational circuits

LAB 6
Designing Of Combinational Circuits
Objective A: To generate the table of 2 by applying all design steps,
equation should be in POS form and implement the circuit using logic
gates ICs.

Components:
1. 74LS32
2. 74LS08& 74LS11

Tools
1. AM-2000 Trainer.
2. Multimeter.
3. Cutter.
4. Single Core Wire.
5. Tweezer.
6. Pair of Pliers.

Procedure:
The design procedure for combinational logic circuits starts with the problem specification and
comprises the following steps:

1. Determine required number of inputs and outputs from the specifications.

2. Derive the truth table for each of the outputs based on their relationships to the input.
3. Simplify the boolean expression for each output. Use Karnaugh Maps or Boolean
algebra.
4. Draw a logic diagram that represents the simplified Boolean expression. Verify the
design by analyzing or simulating the circuit.

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Course Title: Lab-6
Digital Logic & Design Designing of combinational circuits
Truth Table:
A B C D V W X Y Z
0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1 0
0 0 1 0 0 0 1 0 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0

K-Map:

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Course Title: Lab-6
Digital Logic & Design Designing of combinational circuits

Equations:

Logic Diagram:

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Course Title: Lab-7
Digital Logic & Design Designing comparators and decoder circuits

Lab 7
Designing comparator and decoder circuits
Objective A: To check the operation of 4-bit Magnitude Comparator using
the IC 74LS85.

Comparators:
A comparator is a logic circuit used to compare the magnitude of two binary numbers. It may
simply provide an output that is active (goes High) when the two numbers are equal, or it may
additionally provide outputs that signify which of the number is larger when equality does not
hold. 75LS85 is a 4-bit magnitude comparator. Figure 18.1 shows this IC which accepts two four-
bit words at its inputs and produces one of three outputs, A>B, A=B, and A<B. Depending upon
the status of the four-bit words at the inputs, the appropriate one of these outputs will be high
and the other two will be low. A0A1A2A3 and B0B1B2B3 are two 4-bit numbers. Note from the
Figure l8.2 a that pins 4,5 and 6 are designated (A>B)in, (A<B)in and (A=B)in are used for
cascading.

Component:
1. 74LS85 X 1

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Course Title: Lab-7
Digital Logic & Design Designing comparators and decoder circuits

Procedure:
1. Connect the AM-2000 trainer to the 220V AC power supply.
2. Turn on the trainer and verify voltage of the power supply using the multimeter.
It should be +5V exactly.
3. Install the IC 74LS85 on trainer's breadboard.
4. Wire the circuit by consulting the diagram in Figure 7.1.
5. Supply the VCC = +5V and GND to the pins 16 and 8 of the lC.
6. For binary input A (A0A1A2A3) use logic switches S5, S4, S3, S2 and for B (B0B1B2B3)
use switches S9, S8, S7, S6 respectively.
7. Use LED's LO, L1 and L2 for outputs (A<B)out (A=B)out and (A>B) out respectively.
8. For different settings of A and B, observe the outputs.
9. Fill in the table 1 according to the results.

Diagram:

(Figure #7.2)

A 4-bit magnitude comparator used to determine which of inputs A= A0A1A2A3 and B= B0B1B2B3
is larger or if they are equal.

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Course Title: Lab-7
Digital Logic & Design Designing comparators and decoder circuits

Figure 7.3
The 7485 4-bit comparator

4-bit magnitude comparator

Inputs Outputs

A0A1A2A3 B0B1B2B3 (A<B) (A=B) (A>B)

0010 0000

0100 1000

1100 1100

1100 0011

1000 1001

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Course Title: Lab-7
Digital Logic & Design Designing comparators and decoder circuits
In Case of Trouble:

1. Check the power supply.

2. Check the VCC and GND at pins 16 and 8 of the IC.
3. Check all the wire connections.
4. Check the circuit wiring and remove the breaks.
5. Check the IC using its truth table.

Objective B: To check the operation of 2 to 4 line decoder, using the IC

74LS139.

Component:
1. 74LS 139 X 1

Tools:
1. AM-2000 Trainer.
2. Multimeter.
3. Cutter.
4. Single Core Wire.
5. Tweezer.
6. Pair of Pliers.

Diagram:

42 | P a g e
Course Title: Lab-7
Digital Logic & Design Designing comparators and decoder circuits

Procedure:

1. Connect the AM-2000 trainer to the 220V AC power supply.

2. Turn on the trainer and verify the voltage of the power supply using the Multimeter.
It should be +5V exactly.
3. Install the IC 74LS 139 on trainer's breadboard.
4. IC 74LS139 is a dual 2 to 4 line decoders / demultiplexers. Wire one of such decoder
according to the diagram in fig. 14.1 by consulting data sheet of the IC.
5. Use logic switches S2 & S3 for decoder inputs 1 A and 1 B respectively.
6. Connect outputs lY0, IYI, IY2 m1d lY3 to LED's LO, L1, L2 and L3 respectively.
7. Supply the VCC= +SV and GND to the pins 16 and 8 of the I C.
8. Test all the possible combination of inputs and verity the output according to the truth table
of 74LS139.
9. Fill in the table given below according to the results.

Truth Table for 2 to 4 lines Decoder

Inputs
Outputs
Enable Select

1G 1B 1A 1Y0 1Y1 1Y2 1Y3

1 X X

0 0 0

0 0 1

0 1 0

0 1 1

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Course Title: Lab-7
Digital Logic & Design Designing comparators and decoder circuits

In Case of Trouble

1. Check the power supply.

2. Check the VCC and GND at pins 16 and 8 of the IC.
3. Check all the wire connections.
4. Check the circuit wiring and remove the breaks.
5. Check the IC using its truth table.

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Course Title: Lab-7
Digital Logic & Design Designing comparators and decoder circuits

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Course Title: Lab-8
Digital Logic & Design Designing multiplexer and demultiplexer circuits

Lab 8
Designing multiplexer & demultiplexer circuits

Objective A: To check the operation of 1 of 2 data selector / multiplexer

using the IC 74LS157.

Components:
1. 74LSI57x1

Tools:
1. AM-2000
2. Multimeter
3. Cutter.
4. Single Core Wire.
5. Tweezer.
6. Pair of Pliers.

Diagram:

46 | P a g e
Course Title: Lab-8
Digital Logic & Design Designing multiplexer and demultiplexer circuits
Procedure:

1. Connect the AM-2000 trainer to the 220V AC power supply.

2. Turn on the trainer and verify the voltage of the power supply using the Multimeter.
It should be +5V exactly.
3. Install the IC 74LS157 on trainer's breadboard.
4. IC 74LS157 is a quadruple 1 of2 data selectors I multiplexers. Use one out of4 such MUX and
wire the circuit according to the diagram.
5. Use logic switch S3 for 1A and switch S2 for 1B respectively.
6. Connect output 1Y to LED L0.
7. Supply the VCC = +5V and GND to the pins 16 and 8 of the IC.
8. Test all the possible combinations of inputs and verify the output according to the
truth table of74LSI57.
9. Fill in the table given below according to the results.
10. You will see that when select input is 0, then input A will be selected if select
input is 1 then input B will be selected as output

Truth Table for 1 of 2 data multiplexer

Inputs
Output
Strobe Select Data

G̅ A̅ / B 1A 1B 1Y

1 X X X

0 0 0 X

0 0 0 X

0 1 X 0

0 1 X 1

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Course Title: Lab-8
Digital Logic & Design Designing multiplexer and demultiplexer circuits

Diagram:

In Case of Trouble:

1. Check the power supply.

2. Check the VCC and GND at pins 16 and 8 of the IC.
3. Check all the wire connections.
4. Check the circuit wiring and remove the breaks.
5. Check the IC using its truth table.

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Course Title: Lab-8
Digital Logic & Design Designing multiplexer and demultiplexer circuits

Objective B: To employ a 74LS151 as a multiplexer and a 74LSI38 as a

demulitplexer in a single-line digital communications circuit.

Theory of Operation:

As shown in figure 17.1, the 74LS151 functions as a 1-of-8 multiplexer. The 3-bit select code will
command which of the data inputs will be selected to theY output. This same 3-bit code will be
applied to the select inputs of the 74LS138 demultiplexer. Instead of running eight separate
data lines, this circuit employs one multiplexed data line and three lines of select code. This
saves a total of four lines.
The select code of the desired data line (0 through 7) is applied to select inputs of both ICs as
shown in figure 17-1. If the selected data is low, the Y output of 74LS151 will go low. This low is
applied to the G2A enable input of 74LS138 which will enable the IC and the output that
corresponds to the select code will go low and match the original data from 74LS151. If the
selected data is high, the Y output of multiplexer will go high. When this high is applied to the
active-low enable input of 7 4LS138 IC will become disabled. All outputs of demultiplexers will
go high. The selected output will be high, matching the original data sent from 74LS151.

Components
1. 74LS151 X 1
2. 74LS138 X 1

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Course Title: Lab-8
Digital Logic & Design Designing multiplexer and demultiplexer circuits
Procedure:

1. Connect the AM-2000 trainer to the 220V AC power supply.

2. Turn on the trainer and verify the voltage of power supply using multimeter, It should be +5V
exactly.
3. Install the ICs 74LS151 and 74LS138 on trainer's bread board.
4. Wire the circuit according to the diagram in figure 8.3 by consulting data sheets in figure 8.4.
5. Maximum 8 switches are available on the trainer so for inputs D0 through D4 use logic
switches S2 through S6 and for select lines A, Band C use switches S7, S8 and S9 respectively.
6. Connect outputs Y0 through Y4 of 74LS 138 to LED·s L0 through L4 respectively.
7. Supply the VCC=+5V and GND to the pins 16 &8 of the IC respectively.
8. Apply the select code of the desired data line (0 through 4).
9. Observe the corresponding output match the original data.
10. Test all the select inputs (0 through 4) and verify the output matches the
Corresponding input.
11. Fill in the table according to the results.

Truth Table for Multiplexer & demultiplexer

Input data Channel Select Outputs

D0 D1 D2 D3 D4 C B A Y0 Y1 Y2 Y3 Y4

0 1 1 1 1 0 0 0

1 0 1 1 1 0 0 1

1 1 0 1 1 0 1 0

1 1 1 0 1 0 1 1

1 1 1 1 0 1 0 0

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Course Title: Lab-8
Digital Logic & Design Designing multiplexer and demultiplexer circuits

IC Data sheets:

51 | P a g e
 Course Title: Lab-9
Digital Logic & Design To Design multivibrator circuits

Lab 9
To Design Multivibrator Circuits

Objectives: To design and study the following circuits using IC 555.

1. An astable multivibrator
2. A monostable multivibrator
3. A bistable multivibrator

Multivibrators:

Individual Sequential Logic circuits can be used to build more complex circuits such as
Counters, Shift Registers, Latches or Memories etc, but for these types of circuits to
operate in a "Sequential" way, they require the addition of a clock pulse or timing signal
to cause them to change their state. Clock pulses are generally square shaped waves that
are produced by a single pulse generator circuit such as a Multivibrator which oscillates
between a "HIGH" and a "LOW" state and generally has an even 50% duty cycle, that is
it has a 50% "ON" time and a 50% "OFF" time. Sequential logic circuits that use the clock
signal for synchronization may also change their state on either the rising or falling edge,
or both of the actual clock signal. There are basically three types of pulse generation
circuits depending on the number of stablestates,

 Astable - has NO stable states but switches continuously between two states this action
produces a train of square wave pulses at a fixedfrequency.
 Monostable - has only ONE stable state and if triggered externally, it returns back to its
first stablestate.
 Bistable - has TWO stable states that produces a single pulse either positive or negative
invalue.

IC 555 TIMER:

The 555 timer IC was first introduced around 1971 by the signetics Corporation as the
SE555/NE555 and was called "The IC Time Machine" and was also the very first and only
commercial timer IC available. It provided circuit designers with a relatively cheap,
stable, and user-friendly integrated circuit for timer and multivibrator applications.

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Course Title: Lab-9
Digital Logic & Design To Design multivibrator circuits

These ICs come in two packages, either the round metal-can called the 'T' package or the
more familiar 8-pin DIP 'V' package as shown in figure below. The IC comprises of 23
transistors, 2 diodes and 16 resistors with built-in compensation for component
tolerance and temperature drift.

IC 555 in 8-pin DIP package

Functional block diagram of IC 555

The pin connections are as follows:

1. Ground.
2. Triggerinput.
3. Output.
4. Reset input.
5. Controlvoltage.
6. Thresholdinput.
7. Discharge.
8. 8. +VCC. +5 to +15 volts in normal use.

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Course Title: Lab-9
Digital Logic & Design To Design multivibrator circuits

Pin1: Ground. All voltages are measured with respect to this terminal.

Pin2: Trigger. The output of the timer depends on the amplitude of the external trigger
pulse applied to this pin. When a negative going pulse of amplitude greater than 1/3 VCCis
applied to this pin, the output of the timer high. The output remains high as long as the
trigger terminal is held at a lowvoltage.

Pin3: Output. The output of the timer is measured here with respect to ground. There are
two ways by which a load can be connected to the output terminal: either between pin 3
and ground or between pin3 and supply voltage +VCC. When the output is low the load
current flows through the load connected between pin3 and +VCCinto the output
terminal and is called sink current. The current through the grounded load is zero when
the output is low. For this reason the load connected between pin 3 and +VCCis called the
normally on load (we will use this for our circuit) and that connected between pin 3 and
ground is called normally off-load. On the other hand, when the output is high the
current through
theloadconnectedbetweenpin3and+VCCiszero.Theoutputterminalsuppliescurrentto the
normally off load. This current is called source current. The maximum value of sink or
source current is200mA.

Pin4: Reset. The 555 timer can be reset (disabled) by applying a negative pulse to this pin.
When the reset function is not in use, the reset terminal should be connected to +VCCto
avoid any possibility of falsetriggering.

Pin5: Control Voltage. An external voltage applied to this terminal changes the threshold
as well as trigger voltage. Thus by imposing a voltage on this pin or by connecting a pot
between this pin and ground, the pulse width of the output waveform can be varied.
When not used, the control pin should be bypassed to ground with a 0.01µ F Capacitor to
prevent any noiseproblems.

Pin6: Threshold. When the voltage at this pin is greater than or equal to the threshold
voltage 2/3 VCC, the output of the timer low.

Pin7: Discharge. This pin is connected internally to the collector of transistor Q. When
the output is high Q is OFF and acts as an open circuit to external capacitor C connected
across it. On the other hand, when the output is low, Q is saturated and acts as a short
circuit, shorting out the external capacitor C toground.

Pin8: +VCC. The supply voltage of +5V to + 18V is applied to this pin with respect to
ground.

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Course Title: Lab-9
Digital Logic & Design To Design multivibrator circuits
OPERATION:

The functional block diagram shows that the device consists of two comparators, three
resistors and a flip-flop. A comparator is an OPAMP that compares an input voltage and
indicates whether an input is higher or lower than a reference voltage by swinging into
saturation in both the direction. The operation of the 555 timer revolves around the three
resistors that form a voltage divider across the power supply to develop the reference voltage,
and the two comparators connected to this voltage divider. The IC is quiescent so long as the
trigger input (pin 2) remains at +VCC and the threshold input (pin 6) is at ground. Assume the
reset input (pin 4) is also at +VCC and therefore inactive, and that the control voltage input (pin
5) is unconnected.

The three resistors in the voltage divider all have the same value (5K in the bipolar version of
this IC and hence the name 555), so the trigger and threshold comparator reference voltages
are 1/3 and 2/3 of the supply voltage, respectively. The control voltage input at pin 5 can
directly affect this relationship, although most of the time this pin is unused. The internal flip-
flop changes state when the trigger input at pin 2 is pulled down below +V CC/3. When this
occurs, the output (pin 3) changes state to +VCC and the discharge transistor (pin 7) is turned
off. The trigger input can now return to +VCC; it will not affect the state of theIC.
However, if the threshold input (pin 6) is now raised above +(2/3)V CC, the output will return to
ground and the discharge transistor will be turned on again. When the threshold input returns
to ground, the IC will remain in this state, which was the original state when we started this
analysis. The easiest way to allow the threshold voltage (pin 6) to gradually rise to +(2/3)VCC is
to connect it externally to a capacitor being allowed to charge through a resistor. In this way we
can adjust the R and C values for almost any time interval we mightwant.

IC 555 timer as Multivibrator:

The 555 can operate in either mono/bi-stable or astable mode, depending on the connections
to and the arrangement of the external components. Thus, it can either produce a single pulse
when triggered, or it can produce a continuous pulse train as long as it remainspowered.

Astable multivibrator having 50% Duty cycle:

These circuits are not stable in any state and switch outputs after predetermined time
periods. The result of this is that the output is a continuous square/rectangular wave
with the properties depending on values of external resistors and capacitors. Thus, while
designing these circuits following parameters need to be determined:

1. Frequency (or the time period) of the wave.

2. The duty cycle of the wave

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Course Title: Lab-9
Digital Logic & Design To Design multivibrator circuits

Figure 9.1: A rectangular waveform

Referring to the above figure of a rectangular waveform, the time period of the pulse is
defined as T and duration of the pulse (ON time) is τ. Duty cycle can be defined as the
On time/Period that is, τ/T in the above figure. Obviously, a duty cycle of 50% will yield
a square wave.
The key external component of the astable timer is the capacitor. An astable
multivibrator can be designed as shown in the circuit diagram (with typical component
values) using IC 555, for a duty cycle of more than 50%. The corresponding voltage across
the capacitor and voltage at output is also shown. The astable function is achieved by
charging/discharging a capacitor through resistors connected, respectively, either to VCC
or GND. Switching between the charging and discharging modes is handled by resistor
divider R1-R3, two Comparators, and an RS Flip-Flop in IC 555. The upper or lower
comparator simply generates a positive pulse if VC goes above 2/3 VCC or below 1/3 VCC.
And these positive pulses either SET or RESET the Q output.

The time for charging C from 1/3 to 2/3 Vcc, i.e., ON Time = 0.693 (RA + RB). C
The time for discharging C from 2/3 to 1/3 Vcc, i.e. OFF Time = 0.693 RB. C

To get the total oscillation period, just add the two:

Thus,

Tosc = 0.693∙ (RA+RB) ∙C + 0.693∙ (RB) ∙C = 0.693 ∙ (RA + 2∙RB) ∙ C

Fosc = 1/ Tosc = 1.44/ (RA + 2∙RB).C Duty cycle = RA+RB/ RA + 2∙RB

56 | P a g e
Course Title: Lab-9
Digital Logic & Design To Design multivibrator circuits
Circuit Diagram:

Monostable multivibrator:

Monostable multivibrator often called a one shot multivibrator is a pulse generating circuit in
which the duration of this pulse is determined by the RC network connected externally to the
555 timer. In a stable or standby state, the output of the circuit is approximately zero or a logic-
low level. When external trigger pulse is applied (See circuit diagram) output is forced to go
high (VCC). The time for which output remains high is determined by the external RC network
connected to the timer. At the end of the timing interval, the output automatically reverts back
to its logic-low stable state. The output stays low until trigger pulse is again applied. Then the
cycle repeats. The monostable circuit has only one stable state (output low) hence the
namemonostable.
Initially when the circuit is in the stable state i.e, when the output is low, transistor Q in IC 555
is ON and the capacitor C is shorted out to ground. Upon the application of a negative trigger

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Course Title: Lab-9
Digital Logic & Design To Design multivibrator circuits
pulse to pin 2, transistor Q is turned OFF, which releases the short circuit across the external
capacitor C and drives the output high.

The capacitor C now starts charging up towards VCC through R. When the voltage across the
capacitor equals 2/3 VCC, the upper comparator’s (see schematics of IC 555) output switches
from low to high, which in turn drives the output to its low state via the output of the flip-flop.
At the same time the output of the flip-flop turns transistor Q ON and hence the capacitor C
rapidly discharges through the transistor. The output of the monostable remains low until a
trigger pulse is again applied. Then the cycle repeats. The pulse width of the trigger input must
be smaller than the expected pulse width of the output waveform. Also the trigger pulse must
be a negative going input signal with amplitude larger than 1/3 VCC (Why?). The pulse width can
be calculated as (How?):
T= 1.1R.C.

Once triggered, the circuit’s output will remain in the high state until the set time, T, elapses.
The output will not change its state even if an input trigger is applied again during this time
interval. The circuit can be reset during the timing cycle by applying negative pulse to the reset
terminal. The output will remain in the low state until a trigger is again applied. The circuit is
designed as shown in the circuit diagram, the left part of which shows how to generate
negative a trigger pulse from a square wave signal.

Circuit Diagram:

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Course Title: Lab-9
Digital Logic & Design To Design multivibrator circuits

Bistable Multivibrator:

In these circuits, the output is stable in both the states. The states are switched using an
external trigger but unlike the monostable multivibrator, it does not return back to its
original state. Another trigger is needed for this to happen. This operation is similar to a
flip-flop. There are no RC timing network and hence no design parameters. The following
circuit can be used to design a bistable multivibrator. The trigger and reset inputs (pins 2
and 4 respectively on a 555) are held high via pull-up resistors while the threshold input
(pin 6) is simply grounded. Thus configured, pulling the trigger momentarily to ground
acts as a 'set' and transitions the output pin (pin 3) to Vcc (high state). Pulling the
threshold input to supply acts as a ‘reset’ and transitions the output pin to ground (low
state). No capacitors are required in a bistable configuration.

Circuit Diagram:

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Course Title: Lab-9
Digital Logic & Design To Design multivibrator circuits
Circuit components/Equipment:

1. IC 555 (1 No.)
2. Resistors (1KΩ, 2 Nos; 10KΩ, 2 Nos; 2.7KΩ, 1No)
3. Potentiometer (10 KΩ, 1No)
4. Capacitors (0.01 μF, 0.047 μF, 0.1 μF, 1 μF; 1 No.each)
5. Diodes 1N 4148 (2Nos.)
6. D.C. Power supply(10V)
7. Function Generators
8. Oscilloscope
9. Connectingwires
10. Breadboard

Circuit Diagrams: Already provided with text.

Procedure:

 AstableMultivibrator:

(a) For duty cycle more than50%:

o Configure the circuit as per the circuit diagram.

o Use RA = RB = 10 kΩ, RL = 1 kΩ and CT = 0.1 μF, C = 0.01 μF. Using the
power supply set VCC = 10 V.
o Compute the expected values of fosc and duty cycle(%).
o Connect the output terminal (pin 3) to channel 1 of the oscilloscope. Also feed
the voltage across capacitor to channel2.
o Power on your circuit and observe and save the output. Determine the values
of fosc and duty cycle (%) from your observations and compare with the
theoretical values.
o When you are done, turn off the power to your experimental circuit.

(a) For duty cycle less than50%:

o Configure the circuit as per the circuit diagram.

o Use RA = 2.7 kΩ, RB = 10 kΩ, RL = 1 kΩ and CT = 0.1 μF, C = 0.01 μF. Using the
power supply set VCC = 10V.
o Repeat steps 3 to 6 of procedure (a).

(b) For duty cycle variable from 0 to100%:

o Configure the circuit as per the circuit diagram.

o Use R1 = 1 kΩ, R2 = 2.7 kΩ, RX = 10 kΩ, RL = 1 kΩ and CT = 0.047 μF,C=0.01 μF.
o Using the power supply set VCC = 10 V.

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Course Title: Lab-9
Digital Logic & Design To Design multivibrator circuits
o Calculate RA and RB for different settings of the potentiometer using RA = R1+R2, RB = RX-
R2+R3 and repeat steps 3 to 6 of procedure (a) for eachsetting.

 Monostable Multivibrator:

o Configure the circuit as per the circuit diagram.

o Use R1 = 1 kΩ, RA = 2.7 kΩ, RL = 1 kΩ and CT = 1 μF, CD = 0.047 μF, C=0.01 μF.
o Using the power supply set VCC = 10 V.
o Compute the expected value of pulse duration.
o Apply a square wave input of frequency 1 kHz at terminal N of the circuit diagram.
o Connect the output terminal (pin 3) to the oscilloscope. Also feed the voltage across
capacitor to channel2.
o Power on your circuit and observe the output. Determine the value of pulse duration
from your observations and compare with the theoretical values. Save the data.
o When you are done, turn off the power to your experimental circuit.

 Bistable Multivibrator:

o Configure the circuit as per the circuit diagram.

o Use RA = RB = 10 kΩ, RL = 1 kΩ and C1 = 1 μF, C2 = 0.01 μF. Using the power supply set VCC
= 10V.
o Connect the output terminal (pin 3) to the oscilloscope in DC COUPLING mode.
o Power on your circuit.
o Connect the point F to ground momentarily. This will set the output Q in the
oscilloscope to 1 or HIGH level. This state will be permanently stable state and the
operation is called “SET”.
o Now connect the point G to VCC momentarily. This will set the output Q in the
oscilloscope to 0 or LOW level. This is called “RESET” operation.
o When you are done, turn off the power to your experimental circuit.

Observations:

Astable Multivibrator:

 For duty cycle 50%:

RA =RB = kΩ, CT= μF

Output waveform and capacitor voltage as observed in oscilloscope: (paste data here)

Parameters Calculated value Observed value Error

fosc
Duty cycle (%)

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Course Title: Lab-9
Digital Logic & Design To Design multivibrator circuits

Monostable Multivibrator:
RA= kΩ, CT= μF

Output waveform and capacitor voltage as observed in oscilloscope: (paste data here)

Parameter Calculated Observed Error

value value
(ms) (ms)
Pulse duration

Bistable Multivibrator:

Point Connected to Output

F Ground

G VCC

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Course Title: Lab-10
Digital Logic & Design To Check Latch and Flip Flop operation

Lab 10
To check Latch and Flip Flop Operation
Objective A: The experiment is to use the D latch and flip flop according to
its truth table and to learn how it works by usi.ng IC 74LS75 Quad D Latch
and 74LS74 Dual D Edge Triggered Flip-Flops.

Components:
1. 74LS75 X 1
2. 74LS74 x. 1

Tools:
1. AM-2000
2. Multimeter.
3. Cutter.
4. Single Core Wire.
5. Tweezer.
6. Pair of Pliers.

D-LATCH
Diagram:

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Course Title: Lab-10
Digital Logic & Design To Check Latch and Flip Flop operation
Procedure:
1. Connect the AM-2000 trainer to the 220V AC power supply.
2. Turn on the trainer and verify the voltage of the power supply using the multimeter.
It should be +5V exactly.
3. Install the IC 74LS75 on trainer's breadboard.
4. Wire the circuit according to the diagram in Figure 10.1 by consulting IC's data sheet in figure
10.2
5. Supply the VCC=+5 and GND to the pins 5 and 12 of the IC.
6. Connect Enable 1-2 to switch S4.
7. Change the setting of switch S3 and make switch S4 (Enable) High.
8. Observe the output is latched. That is, the output retains the data that was present at the
input when the enable is made high.
9. Also observe that when Enable is high output is continually updated. The output follows any
change in input when Enable is high. Thus this larch has an enable that requires a High level.
10. Fill the truth table given below according to the results.
Truth Table for D- Latch
Enable Input Output

E1-2 D Q

0 0

0 1

1 0

1 1

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Course Title: Lab-10
Digital Logic & Design To Check Latch and Flip Flop operation

D-FLIP FLOP
Diagram:

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Course Title: Lab-10
Digital Logic & Design To Check Latch and Flip Flop operation
Procedure:
1. Install the IC 74LS74 on the trainer's breadboard.
2. Connect switches S2 and S3 to inputs J D and 2D respectively.
3. Connect LED's L0 and L1 to outputs IQ and 2Q respectively.
4. Connect S4 to CK1 and CK2 pins of the IC.
5. Recognize that S4 controls the clock for the flip-flops. We will determine what is required on
the clock to allow data to transfer. There are four possibilities:
• Low level
• High level
• Positive Edge (Low to high change)
• Negative edge (High to Low change)
6. Set switches S2 and S3 to High and S4 to low. Now move S4 to High and back
Low again. Both LED's L0 and L1 should read 1: do they? ------------
7. Set S2 to low. The L0 display should indicate 1. Does it? What is the L1 LED indicating? ---------
8. Now move S4 to high. Do the LO LED updated to new information? -------------
9. Move S2 to high and S3 to low position, Do the LED's L0 and L1 update to the new data? ------
10. Move S4 to low. Any change in the LED's? ----------------
11. Now move S4 to high. Any change now? ----------------
12. Therefore, what is required to the output? ----------------
(I) Low level
(2) High level
(3) Positive edge
(4) Negative edge
13. We should have seen that the D flip-flop would not transfer data if the clock is held Low or
held high.
14. That is, it does not have a level sensitive clock. The clock responds only to a positive
transition (change from low to High). The output follows the input when the transition occurs.

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Course Title: Lab-10
Digital Logic & Design To Check Latch and Flip Flop operation

In Case of Trouble:

1. Check the power supply.

2. Check the VCC and GND at pins 14 and 7 of the IC.
3. Check all the wire connections.
4. Check the circuit wiring and remove the breaks.
5. Check the lC using its truth table.

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Course Title: Lab-10
Digital Logic & Design To Check Latch and Flip Flop operation

Objective B: The experiment is to learn how a D latches can be used to

latch BCD data using IC 74LS75 Quad D Latch, IC 74LS47 7-Segment
Decoder/Driver and common anode 7-segment display.

Components:
1. 74LS75 X 1
2. 74LS47 X 1
3. Common anode display

Tools:
1. AM-2000 Trainer
2. Multimeter
3. Cutter
4. Single Core Wire
5. Tweezer
6. Pair of Pliers

Diagram:

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Course Title: Lab-10
Digital Logic & Design To Check Latch and Flip Flop operation
Procedure:

1. Connect the AM-2000 trainer to the 220V AC power supply.

2. Turn on the trainer and verify the voltage of the power supply using the multimeter.
It should be +5V exactly.
3. Install the IC 74LS75 on trainer's breadboard.
4. Supply the VCC = +5v and GND to the pins 5 to 12 of the IC.
5. Wire the circuit according to the diagram using lCs data sheet.
6. Use logic switches S2 through S5 for inputs l D through 4D.
7. Connect the enable signals coming out of each flip-flop (Enable 1-2 and Enable 3-4) to S6.
Connect the outputs 1Q through 4Q 7475 to BCD input 8421 of 7447 respected available on
SBB-63.
8. Input different BCD words using switches S2 through S5 and then set S6 to High.
9. Observe that the output is latched and corresponding digit is displayed on 7-segment display.
That is, the output retains the data that was present when the enable is high.
10. Also observe that when enable is High, the output follows any change in input.

In Case of Trouble:

1. Check the power supply

2. Check the VCC and GND at proper pins of the lCs.
3. Check all the wire connections.
4. Check the circuit wiring and remove the breaks.
5. Check the ICs using their truth table

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Course Title: Lab-11
Digital Logic & Design Recirculating Data and 2-bit Binary Counter

Lab 11
Recirculating Data and 2-bit Binary Counter
Objective A: This experiment is to examine the concept of shifting data
around in a circular shift register. By presetting the Flip-flop, any desired
output pattern can be generated.

Components:
1. 74LS74 X 2
Tools :
1. AM-2000 Trainer.
2. Multimeter.
3. Cutter.
4. Single Core Wire.
5. Tweezer.
6. Pair of Pliers

Diagram:

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Course Title: Lab-11
Digital Logic & Design Recirculating Data and 2-bit Binary Counter
Procedure:

1. Install the Two 74LS74 1Cs on the trainer's breadboard.

2. Wire the circuit according to the diagram in figure in 11.1.
3. Set S2 to Low. Set S4, S5, S6 and S7 to High.
4. Set S3 to Low and then back to high. 1l1is resets all flip-flops. All four LED's should be OFF.
5. Move S4 to Low and then back high. This has set (preset) the first flip-flop; its Q output
should be High and L1 should be lit.
6. Now cycle the data. Through the ring of flip-flops by supplying a clock signal. Move S2 to High
and then back Low again. Note that the High has moved to L2.
7. Again cycle S2 High and then Low. The data again should have shifted one position.
8. Continue to cycle S2, observing that four clock are needed to get the data completely around
the loop.
9. Set S2 Low. Set S3 to Low and then High.
10. Set S6 and S7 both Low and then High again. Observe that L3 and L4 are lit.
11. Cycle S2. Observe that the data recirculates.
12. This circuit is also called a "ring counter" or "Johnson counter" and often used to recirculate
one bit, which is used to turn ON one digit in a strobe display.
13. Use CLK Signal available on SBB 63 instate S2 and observe that how the data recirculate.
14. Do the same experiment using 7-Segment Decoder/Driver for output indication.

In Case of Trouble:

1. Check the power supply.

2. Check the VCC and GND at pins 14 and 7 of the IC.
3. Check all the wire connections.
4. Check the circuit wiring and remove the breaks.
5. Check the lC using truth table.

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Course Title: Lab-11
Digital Logic & Design Recirculating Data and 2-bit Binary Counter
Objective B: To design 2-bit binary synchronous counter using D-flipflop
IC.

Overview:
Synchronous counters are easier to design than asynchronous counters. They are called
synchronous counters because the clock input of the flip-flops. are all clocked together at the
same time with the same clock signal. Due to this common clock pulse all output states switch
or change simultaneously.

A 2-bit synchronous up counter is one which counts from 0 to 3, having 2 flipflops connected to
each other having same clock input.

Diagram:

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Course Title: Lab-11
Digital Logic & Design Recirculating Data and 2-bit Binary Counter

Procedure:
1. Install a 7474 IC on the trainers breadboard.
2. Wire the circuit according to the given diagram.
3. Make common connection of the clock of both flipflops and connects it to the pulse switches.
4. Connects Q0 and Q1 output to the L0 and L1.
5. Now press and release the pulse switch for clock pulse generation and observe the output .

Table:
Counts Clk Q1 Q0
0 0-1-0
1 0-1-0
2 0-1-1
3 0-1-2
0 0-1-3

In Case of Trouble:

1. Check the power supply.

2. Check the VCC and GND at pins 14 and 7 of the IC.
3. Check all the wire connections.
4. Check the circuit wiring and remove the breaks.
5. Check the lC using truth table.

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Course Title: Lab-13
Digital Logic & Design To check the read /write operation of RAM

Lab 12

To check J-K Flip Flop Operation and Design

Decade Counter
Objective A: The experiment is to use the J-K flip-flop according to its truth
table and to learn how it works by using lC 74LS76 Dual J-K Flip-Flops.

Components:
1. 74LS76 X 1

Tools:
1.AM-2000.
2.Multimeter.
3.Cutter.
4. Single Core Wire.
5. Tweezer.
6. Pair of Pliers.

Diagram:

Figure 12.1

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Course Title: Lab-12
Digital Logic & Design JK-Flipflop and Designing of Decade Counter
Procedure:

1. Connect the AM-2000 trainer to the 220V AC power supply.

2. Tum 011 the trainer and verify the voltage of the power supply using the multimeter.
It should be +5V exactly.
3. Install the IC 74LS76 on trainer's breadboard.
4. Wire the circuit according to the diagram using IC's data sheet.
5. Supply the VCC= +5V and GND to the pins 14 and 7 of the IC.
6. Set the switches as shown in table-1 and record the indications of L1 and L2.
7. Analyze your results to determine some conclusions about the JK.
8. When Clear and Preset is both High, does the output respond to the J, K and clock
Inputs?
9. When Clear is Low, does Q get held Low or High?
10. When preset is Low, does Q get held Low or High?
11. With Highs on Preset, Clear, J and K what happens to the output with each successive
Clock pulse?

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Course Title: Lab-12
Digital Logic & Design JK-Flipflop and Designing of Decade Counter

In Case of Trouble:

1. Check the power supply.

2. Check· the VCC and GND at pins 5 and 13 ofthe IC.
3. Check all the wire connections
4. Check the circuit wiring and remove the breaks.
5. Check the IC using its truth table.

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Course Title: Lab-12
Digital Logic & Design JK-Flipflop and Designing of Decade Counter
Objective B: To design a 4-bit synchronous decade counter using “JK-
flipflop” by applying all design steps. Equation should be in SOP form.

State Diagram:

Next State Table:

Present State Next State
Q3 Q2 Q1 Q0 Q3 Q2 Q1 Q0 K3 J3 K2 J2 K1 J1 K0 J0
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0
0 1 0 0 0 1 0 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 1 1
0 1 1 0 1 0 0 0
1 0 0 0 1 0 0 1
1 0 0 1 0 0 0 0

Transition Table:

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Course Title: Lab-12
Digital Logic & Design JK-Flipflop and Designing of Decade Counter
K-Map:

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Course Title: Lab-12
Digital Logic & Design JK-Flipflop and Designing of Decade Counter
Equation:

Circuit Diagram:

In Case of Trouble:
1. Check the power supply.
2. Check the VCC and GND at pins 14 and 7 of the IC.
3. Check all the wire connections.
4. Check the circuit wiring and remove the breaks.
5. Check the lC using truth table.

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Course Title: Lab-13
Digital Logic & Design To check the read /write operation of RAM

Lab 13
To check the read/write operation of RAM
OBJECTIVE A: To check read/write operation of RAM

Components:
1.74LS47x1
2.74LS93x1
3.74LS170x1

Tools:
1.AM2000 trainer.
2.Multimeter.
3.Cutter.
4.Single Core Wire.
5.Tweezer.
6. Pairs of pliers.

Theory
A memory is an important part to store information. Computer memories include tapes,
punched cards, magnetic disks and semiconductor devices.
RAM is a semiconductor memory wherein any location is accessible to retrieve (read) or store
(write) information regard to any other location. In figure 16.1 a basic cell of read/write RAM
which consist select, data input, output and read/write lines. The select input enables the cell
for writing or reading. The read/write input determines the operation on the selected cell.

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Course Title: Lab-13
Digital Logic & Design To check the read /write operation of RAM
Procedure:
1. Connect the AM2000 trainer to the 220v AC power supply.
2. Turn on the trainer and verify the voltage of the power supply using the Multimeter.
It should be +5 V exactly.
3. Write operation: Install the 4x4 RAM chip 74LS170 and the binary counter 74LS93 on the
trainer's breadboard.
4. Write the circuit as shown is figure 13.2.
5. Use logic switches s2 through s5 for data inputs A through D.
6. For read and write enable inputs, i.e., pin #11 and #12, use logic switches s6 and s7
respectively. It normally places the memory in read mode.
7. Use LED L1 and L2 for outputs A and B of the counter.
8. The outputs of A and B of the binary counter 7493 are connected to the read/write select
Inputs of the RAM whereby the address from AB=00 to AB=11 is selected. Use logic switch
S8 for setting the counter in state AB=00.
9. Set Logic switches s2 through s5 in the state 0000, use logic switches s6 and s7 to load the
binary word into the memory.
10. Observe the output and record your observation in table.
11. Use the Logic switch s8 to select the next memory address. The display goes blank. Reset
the logic switch S2 through S5 to 0101 and load it into selected location by operating the logic
switches s6 and s7. Observe the output and record observation in table. Repeat the process
until four words are loaded into memory.
12. READ OPERATION: Operate the logic switch s8 four times to sequence the counter from
AB=00 to AB=11. Observe the selected address on l1 and l2 and the RAM contents on the 7-
segment Display.

Address Binary Word Loaded Output

A B S2 S3 S4 S5 Display
0 0
0 1
1 0
1 1

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Course Title: Lab-13
Digital Logic & Design To check the read /write operation of RAM

In Case Of Trouble:

1. Check the power supply.

2. Check the VCC and GND of the IC's.
3. Check all the wires connections.
4. Check the circuit and remove the breaks.
5. Check the Ic using truth table.

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Course Title: Lab-14
Digital Logic & Design To demonstrate binary up-down counter

Lab 14
To demonstrate binary up-down counter
OBJECTIVES:

To demonstrate the proper connections for a binary up counter

To demonstrate the proper connections for a binary down counter

To connect and operate an MSI UP/DOWN counter

Preparation:

A binary counter is generally used in applications requiring the counter to progress through its
states in an increasing binary-count sequence; however, it is occasionally desirable to use a
counter which will progress through a decreasing binary-count sequence. A counter which can
be used to count upward or downward is called an UP-DOWN Counter. UP-DOWN Counter are
useful in many application, one of the most important is analog to digital conversion.

Fundamental Concepts:

A four Flip-flop binary counter has 16 possible states and its normal count sequence is 0000,
0001, 0010… 1111, and back to 0000. Since the counter begins at zero and each succeeding
state is a larger number, this is considered to be an up counter. Of course, the counter resets
itself when passing from count 15 (1111) to zero (0000).

On the other hand, a four-flip-flop down counter is one which still has the same 16 possible
states but has a normal count sequence 1111, 1110, 1101… 0000, 1111. That is the counter
begins at 15 (1111), and each succeeding state is a smaller number. The reset here occurs as
the counter progresses from zero (0000) to 15 (1111).

It is really quite simple to construct a binary up-down counter, i.e. a counter capable of
counting either up or down. The fundamental ideas are shown in Fig.1. In Fig.1 a, each flip-flop
is triggered with the true side of the previous flip-flop. This forms a simple binary ripple counter
which progresses naturally through an up count sequence.

In Fig.1 b, each flip-flop is triggered with the complement side of the previous flip-flop. This
forms a simple binary ripple counter which progresses naturally through a down count
sequence.

UP/DOWN COUNTER:
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Course Title: Lab-14
Digital Logic & Design To demonstrate binary up-down counter
A compete up/down counter can be constructed by incorporating the appropriate logic so that
the input to each flip-flop can be taken from the true or the complement side of each previous
flip-flop as shown in figure 2. In this diagram, holding count up high will enable the upper AND
gates, and holding count down low will disable the lower AND gates. The counter will then
function as an up counter. On the other end, if count up is low and down is high, it will function
as a down counter. Notice that, if count-up and count-down are both held low, the counter will
cease to operate. Also if count-up and count-down are both held high, the counter will not
function properly. Therefore count up must always be the complement of count-down for this
configuration. The counter in figure 2 is a serial ripple counter, sometimes referred as an
asynchronous counter. For greater speed, up-down counters are often constructed as parallel
or synchronous counter.

Figure 14.1

Figure 14.2

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Course Title: Lab-14
Digital Logic & Design To demonstrate binary up-down counter
MSI 193

The 193 is a synchronous up-down 4-bit binary counter. It has a master reset input (CLR), and it
can be reset lo any desired count with the parallel load inputs. Basically, it functions just like the
counter in fig. 2 except that the clock (either UP or DOWN) and the output of each previous flip-
flop are connected to each AND gate. Thus each flip flop is clocked resulting in a parallel or
synchronous, operation.

The logic symbol of MSI 193 is shown in Figure 14.3. (Examine the data sheet for logic diagram),
LOAD is control input to load data into pins A, B, C, and D. When the device is used as a counter,
pins A, B, C, and D are left open and LOAD is held high.

Pin CLR is the master reset, and it is normally held low (a high level on CLR will reset all flip-
flops). CO and BO arc output to be used to drive following 193s, and we shall simply leave them
open.

Now the clock inputs are UP and DOWN. Placing the clock on UP will cause the counter to count
up, and placing the clock on DOWN will cause counter to count down. Notice that the clock
should be connected to either UP or DOWN but not both and the unused inputs should be held
high.

Figure 14.3

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Course Title: Lab-14
Digital Logic & Design To demonstrate binary up-down counter
SELF TEST:

1- Draw the expected waveforms for the up counter in Fig 1a.

Clock
A
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B
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C
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2- Draw the expected waveforms for the down counter in Fig 1b.
Clock
A
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B
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C
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3- The J and K inputs to the flip-flops in Figs. 1 & 2 have no connections. The flip-flops are
being used as simple toggle, should there be any connections to the J and K inputs.
________________________________________________________________________
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____________

4- A set of waveforms for a “typical clear, load and count sequence” are given on the
54ALS193 data sheet. The waveforms illustrate how to preset to binary 13. Show how to
alter these waveforms to preset to binary 7.

PROCEDURE:
Equipment and parts required:
3 JK master/slave flip-flop '7476 or equivalent
4 AND gate, 2-input, '11 or equivalent
2 OR gates, 2-input, '32 or equivalent
1 binary up-down counter, 4-bit, '193 or equivalent
1 square-wave signal generator, 0- to + 5v dc levels, variable frequency
1 power supply, 5 V d

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Course Title: Lab-14
Digital Logic & Design To demonstrate binary up-down counter
1 oscilloscope, dc-coupled, dual trace
1- Construct the up counter shown in Fig. 1a, and apply the clock. You may prefer to use
the output of a one shot actuated by push button 'or a pulse generator set at a low
repetition rate for the Clock. Record the output waveforms observed. Notice carefully
the phase relationships with respect to the clock (remember there are eight discrete
states).
Clock
A
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B
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C
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2- Construct the down counter in Fig. 1b, apply the clock and record the output waveform
observed.
Clock
A
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B
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C
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3- Construct the up-down counter shown Fig, 2. Ground the count-down line, and apply +
V (+5v dc) to the count-up line. Apply the clock, and carefully record the output
waveform with respect to the clock. Be sure to include all eight slates.
Clock
A
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B
_______________________________________________________________________
C
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Course Title: Lab-14
Digital Logic & Design To demonstrate binary up-down counter
4- Ground the count up line and apply + V (+5v dc) to the count-down line. Apply the clock,
and carefully record the output waveform.
Clock
A
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B
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C
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5- Examine the data sheet for MSI 193 up-down counter to determine proper pin
locations. Record the maximum supply current required for 5 V dc.
I ______________________________________________________________________
Make connections to the counter in figure 3 as follows.
Pins 15, 1,10,9 (preset data inputs) Open
Pins 12, 13 (CO & BO) Open
Pins 2, 3, 6, 7 (outputs) to indicator lamps or oscilloscope
Pin 11 (LOAD) to + V
Pin 16 (+ V) to + V
Pin 14 (CLR) to ground
Pin 8 (GND) to ground

6- Now for the count up mode, connect pin 4 down to +V, and apply the clock to pin 5 up.
Record carefully the 4 output waveforms with respect to the clock. Remember a four
flip-flop counter has 16 states.
Clock

QA_____________________________________________________________________

QB_____________________________________________________________________

QC_____________________________________________________________________

QD_____________________________________________________________________

CO_____________________________________________________________________

BO___________________________________________________________________

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Course Title: Lab-14
Digital Logic & Design To demonstrate binary up-down counter
7-For the count-down mode, pin 5 (UP) to + V and apply the clock to pin 4 (DOWN). Record the
resulting waveforms.

Clock

QA_____________________________________________________________________

QB_____________________________________________________________________

QC_____________________________________________________________________

QD_____________________________________________________________________

CO_____________________________________________________________________

BO_____________________________________________________________________

7- Apply the clock to both pins 4 (DOWN) and 5 (UP) simultaneously and note the results
here.

Questions:

1- Use the waveform from step 1 in the procedure to write a truth table for up counter in
fig 1a.

2- Use the waveform from step 2 in the procedure to write a truth table for down counter
in fig 1b.

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Course Title: Lab-14
Digital Logic & Design To demonstrate binary up-down counter
3- Do the waveforms in step 3 and 4 for the procedure match the waveforms problems
1&2 of the self-test and 1&2 of the procedure?

4- Write a 16 state truth table and show by arrows alongside it the directions for counting
up & down. From this table, label the states for 0000, 0010, 0100, 1000 and 1111 on the
waveform recorded in steps 6&7 of the procedure.

State QA QB QC QD
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
5- Explain how the circuit in fig 4 will guarantee that UP-DOWN so that the counter will
always be in either the count-up or count-down mode.

Figure 14.4

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