Microprocessors and Microsystems 73 (2020) 102964

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Microprocessors and Microsystems

journal homepage: www.elsevier.com/locate/micpro

Effective RCA design using quantum dot cellular automata

Jeyalakshmi Maharaj a,∗, Santhi Muthurathinam b
a
Department of Electronics and Communication Engineering & Anna University, SSM Institute of Engineering and Technology, Dindigul, Tamilnadu, India
b
Department of Electronics and Communication Engineering & Anna University, Saranathan College of Engineering, Tiruchirappalli, Tamilnadu, India

a r t i c l e i n f o a b s t r a c t

Article history: Quantum dot Cellular Automata (QCA) is a transistor less technology alternative to CMOS for develop-
Received 24 October 2019 ing low-power, high speed digital circuits. Adder circuits are broadly employed in all digital computation
Revised 12 December 2019
systems. In this paper, a novel coplanar QCA full adder circuit is proposed which is designed with min-
Accepted 20 December 2019
imum number of QCA cells. The proposed full adder requires only 13 QCA cells, an area of 0.008 μm2
Available online 26 December 2019
and delay of about 2 clock cycles to implement its function. Then an efficient 4-bit Ripple Carry Adder
Keywords: (RCA) is designed based on the proposed full adder that performs higher end addition in an effective
Quantum dot Cellular Automata (QCA) way. Simulations results are obtained precisely using QCA designer tool version 2.0.3. Also the simulation
Majority voter gate results shows that the proposed 4-bit Ripple Carry Adder (RCA) requires only 70 QCA cells, an area of
1- bit full adder 0.18 μm2 and delay of about 5 clock cycles to implement its function with enhanced performance in
Ripple Carry Adder (RCA) terms of latency, area and QCA Cost. From the comparisons, it is found that our work achieves over 55%
improvement in QCA cell count.
© 2019 Elsevier B.V. All rights reserved.

1. Introduction posed which is designed with minimum QCA cells compared to

the existing designs. In QCA, only few Ripple Carry Adders (RCA)
QCA technology is a new platform which implements complex [3,15,20] are proposed. Also a Ripple Carry Adder (RCA) is designed
VLSI architectures with very less power consumption and achieves using a proposed Full adder which has improved performance in
high speed at nano-scale level compared to CMOS technology [1]. propagation delay and cell count. This adder architecture finds ap-
Also, in CMOS technology, the voltage and current represents the plications in designing all secured Nano-communication network.
binary values and the circuit switching frequency couldn’t be in- The rest of the paper is organized as follows: Section 2 de-
creased beyond certain values. scribes the fundamental information in QCA. Section 3 de-
The limitations of CMOS technology such as high integration scribes the existing designed full adders and their limitations.
density within small area due to large number of transistors and Sections 4 and 5 presents the proposed 1-bit full adder and 4-
wire connections between them was overcome by QCA technol- bit Carry propagation adder design and their implementations.
ogy. In this technology, the binary information could be transmit- Section 6 presents the performance evaluation of the proposed
ted through Coulombic repulsion [2] between the neighboring QCA adders and previous adder design. Results and comparison are dis-
cells. It is a transistor less technology. Here, the binary value 0 or 1 cussed in Sections 7 and 8 gives the conclusion of the proposed
is encoded through the reconfigurations of electrons in the quan- work.
tum dots of QCA cells.
Adder architecture is a basic architecture in constructing all dig- 2. QCA basics
ital circuits [3]. Many computational blocks such as multipliers,
arithmetic logic unit’s (ALU), shift registers are constructed using 2.1. Quantum dot cellular automata cell and QCA wire
these adders in QCA technology. Many high speed DSP proces-
sors architecture designs and parallel computations also depends QCA based circuits are constructed using QCA cells. The square
on adder design. Many adders were constructed and implemented shape QCA cells [1] comprises of four quantum dots with two dots
previously in QCA [2–9]. In this paper, a new Full adder is pro- occupied by electrons. These electrons resides over in the diagonal
corner of the cell due to Coulombic repulsion [3] of force between
them. Tunneling of electrons between the quantum dots results in
∗
Corresponding author. two polarized states. These states namely PL = −1 and PL = +1
E-mail addresses: jeyame20@gmail.com (J. Maharaj), santhiphd@gmail.com [1,3] represents logic value ‘0’ and ‘1’ respectively as shown in
(S. Muthurathinam). Fig. 1(a).

https://doi.org/10.1016/j.micpro.2019.102964
0141-9331/© 2019 Elsevier B.V. All rights reserved.
2 J. Maharaj and S. Muthurathinam / Microprocessors and Microsystems 73 (2020) 102964

Fig. 1. (a) Polarization state of a cell (b) QCA wire.

Fig. 2. (a) Clock zones of QCA cells (b) QCA clocking.

Wires in QCA, are constructed either using normal cell or ro-

tated cell [12]. Due to its less complexity, normal cell as shown in
Fig. 1(b) are preferred over compared to rotated cell [16]. The po-
larization state of cells gets changed when input is applied at one
end of the wire. Based on the polarization [11] either logic ‘0’ or
logic ‘1’ will be a transmitted horizontally or vertically.

2.2. QCA clocking

Two ways of Clocking is performed: zone clocking and contin-

Fig. 3. (a) Majority voter gate (b) AND gate (c) OR gate.
uous clocking. The input is directed towards the output precisely
under zone clocking. The propagation delay in QCA circuits is re-
duced far by assigning the clock zones to different parts of the
circuits which will change the potential barrier between quantum
dots. As shown in Fig. 2(a) there are four clock zones [1,10] in QCA 2.3. QCA logic gates
circuits are clock zone 0, clock zone 1, clock zone 2, and clock
zone 3 whose phase differs by 90°. The cells with identical color Designing the QCA circuit generally requires an Inverter, QCA
are assigned the same clocking zone. Accordingly there are four wire and a three-input Majority Voter gate [16]. The signal propa-
phases [18] in QCA circuits namely switch, hold, and release and gates in QCA wire as a result of the electricity interlinkage between
relax phase [8] respectively as shown in Fig. 2(b). cells. A Majority Voter gate has five cells. Among five, three cells
Clocking in QCA is used to control the polarization state of cells. works as input cells and one cell works as output cell as given in
In a circuit designed using QCA, the overall delay is proportional to Fig. 3(a). The middle cell is called as device cell (8) and its logic
the number of zones within the path with the longest delay. operation depend on logic of input cells. The equation given in
 J. Maharaj and S. Muthurathinam / Microprocessors and Microsystems 73 (2020) 102964 3

Fig. 4. QCA layout of earlier designs (a) In (3) (b) In (6) (c) In (7) (d) In (9) (e) In (22).

(1) explains the Boolean logic of Majority Voter gate. 3. Existing designs
∗ ∗ ∗
MV (A, B, C ) = F = (A B ) + (B C ) + (C A ) (1)
Trailokya and Ashutosh (3) designed a one-bit Full adder which
Where A, B, C are inputs and F is the output. With Majority Voter consists of three-input XOR gate and a three-input majority gates.
gate, AND gate is constructed as shown in Fig. 3(b). Among the This design incorporates a QCA cell count of about 40 cells as
three input cells of the AND gate, one cell is having a fixed po- shown within the Fig. 4(a). An increase in the QCA cell count ends
larization PL = -1. Logical function implementation of AND gate is up in an increase of the area and delay of the design. Abedi and
Y = A ∗ B. Also a Majority Voter gate is used to construct an OR- Jaberipur [6] designed a Full adder that has 59 QCA cells and de-
gate as shown in Fig. 3(c). Among the three input cells, one cell lay of 1 clock phases as shown within the Fig. 6(b). Mersede and
is having a fixed polarization PL = +1. Logic function for OR gate Keivan (7) designed a Full adder that requires three majority and
implementation is, Y = A + B. two inverter gates. The adder in this design comprises of 37 QCA
4 J. Maharaj and S. Muthurathinam / Microprocessors and Microsystems 73 (2020) 102964

Fig. 5. (a) Schematic diagram of 1-bit full adder (b) 1-bit full adder (c) Schematic diagram of 2-bit RCA (d) Layout of 2-bit RCA (e) Schematic diagram for 4-bit RCA (f)
Layout of 4-bit RCA.
 J. Maharaj and S. Muthurathinam / Microprocessors and Microsystems 73 (2020) 102964 5

Fig. 6. Comparison of 1-bit full adder (a) QCA cell count (b) Area (c) QCA cost.

cells which require more than two clock phases for generating the    
carry and sum outputs as shown within the Fig. 6(c). Hamid and Sum = A0  B0 C0 + B0C0  + A0 B0C0 + B0 C0  (3)
Abdalhossein (9) designed a 1-bit QCA full adder that has 33 QCA
cells and delay of 2 clock phases as shown within the Fig. 6(d).
Shahram and Ali [22] designed a Full adder that has 26 QCA cells Sum = A0  (B0  C0 ) + A0 (B0  C0 ) (4)
and delay of 2 clock phases as shown within the Fig. 6(e).

4. Proposed 1-bit full adder design

Sum = A0  B0  C0 (5)

Full adder is the basic element in performing all arithmetic and Cout = MV (A0 , B0 , C0 ) (6)
logical operations in ALU of a processor. To obtain an efficient ar-
chitecture in terms of latency, area and delay here a coplanar im-
plementation of Full adder has been designed which is given in Cout = (A0 B0 ) + (B0C0 ) + (C0 A0 ) (7)
Fig. 5(a). Coplanar crossover is preferred over multilayer crossover
The adder proposed here requires only thirteen QCA cells with
because properly aligned regular QCA cells and 45° rotated cells
two clock phases which was not yet achieved in previous design.
that do not interact with each other could be used. Also the com-
The area required for the proposed full adder is about 0.009 μm2
plex circuits could be realized easily using coplanar crossover. This
which reinforces the implementation of the design. This design at-
adder comprises of an inverter and a Majority Voter gate. So, min-
tains the lowest latency owing to the less count of QCA cells. The
imum number of logic gates has been preferred over here which
QCA layout is shown in Fig. 5(b).
minimize the QCA cell count and delay. Let the three inputs of full
adder are A0 , B0, and Ci and their corresponding outputs are Sum
5. Proposed higher adder circuit
and Carry. The inputs are given to the full adder using three-input
MV gate.
The proposed Full adder is very simple in implementing higher
The sum output of full adder are derived as per Eqs (2)–(4).
adder designs. Using this Full adder, higher adders like 2-bit and
Finally derived equations representing the sum and carry output
4-bit RCA (Ripple Carry Adder) has been designed with reduced
of full adder are given in (5), (6) and (7).
number of QCA cells that stands completely different from the ear-
Sum = A0  B0 C0 + A0 B0C0  + A0 B0C0 + A0 B0 C0  (2) lier designs.
6 J. Maharaj and S. Muthurathinam / Microprocessors and Microsystems 73 (2020) 102964

Fig. 7. Comparison of 4-bit RCA (a) QCA cell count (b) Area.

Table 1
One-bit full adder: a comparison.

Reference QCA Cell Count Area(μm2 ) Delay (Clock Phase) Application Cost(Area∗ Latency)

[1] 28 0.01 2 Multilayer 0.0050

[3] 40 0.03 05 Coplanar 0.015
[4] 47 0.02 15 Multilayer 0.3
[5] 114 0.23 1.25 Coplanar 0.287
[6] 59 0.043 1 Coplanar 0.043
[7] 37 0.0245 1 Coplanar 0.0245
[8] 115 0.1020 1.25 Coplanar 0.1275
[9] 33 0.02 0.5 Coplanar 0.01
[12] 39 0.027 4 Coplanar 0.108
[13] 25 0.01 2 Coplanar 0.02
[14] 30 0.028 0.75 Coplanar 0.021
[15] 30 0.04 0.5 Coplanar 0.02
[17] 63 0.05 0.75 Coplanar 0.028
[20] 44 0.06 1.25 Coplanar 0.075
[22] 44 0.03 0.5 Coplanar 0.015
Proposed 13 0.009 2 Coplanar 0.018

Table 2
4-bit RCA: comparison.

Reference QCA Cell Count Area(μm2 ) Delay (Clock Phase) Application Cost(Area∗ Latency)

[3] 212 0.194 05 Coplanar 0.97

[14] 125 0.17 5 Multilayer 0.85
[15] 209 0.3 1.25 Coplanar 0.375
[17] 295 0.3 1.5 Coplanar 0.45
[19] 339 0.25 1.75 Coplanar 0.437
Proposed 70 0.18 5 Coplanar 0.9

In 2-bit RCA, only two Majority Voter gates and two inverter 6. Performance evaluation
gates are needed to design the architecture. The schematic diagram
and layout of a 2-bit and 4-bit RCA (Ripple Carry Adder) are given QCA Designer version 2.0.3 tool is taken into account as effec-
in Fig. 5(c), (d), (e) and (f) respectively. Similarly by providing three tive in coming up with the QCA layout of adder design. To check
inputs An , Bn and Cn to the n-bit Full adder, an n-bit RCA can be the proficiency of proposed adders with existing adders, parame-
designed. The equation for the carry (Cn+1 ) and sum (Sn ) output of ters like delay, area and Quantum cost has been considered and
n-bit Full adder is carried out by (8), (9) and (10) compared as given in Table 1. It addresses the assessment among
the designs of proposed 1- bit Full adders and prior designs. From
Cn+1 = MV (An , Bn , Cn ) (8)
the comparison, it seems that our proposed adder has attained less
number of QCA cells. Also it is esteemed that this adder yields
Cn+1 = (An Bn ) + (BnCn ) + (Cn An ) (9) higher capability in terms of area and delay as estimated by com-
parison chart given in Fig. 6(a), (b) and (c).
Table 2 shows the comparison of 4-bit RCA with the earlier
Sn = An  Bn  Cn (10)
designs. The proposed RCA design shows the exceptional perfor-
The proposed 4-bit RCA has four Majority voter gate (MV) and mance than the multilayer design in various parameters such as
four QCA XOR Gates to implements its function Here the circuit latency, area and cell count. Also it is esteemed that this adder
needs 60 QCA cells to design a 4-bit RCA and the eventual outputs yields higher capability in terms of area and delay as estimated by
are produced after certain latency. comparison chart given in Fig. 7(a) and (b).
 J. Maharaj and S. Muthurathinam / Microprocessors and Microsystems 73 (2020) 102964 7

Fig. 8. (a) Simulation result of one-bit full adder (b) Simulation result of 4-bit ripple carry adder.

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