BITS, Pilani- K.K.
Birla Goa Campus
First Semester 2023-24
Course Handout (Part-II)
In addition to Part I (General Handout for all the courses appended to the time table), this
portion gives further specific details regarding the course.
Course No. : ECE/EEE/INSTR F215
Course Title : Digital Design
Instructor-In-charge : Anita Agrawal
Team of Instructors : Ramesh Vasan ,Arun Raman, Chirayu Amita Dilip Athalye
:
Course Description: This course covers the topics on logic circuits and
minimization, Digital ICs, Combinational and Sequential logic
circuits, State table and State diagrams,
Programmable Logic devices, Arithmetic Operations and
Algorithms, Introduction to Computer Organization,
Algorithmic State Machines.
Scope and Objective: The objective of the course is to impart knowledge of the
tools for the design of digital circuits and to provide methods
and procedures suitable for a variety of digital design
applications.
The course introduces fundamental concepts of Computer
Organization too. It also includes laboratory practice using
MSI devices.
Text Books:
T1: M.Morris Mano and Michael D.Ciletti, “ Digital Design”, PHI, 4th Edition
Reference Books:
R1 Donald D. Givone , “Digital Principles and Design”, TMH 2003
R2 Samir Palnitkar, “Verilog HDL”, Pearson Education.
Course Plan:
Lect. Reference to
Learning Objectives Topics to be covered
No. Text Book
Introduction to Digital
Systems and Digital Systems, Digital ICs 1.1; 1.9; 2.8, 2.9,
1
Characteristics of Digital 10.1,2
ICs.
Boolean functions, Canonical
Boolean algebra and logic forms, Standard forms,
2-3 2.2-2.7
gates conversion between different
forms
Codes, Number Systems Different Number systems such
4-5 1.2-7
as binary, octal etc and codes
such as BCD, Excess-3 etc..
K-Maps (2,3,4 & 5 variables),
6-8 Simplification of Boolean
Different types & levels of 3.1 to 3.9
functions
implementations.
Simulation and Synthesis Hardware Description
9 3.11
basics Language (HDL)
Combinational Logic,
10-11 Adders, Subtractors Multipliers 4.1 - 4-7
Arithmetic circuits
Comparators, Decoders,
12-14 MSI Components 4.8 to 4.11
Encoders, MUXs, DEMUXs
Simulation of
15 Combinational Logic HDL for Combinational Logic 4.12
Functions.
Latches, Flip-Flops &
16-18 Sequential Logic 5.1 to 5.4
Characteristic tables
Analysis of clocked sequential
Clocked Sequential
19-22 circuits, state diagram and 5.5, 5.7, 5.8
Circuits
reduction
Shift registers, Synchronous & 6.1 to 6.5
23-25 Registers & Counters
Asynchronous counters
26-28 Memory and PLDs RAM, ROM, PLA, PAL, FPGA 7.1-7.3 7.5 to 7.7
TTL, MOS Logic families and
Digital Integrated 10.3-10.5, 10.7 to
29-31 their characteristics
Circuits 10.9
Analysis of arithmetic Multiplication & Division
32-34 Class Notes
units algorithms
Design of Asynchronous
35-37 Asynchronous Sequential Logic 9.1 – 9.4
Circuits.
Design of Digital
38-40 Systems using software Algorithmic State Machines R1: Chapter 8
approach
Evaluation Scheme:
Component Duration Weightage Date & Time CB/OB
14-10-23
Midsem 1.5 hrs. 20% CB
9:00 AM-10:30 AM
Quiz ** 10% ** CB
Comprehensive Examination 3 Hrs 40% 15-12-23 (FN) CB
scheduled
20%
Laboratory +Verilog eval hrs.as per OB
time-table
Lab Comprehensive ** 10% ** CB
** To be announced later
Laboratory
S.No. Name of Experiment
1. IMPLEMENTATION OF BOOLEAN FUNCTIONS USING LOGIC GATES
2. ADDERS AND SUBTRACTORS
3. BCD ADDER
4. DECODERS/ DEMULTIPLEXERS, MULTIPLEXERS AND COMPARATORS
5. LATCHES & FLIP-FLOPS
6. OPERATION OF 4-BIT COUNTER
7. COUNTERS
8. SHIFT REGISTERS
9. SEQUENCE DETECTORS
Chamber Consultation Hour: To be announced in class
Notices: All notices and announcements will be posted in the course folder on moodle.
Make-up Policy: Make-up in any of the components may be granted only in extremely
genuine cases (admitted to hospital) and with prior permission.
INSTRUCTOR-IN-CHARGE
