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ELECTRONIC DEVICES
CHAPTER 3

Field Effect Transistor

Lecturer: Dr. Đào Việt Hùng

Department of Electronics
School of Electrical and Electronic Engineering
Hanoi University of Science and Technology
Email: hunget.bk@gmail.com
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What is Field Effect Transistor?
 Field effect transistor (FET, transistor hiệu ứng
trường) is an unipolar transistor.
 FET uses electric field to control the conductivity of
a conductive channel.
 There are many types:
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FET vs. BJT

Criteria BJT FET

Charge carriers Both e and h (bipolar) Only e or h (unipolar)

Terminals C, B, E D, G, S

Main mechanism Current-controlled: IB controls IC Voltage-controlled: UGS controls ID

Types NPN or PNP N-channel or P-channel

 Linear, easy to use  Very high input impedance

Advantages
 High current, high voltage  Fast switching

 Digital ICs
Typical  Analog amplifiers
 High current and high speed
applications  Discrete analog circuits
switching elements
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Contents

1. Junction FET
2. Metal Oxide Semiconductor FET
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1 - Junction FET

 Structure and basic operation

 Characteristic curves of JFET
 Shockley equation and transconductance
 JFET biasing
 Parameters and datasheets
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1.1 Structure and basic operation
 JFET (junction FET) is constructed by:
– A long channel of N-type (or P-type) semiconductor
material: One end forms the Drain (D, máng) while the
other forms the Source (S, nguồn).
– A region of P-type (or N-type) surrounds the channel to
form a P-N junction. This region is called Gate (G, cửa)
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1.1 Structure and basic operation
 Two types of JFET: N-channel and P-channel.
 N-channel has better characteristic than P-channel.
Why? (…recall Chapter 2)
 Symbols:

N-channel P-channel
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1.1 Structure and basic operation

 For proper operation, FET need to be biased.

 The JFET is always operated with the G-S
junction (P-N junction) reverse-biased 
– N-channel type: UGS ≤ 0; UDS > 0
– P-channel type : UGS ≥ 0; UDS < 0

N-channel JFET
biasing
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1.1 Structure and basic operation

 Consider an example:
N-channel JFET with
UGS ≤ 0 and UDS > 0
– First:
• Fix: UGS = 0
• Change: UDS > 0
 Phenomenon:
• G-S is reversed-biased,
hence IG = 0.
• A thin depletion region is
produced along the P-N
junction.
• The channel is a ohmic
conductor.
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1.1 Structure and basic operation
– When UDS increased 
differences among
voltages along the
channel increase.
 Phenomenon:
• The depletion region is
gradually extended.
• Wider depletion region,
lower channel
conductivity  channel
becomes “non-ohmic”.
• Always: IG = 0
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1.1 Structure and basic operation
– When UDS is high enough
(= UP) the channel is
“pinched” and ID reaches
maximum value  UP is
called “pinch-off” voltage.

– When UDS > UP  ID

maintains a saturation
level defined as IDSS

IDSS = Drain to Source current with gate Shorted

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1.1 Structure and basic operation
– Second:
• Fix: UGS < 0
• Change: UDS > 0
 Phenomenon:
• The reversed voltage of the P-N
junction is “added” an amount =
|UGS|  channel is “pinched”
earlier (UDS < UP).
• More negative value of UGS 
channel is pinched faster  the
saturation of ID is smaller.
• When UGS = UGS(off) = −UP  the
channel is pinched regardless the
value of UDS  JFET has been
“turned off”.
In conclusion, UGS can be used
to control the saturation value UGS = −1 V
(maximum value) of ID
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1.2 Characteristic curves of JFET

 There are 2 important characteristic curves:

– Family of drain characteristic curves: present the
relation between ID and UDS at different values of UGS.

Recall BJT: Collector characteristic curves

– Transfer characteristic: presents the relation between

UGS and ID (UGS controls ID).

 Recall BJT: relation between IB and IC

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1.2 Characteristic curves of JFET

 Drain characteristic curve when UGS = 0

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1.2 Characteristic curves of JFET
Comments:
– Ohmic region: the depletion region is thin  ID is a linear
function of UDS.
– Active region: channel is pinched off, ID = constant
regardless the increment of UDS.
Explanation: When ID tends to increase  differences
among voltages along the channel increase  UDG (P-N
junction) increases  the depletion is extended  channel
is strongly pinched  ID decreases  ID is kept constant.
– Breakdown region: P-N junction is broken down  JFET is
destroyed.
 There are 2 important parameters:
• Pinch-off voltage: UP
• Saturation value of ID when UGS = 0: IDSS

IDSS = Drain to Source current with gate Shorted

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1.2 Characteristic curves of JFET

 Family of drain characteristic curves:

– Set of curves, with many values of UGS.
– The family of curves shows: IDSS, UP, UGS(off)
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1.2 Characteristic curves of JFET

 Transfer characteristic:
– Presents the relation between UGS
and ID (UGS controls ID).
– Can be plotted based on 4 special
points as in the figure.
– Can also be developed from the
drain characteristic curves by
plotting values of ID for the values
of UGS taken from the family of
drain curves (see next page).
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1.2 Characteristic curves of JFET
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1.3 Shockley equation and transconductance

 The JFET transfer characteristic curve can be

expressed approximately as:
2
 UGS 
ID  IDSS  1  
 U
 GS ( off ) 

 With a given JFET, ID can be calculated based

on UGS
 JFET (and MOSFET in the next section) is
called “square-law device”  non-linear!
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1.3 Shockley equation and transconductance

 Forward transconductance: gm
ID
gm 
UGS

 Unit of gm: S or mho

 Within a JFET, value of gm
depends on the working point.
 Datasheet usually gives gm0 at
UGS = 0
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1.3 Shockley equation and transconductance

 Value of gm at any point can be calculated from

gm0 by:
 UGS 
gm  gm0 1  
 U 
 GS ( off ) 

 If not given, the value of gm0 can be calculated:

2IDSS
gm0 
UGS ( off )
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1.4 JFET biasing
 The nature of work: creating a negative value of
UGS to pinch the channel  ID is saturated and
ready for being controlled.
 There are 3 types of bias:
– Fixed-bias
– Self-bias
– Voltage-divider bias
 In each type, we consider:
– Position of the Q-point.
– The stability of the Q-point when parameters (IDSS, UP,
gm) of JFET vary.
– A good bias circuit: IDQ is highly stable
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1.4 JFET biasing
 Note: the stability of the bias
circuit is very important
because the transfer
characteristic of a JFET can
differ considerably from one
device to another of the
same type.
 E.g., 2N5459:
– IDSS: 4 ÷ 16 (mA)
– UGS(off): −2 ÷ −8 (V)

 If using a bad bias circuit,

10 JFET 2N5459 can work at
10 different Q-point!
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1.4 JFET biasing
+EDS
 Fixed-bias:
RD
• Connect EGS between G and S 
create a negative UGSQ. D
• RG: to avoid shorting the input
G
signal to ground.
• Q-point: RG S
• UGSQ = −EGS (because IG = 0) UGS
EGS -
• UDSQ = EDS – ID.RD
• IDQ: using Shockley equation +

 Q(UGSQ, IDQ, UDSQ)

N-channel JFET
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1.4 JFET biasing
ID
 Fixed-bias:
• Q-point can be determined
by using the transfer
characteristic
Q
IDQ

UGS
UP UGSQ = EGS

• Stability of Q-point: bad …? Starting point

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1.4 JFET biasing
 Self-bias: +EDS
– ID = IS flows through JFET  create a dropout
voltage on RS  the negative UGS. ID RD
• RG: to avoid shorting the input signal to D
ground.
 Q-point: G
• VG = 0 (because IG = 0)
• VS = IS.RS = ID.RS S
UGS
 UGS = −ID.RS RG
RS
• Combined with the Shockley equation  a
IS
quadratic equation of UGS  there are 2
solutions choose |UGS| < |UP|
 UDSQ = EDS – IDQ.(RD + RS)

 Q(UGSQ, IDQ, UDSQ) N-channel

JFET
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1.4 JFET biasing

 Self-bias:
• Q-point can be
determined by using the ID
transfer characteristic
IDSS
Q is the intersection of the
transfer characteristic curve and
the line UGS = − ID.RS

Q IDQ
• Stability of Q-point:
relatively good …?
UGS
UP UGSQ = EGS
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1.4 JFET biasing
+EDS
 Voltage-divider bias:
– UGS is created by the voltage-divider and
the dropout on RS. ID RD
R1
 Q-point: D
• VG = EDS.R2/(R1 + R2) (because IG = 0)
• VS = IS.RS = ID.RS IP G
 UGS = VG – ID.RS S
• Combined with the Shockley equation  UGS
R2
a quadratic equation of UGS  there are RS
2 solutions choose |UGS| < |UP|
IS
 UDSQ = EDS – IDQ.(RD + RS)

 Q(UGSQ, IDQ, UDSQ)

N-channel
JFET
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1.4 JFET biasing

 Voltage-divider bias:
• Stability of Q-point: good …?

ID

IDSS

Q is the intersection
of the transfer
characteristic curve Q IDQ
and the line
UGS = VG − ID.RS

UGS
UP UGSQ VG
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1.4 JFET biasing

Fixed-bias Self-bias Voltage-divider bias

Bad Relatively good Good

+EDS
+EDS +EDS
RD ID RD ID RD
D D R1
D
G G
IP G
RG S
UGS S S
UGS UGS
EGS - RG R2
RS RS
+
IS IS
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1.5 Parameters and datasheets

 Similar to the other semiconductor components,

JFET has some maximum rating: ID(max), UDS(max),
PD(max), …
 Dedicated parameters:
– IDSS: drain to source current with gate shorted
– UGS(off) = −UP: cutoff voltage and pinch-off voltage
– gm: forward transconductance
– rG: input resistance
– rD: channel resistance
– CGS, CGD: parasitic capacitances
…
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Contents

1. Junction FET
2. Metal Oxide Semiconductor FET
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2 - Metal Oxide Semiconductor FET

 Structure and basic operation

 Characteristic curves of MOSFET
 Shockley equation and transconductance
 MOSFET biasing
 Parameters and datasheets
 Complementary MOS
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2.1 Structure and basic operation
 MOSFET = Metal Oxide Semiconductor FET
 Differences from JFET: instead a P-N junction, G
(metal) is isolated from the channel
(semiconductor) by a layer of insulator (oxide).
In some case, G is non-metallic  the FET is
called IGFET (Insulated-Gate FET)
 MOSFET has 2 major type:
– Enhancement-mode MOSFET (E-MOSFET): there is
no conduction channel between D-S when UGS = 0.
– Depletion-mode MOSFET (D-MOSFET): there is a
thin conduction channel between D-S when UGS = 0
 D-MOSFET conducts current when UGS = 0
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2.1 Structure and basic operation
 E-MOSFET:
– Constructed by:
• Gate: a metal layer
• Isolation layer: SiO2, very thin,
isolate G from channel.
• D and S: N-type (or P-type)
semiconductor, doped on
substrate.
• Substrate (or Body): P-type (or
N-type) semiconductor.
– N-channel E-MOSFET has the
P-type substrate, and vice
versa.
– E-MOSFET only operates in
enhancement-mode N-channel
E-MOSFET
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2.1 Structure and basic operation

 E-MOSFET:

Actual E-MOSFETs:
Symbol IRF540 (N-channel) and
IRF9540 (P-channel)

B and S is
connected
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2.1 Structure and basic operation

 D-MOSFET:
– Differences from E-MOSFET: there is a conduction
channel between D and S
– D-MOSFET can operate in both enhancement-
mode and depletion-mode

N-channel P-channel
D-MOSFET D-MOSFET
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2.1 Structure and basic operation

 D-MOSFET:

Actual D-MOSFET:
Symbol IXTP01N100D
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2.1 Structure and basic operation
 For proper operation, MOSFET need to be biased.
 For N-channel E-MOSFET: UGS > 0
– A positive gate voltage (above a threshold value) induces
a channel by creating a thin layer of negative charges in
the substrate region adjacent to the SiO2 layer
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2.1 Structure and basic operation

 N-channel E-MOSFET :
– When UDS increases, the
channel becomes smaller.
– The channel is pinched-
off when UDS is high
enough  ID is saturated
– The higher UGS  the
thicker channel  the
larger ID  UGS can
control the saturation
value of ID
– IDSS is the leakage current
 very small
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2.1 Structure and basic operation

 For N-channel D-MOSFET : UGS can be <, =, > 0

Depletion-mode Enhancement-
(commonly used) mode
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2.1 Structure and basic operation
 N-channel D-MOSFET :
– The narrow channel connects D and S  the operation is similar
to JFET and the E-MOSFET in which the channel is induced 
• When UDS increases, the channel becomes smaller.
• The channel is pinched-off when UDS is high enough  ID is saturated
• The higher UGS  the thicker channel  the larger ID
 UGS can control the saturation value of ID.

– Operation mode:
• Enhancement: UGS > 0  channel becomes thicker  ID(max) > IDSS
• UGS = 0  ID(max) = IDSS
• Depletion: UGS < 0  channel becomes thinner  ID(max) < IDSS
– Similar to JFET, when UGS = UGS(off)  the channel is totally
depleted and ID = 0 regardless the value of UDS
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2.2 Characteristic curves of MOSFET

 There are 2 important characteristic curves:

– Family of drain characteristic curves: present the
relation between ID and UDS at different values of UGS.

– Transfer characteristic: presents the relation between

UGS and ID (UGS controls ID).

 Predictions: the characteristic curves of JFET, E-

MOSFET, and D-MOSFET:
– Have similar shapes because of the same basic
operating mechanism.
– Have different positions in the coordinate system.
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2.2 Characteristic curves of MOSFET

 E-MOSFET:

Transfer Drain
characteristic characteristic
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2.2 Characteristic curves of MOSFET

 D-MOSFET

Transfer Drain
characteristic characteristic
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2.3 Shockley equation and transconductance

 Shockley equation for D-MOSFET (for both

depletion-mode and enhancement-mode):
2
 UGS 
ID  IDSS  1  
 U
 GS ( off ) 

• ID: Drain current

• IDSS: Saturated drain current when UGS = 0
• UP = −UGS(off): pinch-off voltage
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2.3 Shockley equation and transconductance

 E-MOSFET: (on)

2
ID  k UGS  UT  (on)

• ID: Drain current (on)

• UT: threshold voltage (on)

UT
• k: a constant, depends
on the particular (on)
MOSFET.
k can be calculated by
taking the specified
value of ID, called ID(on), ID (on)
at the given value of UGS.
k 2
UGS ( on )  UT 
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2.4 MOSFET biasing
 There are 4 types of bias:
– Fixed-bias
– Self-bias (not for E-MOSFET)
– Voltage-divider bias
– Drain-feedback bias (not for D-MOSFET in
enhancement-mode)

 In each type, we must consider:

– Position of the Q-point.
– The stability of the Q-point when parameters (IDSS,
UP, gm) of FETs vary.
– A good bias circuit: IDQ is highly stable
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2.4 MOSFET biasing
 Fixed-bias:
– Q-point determination: easily (see JFET)

+EDS

RD
N-channel
D-MOSFET D
N-channel
G E-MOSFET

RG S
UGS
EGS
EGS must
EGS can be
be ≥ UT
<, =, > 0
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2.4 MOSFET biasing

 Fixed-bias:
– Q-point can be determined by using the transfer
characteristic.
ID ID

N-channel
D-MOSFET N-channel
Q IDQ Q E-MOSFET
IDQ

UGS UGS
UP UGSQ = EGS UT UGSQ = EGS
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2.4 MOSFET biasing
+EDS
 Self-bias:
ID RD
– Not applicable for E-MOSFET
D
• VG = 0 (because IG = 0)
• VS = IS.RS = ID.RS
G
 UGS = − ID.RS
• Combined with the Shockley S
equation  a quadratic equation of UGS
RG
UGS  there are 2 solutions  RS
choose |UGS| < |UP| IS

 UDSQ = EDS – IDQ.(RD + RS)

 Q(UGSQ, IDQ, UDSQ)
N-channel
D-MOSFET
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2.4 MOSFET biasing

 Self-bias:
– Q-point determination using transfer characteristic.

ID

Q is the intersection of the

transfer characteristic curve and IDSS
the line UGS = − ID.RS
Q IDQ

UGS
UP UGSQ
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2.4 MOSFET biasing

 Voltage-divider bias:

+EDS +EDS

ID RD ID RD
N-channel R1 R1
D-MOSFET D D N-channel
E-MOSFET

IP G IP G
S S
UGS UGS
R2 R2
RS RS
IS IS
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2.4 MOSFET biasing
 Voltage-divider bias:
• VG = EDS.R2/(R1 + R2) (because IG = 0)
• VS = IS.RS = ID.RS
 UGS = VG – ID.RS
• In case of D-MOSFET: see JFET
• In case of E-MOSFET:
ID = k.(UGS – UT)2 combined with UGS = VG – ID.RS  a quadratic
equation of UGS  there are 2 solutions  choose |UGS| < |UP|

 UDSQ = EDS – IDQ.(RD + RS)

 Q(UGSQ, IDQ, UDSQ)

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2.4 MOSFET biasing

 Voltage-divider bias:
– Q-point determination using transfer characteristic.
ID ID

IDSS

Q IDQ
IDQ Q

UGS UGS
UP UGSQ UG UT UGSQ UG

Q is the intersection of the transfer characteristic

curve and the line UGS = VG − ID.RS
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2.4 MOSFET biasing

 Drain-feedback bias: +EDS

– Not applicable for D-MOSFET in ID RD
depletion-mode.
D
– E-MOSFET:
• VG = VD (because IG = 0) RG
 UGS = UDS = EDS – ID.RD
• ID = k.(UGS – UT)2  combined with G
UGS = EDS – ID.RD  a quadratic
equation of UGS  there are 2 UGS
solutions  choose |UGS| < |UP| S

 Q(UGSQ, IDQ, UDSQ)

N-channel
E-MOSFET
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2.4 MOSFET biasing

 Drain-feedback bias:
– Q-point determination using transfer characteristic.

ID

Q is the intersection of the

transfer characteristic curve and
the line UGS = EDS – ID.RD
IDQ Q

UGS
UGSQ EDS
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2.4 MOSFET biasing

Voltage-divider Drain-feedback
Fixed-bias Self-bias
bias bias
+EDS +EDS

RD
ID RD
D
+EDS R1
D +EDS
G
ID RD IP G ID RD
RG S D S
UGS
R2
UGS D
EGS RS
G IS D-MF RG
D-MF
S
+EDS UGS +EDS G
RG
RD RS
E-MF E-MF ID RD
D IS R1 UGS
D S
G
IP G
RG S
UGS S
UGS
EGS R2
RS
D-MF IS E-MF
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2.5 - Parameters and datasheets
 Similar to the other semiconductor components,
MOSFET has some maximum rating: ID(max),
UDS(max), UGS(max), PD(max), …
 Dedicated parameters:
– gm: transconductance
– ID(on), RDS(on): drain current and channel resistance (in a
specific condition).
– CGS, CGD: parasitic capacitances
E-MOSFET D-MOSFET
UT: threshold voltage UGS(off): channel cutoff voltage

IDSS: saturated ID when UGS = 0

Note: Static electricity applied to the gate of MOSFET can destroy gate oxide layer
 MOSFET needs to be handled with care
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2.6 Complementary MOS
 Complementary MOS = CMOS = combination
among N-channel and P-channel E-MOSFETs.
 Advantages: low power consumption, high-speed
switching, high-density, high most commonly-used
technology for digital ICs.
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Summary

 Studied
– Junction FET (JFET)
– Metal Oxide Semiconductor FET (MOSFET)

 Important, for GPA & CPA enhancement

– Structure, basic operation, curves of FETs
– Shockley equations
– Bias circuits, Q-point determination
 III.63/63

Lecturer: Dr. Đào Việt Hùng

Department of Electronics
School of Electrical and Electronic Engineering
Hanoi University of Science and Technology
Email: hunget.bk@gmail.com