BIS-AV-0417-0611 wen [TT TT TTT) Time : 3 Hours @) () © @ (©) © (@) (h) @ @ (@) (b) CS 15-1403 COMPUTER ARCHITECTURE AND ORGANISATION (2015 Scheme) PART A (Answer ALL questions) Le Wech. Degree IV Semester Examination April 2017 Maximum Marks : 60 (10x 2= 20) List the steps needed to perform the execution of the machine instruction STORE RI, LOC. What are the condition code flags available? How do they help in detecting anomalies in results? What is the principle of operation of Carry Look ahead adders? Calculate the maximum delay experienced when four 4-bit adders are cascaded to form a 16 bit adder in carry look ahead fashion, What are the relative merits and demerits of horizontal and vertical micro instruction formats? Explain the LRU replacement strategy and its implementation. What is the role of TLB in a virtual memory system? What are the different ways available to enable and disable interrupts? Discuss the system of device identification followed in vectored interrupt system. A computer system has main memory consisting of IM words. It also has a 4K work cache organized in the block set associative manner, with 4 blocks per set and 64 words per block. (i) How many bits are there in main memory address? Gi) Calculate the number of bits in each of TAG, SET and WORD fields of the main memory address format, Differentiate between the features of asynchronous and synchronous DRAMS. PART B (4 10=40) A list of student marks which contains j test scores for each student along with student id, Assume there are n students. Write an assembly language program for computing the sums of scores on each test and store these sums in the memory locations SUM, SUM#4, SUM+8 ete. Explain how parameter passing is achieved using stack. What is the role of Frame Pointer (FP) in it? oR 6) GS) (P-1.0,)UL IV. VI Vil. VIL Ix, (a) (b) () @ (b) @ (b) (a) (b) (a) (b) (a) (b) (a) (b) Register RI and R2 of a computer contain the decimal values 1200 and 4600 respectively. What is the effective address of the memory operand in each of the following instructions? (i), LOAD 20 (RI), RS (ii) STORE RS, 30 (RI, R2) Gili) ADD-(R2), RS (iv) SUB (RI)+.RS Implement the high level language statement C=A+B using different instruction formats. What are the two schemes followed for byte addressability? With the help of a block diagram, explain the microinstruction sequencing, with next address field. How is Bit-Oring effectively used there? Write the control sequence steps required for executing the following instruction in single bus structure of CPU. OR Multiply the following signed 2’s complement numbers using booth’s algorithm. Multiplicand = 110101 and Multiplier = 011011. How does bit pair recording make the multiplication faster? With the help of a block diagram, explain restoring division method. What is the modification for non restoring? What is meant by locality of reference? Explain the various mapping functions used in cache implementation. Draw and explain the internal organization of a 2MX8 DRAM chip. OR How does the address translation mechanism work in a virtual memory system? Explain the working of a Static RAM (SRAM) cell. How are the read and write operations implemented? How is an ISR different from an ordinary subroutine execution? How is the processor handling the problem of simultaneous requests and interrupt nesting? OR Draw the block diagram and explain how a typical serial port works. What is the need of bus arbitration in DMA? Differentiate between centralized and distributed bus arbitration, (4) @) GB) (5) (6) (6) (5) (5) (5) (5) G) GB) a a) (6)