APW7120A

5V to 12V Supply Voltage, 8-PIN, Synchronous Buck PWM Controller

Features General Description

• Operating with Single 5~12V Supply Voltage or The APW7120A is a fixed 300kHz frequency, voltage mode,
Two Supply Voltages and synchronous PWM controller. The device drives two
• Drive Dual Low Cost N-Channel MOSFETs low cost N-channel MOSFETs and is designed to work
with single 5~12V or two supply voltage(s), providing ex-
- Adaptive Shoot-Through Protection
cellent regulation for load transients.
• Built-in Feedback Compensation
The APW7120A integrates controls, monitoring and pro-
- Voltage-Mode PWM Control
tection functions into a single 8-pin package to provide a
- 0~100% Duty Ratio low cost and perfect power solution.
- Fast Transient Response A power-on-reset (POR) circuit monitors the VCC supply
• ±2% 0.8V Reference voltage to prevent wrong logic controls. An internal 0.8V
- Over Line, Load Regulation, and Operating reference provides low output voltage down to 0.8V for
Temperature further applications. An built-in digital soft-start with fixed
• Programmable Over-Current Protection soft-start interval prevents the output voltage from over-
shoot as well as limiting the input current. The controller’s
- Using RDS(ON) of Low-Side MOSFET
over-current protection monitors the output current by
• Hiccup-Mode Under-Voltage Protection
using the voltage drop across the low-side MOSFET’s
• 118% Over-Voltage Protection
RDS(ON), eliminating the need of a current sensing resistor.
• Adjustable Output Voltage Additional under voltage and over voltage protections
• Small Converter Size monitor the voltage on FB pin for short-circuit and over-
- 300kHz Constant Switching Frequency voltage protections. The over-current protection cycles the
- Small SOP-8 Package soft-start function until 4 over-current events are counted.
• Built-In Digital Soft-Start Pulling and holding the voltage on OCSET pin below
• Shutdown Control Using an External MOSFET 0.15V with an open drain device shuts down the controller.

• Lead Free and Green Devices Available

(RoHS Compliant) Pin Cinfiguration

Applications BOOT 1 8 PHASE

UGATE 2 7 OCSET
• Motherboard GND 3 6 FB

• Graphics Card
LGATE 4 5 VCC

• High Current, Up to 20A, DC-DC Converters

SOP-8
(Top View)

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.

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Rev. A.3 - Nov., 2009
APW7120A

Ordering and Marking Information

APW7120A Package Code

K : SOP-8
Assembly Material Operating Ambient Temperature Range
Handling Code E : -20 to 70 oC
Handling Code
Temperature Range TR : Tape & Reel
Package Code Assembly Material
G : Halogen and Lead Free Device

APW7120A XXXXX - Date Code

APW7120A K : XXXXX

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).

Absolute Maximum Ratings (Note 1)

Symbol Parameter Rating Unit

VCC VCC Supply Voltage (VCC to GND) -0.3 ~ 16 V
VBOOT BOOT Voltage (BOOT to PHASE) -0.3 ~ 16 V
UGATE Voltage (UGATE to PHASE)
<400ns pulse width -5 ~ VBOOT+0.3 V
>400ns pulse width -0.3 ~ VBOOT+0.3
LGATE Voltage (LGATE to GND)
<400ns pulse width -5 ~ VCC+0.3 V
>400ns pulse width -0.3 ~ VCC+0.3
PHASE Voltage (PHASE to GND)
<400ns pulse width -10 ~ 30 V
>400ns pulse width -3 ~ 16
VI/O Input Voltage (OCSET, FB to GND) -0.3 ~ 7 V
o
Maximum Junction Temperature 150 C
o
TSTG Storage Temperature -65 ~ 150 C
o
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 C
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

Thermal Characteristics
Symbol Parameter Typical Value Unit
(Note 2)
Junction-to-Ambient Resistance in Free Air
θJA
o
160 C/W
SOP-8
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.

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APW7120A

Recommended Operating Conditions (Note 3)

Symbol Parameter Range Unit
VCC VCC Supply Voltage 4.5 ~ 13.2 V
VOUT Converter Output Voltage 0.8 ~ 70%VIN V
VIN Converter Input Voltage 2.2 ~ 13.2 V
IOUT Converter Output Current 0 ~ 20 A
o
TA Ambient Temperature -20 ~ 70 C
o
TJ Junction Temperature -20 ~ 125 C
Note 3: Please refer to the typical application circuit.

Electrical Characteristics
Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V and TA = -20 ~ 70oC. Typical values
are at TA = 25oC.

APW7120A
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
SUPPLY CURRENT
IVCC VCC Nominal Supply Current UGATE and LGATE Open - 2.1 6 mA
VCC Shutdown Supply Current - 1.5 4 mA
POWER-ON-RESET
Rising VCC Threshold 3.8 4.1 4.4 V
Hysteresis 0.1 0.45 0.6 V
OSCILLATOR
FOSC Free Running Frequency 250 300 350 kHz
∆VOSC Ramp Amplitude - 1.5 - VP-P
REFERENCE VOLTAGE
VREF Reference Voltage Measured at FB Pin - 0.8 - V
Accuracy TA =-20~70°C -2.0 - +2.0 %
Line Regulation VCC=12 ~ 5V - 0.05 0.5 %
ERROR AMPLIFIER
DC Gain - 86 - dB
FP1 First Pole Frequency - 0.4 - Hz
FZ Zero Frequency - 0.4 - kHz
FP2 Second Pole Frequency - 430 - kHz
Average UGATE Duty Range 0 - 70 %
FB Input Current - - 0.1 µA
PWM CONTROLLER GATE DRIVERS
UGATE Source VBOOT-PHASE =12V, VUGATE-PHASE =6V 1.0 2.0 - A
UGATE Sink VBOOT-PHASE =12V, VUGATE-PHASE=1V - 3.5 7 Ω
LGATE Source VCC=12V, VLGATE=6V 1.0 1.9 - A
LGATE Sink VCC=12V, VLGATE=1V - 2.6 5 Ω
TD Dead-Time Guaranteed by Design - 40 100 ns

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APW7120A

Electrical Characteristics (Cont.)

Unless otherswise specified, these specifications apply over VCC = 12V, VBOOT = 12V and TA = -20 ~ 70oC. Typical values
are at TA = 25oC.

APW7120A
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
PROTECTIONS
IOCSET OCSET Current Source VPHASE=0V, Normal Operation 35 40 45 µA
Over-Current Reference Voltage TA =-20~70°C 0.37 0.4 0.43 V
UVFB FB Under-Voltage Threshold VFB Falling 62 67 72 %
FB Under-Voltage Hysteresis - 45 - mV
Over-Voltage Threshold VFB Rising 114 118 122 %
SOFT-START AND SHUTDOWN
TSS Soft-Start Interval 2 3.8 5 ms
OCSET Shutdown Threshold Falling VOCSET 0.1 0.15 0.3 V
OCSET Shutdown Hysteresis - 40 - mV

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APW7120A

Typical Operating Characteristics

Reference Voltage vs. Junction Switching Frequency vs. Junction

Temperature Temperature
0.812 350
0.810 340

Switching Frequency, FOSC (kHz)

Reference Voltage, VREF (V)

0.808 330
0.806
320
0.804
0.802 310
0.800 300
0.798 290
0.796 280
0.794
270
0.792
0.790 260
0.788 250
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (oC) Junction Temperature (oC)

VCC POR Threshold Voltage vs.

OCSET Current vs. Junction Temperature
Junction Temperature
45 4.4
4.3
VCC POR Threshold Voltage (V)

44
OCSET Current, IOCSET (µA)

43 4.2 Rising VCC

42 4.1
41 4.0
40 3.9
39 3.8
38 3.7 Falling VCC

37 3.6
36 3.5
35 3.4
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Junction Temperature (oC) Junction Temperature (oC)
OCSET Shutdown Threshold Voltage
vs. Junction Temperature
OCSET Shutdown Threshold Voltage (V)

0.20
Falling VOCSET

0.18

0.16

0.14

0.12

0.10
-50 -25 0 25 50 75 100 125 150
Junction Temperature (oC)

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APW7120A

Operating Waveforms
(Refer to the typical application circuit, VBAIS=VIN=+12V supplied by an ATX Power Supply)

1. Load Transient Response : IOUT = 0A -> 15A -> 0A

- IOUT slew rate = ±7.5A/µs

IOUT = 0A -> 15A IOUT = 0A -> 15A -> 0A IOUT = 15A -> 0A

VOUT=1.8V VOUT
VOUT
1 1 1
VOUT

VUGATE VUGATE VUGATE

3 3 3
15A
IOUT
IOUT IOUT
0A
2 2 2

Ch1 : VOUT, 100mV/Div, AC, Ch1 : VOUT, 100mV/Div, AC, Ch1 : VOUT, 100mV/Div, AC,
Ch2 : IOUT, 10A/Div Ch2 : IOUT, 10A/Div Ch2 : IOUT, 10A/Div
Ch3 : VUGATE, 20V/Div, DC Ch3 : VUGATE, 20V/Div, DC Ch3 : VUGATE, 20V/Div, DC
Time : 5µs/Div Time : 40µs/Div Time : 5µs/Div
BW = 20 MHz BW = 20 MHz BW = 20 MHz

2. UGATE and LGATE Switching Waveforms

Rising VUGATE Falling VUGATE

IOUT = 15A
VLGATE
VLGATE VUGATE
VUGATE

1,2 1,2

Ch1 : VUGATE, 5V/Div, DC Ch2 : VLGATE, 2V/Div, DC Ch1 : VUGATE, 5V/Div, DC Ch2 : VLGATE, 2V/Div, DC
Time : 20ns/Div BW = 500 MHz Time : 20ns/Div BW = 500 MHz

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APW7120A

Operating Waveforms (Cont.)

(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply)

3. Powering ON / OFF

Powering ON Powering OFF

VCC=VIN=5V VCC=VIN=5V
RL=0.12Ω VCC VCC RL=0.12Ω

1 1

IL
IL
3 3
VOUT

VOUT
2 2

Ch1 : VCC, 2V/Div, DC Ch2 : VOUT, 1V/Div, DC Ch1 : VCC, 2V/Div, DC Ch2 : VOUT, 1V/Div, DC
Ch3 : IL, 10A/Div, DC Time : 5ms/Div Ch3 : IL, 10A/Div, DC Time : 10ms/Div
BW = 20 MHz
BW = 20 MHz

Powering ON Powering OFF

VCC=VIN=12V VCC=VIN=12V
RL=0.12Ω VCC RL=0.12Ω
VCC

1
1

IL
IL
3 3
VOUT

VOUT
2 2

Ch1 : VCC, 5V/Div, DC Ch2 : VOUT, 1V/Div, DC Ch1 : VCC, 5V/Div, DC Ch2 : VOUT, 1V/Div, DC
Ch3 : IL, 10A/Div, DC Time : 5ms/Div Ch3 : IL, 10A/Div, DC Time : 10ms/Div
BW = 20 MHz BW = 20 MHz

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Rev. A.3 - Nov., 2009
APW7120A

Operating Waveforms (Cont.)

(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply)

4. Enabling and Shutting Down

Enabling by Releasing OCSET Pin Shutting Down by Pulling OCSET Low

VOCSET
3 VOCSET 3

2 VUGATE
2
VUGATE

VOUT

1 1 VOUT
IOUT=2A

Ch1 : VOUT, 1V/Div, DC Ch2 : VUGATE, 20V/Div, DC Ch1 : VOUT, 1V/Div, DC Ch2 : VUGATE, 20V/Div, DC
Ch3 : VOCSET, 2V/Div, DC Time : 2ms/Div Ch3 : VOCSET, 2V/Div, DC Time : 2ms/Div
BW = 20 MHz BW = 20 MHz

5. Over-Current Protection

No Connecting a shutdown MOSFET Connecting a shutdown MOSFET

at OCSET Pin (2N7002) at OCSET Pin

ROCSET=15k ROCSET=15k
APM2512 APM2512

VOUT VOUT
1 1

IL 2
IL
2

Ch1 : VOUT, 1V/Div, DC Ch2 : IL, 10A/Div, DC Ch1 : VOUT, 1V/Div, DC Ch2 : IL, 10A/Div, DC
Time : 5ms/Div BW = 20 MHz Time : 5ms/Div BW = 20 MHz

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Rev. A.3 - Nov., 2009
APW7120A

Operating Waveforms (Cont.)

(Refer to the typical application circuit, VBIAS=VIN=+12V supplied by an ATX Power Supply)

6. OCSET Voltage RC Delay

No Connecting a shutdown MOSFET Connecting a shutdown MOSFET

at OCSET Pin (2N7002) at OCSET Pin

VOCSET VOCSET

IL IL

1,2 OCP 1,2 CProber=8pF OCP

CProber=8pF C2N7002=44pF (measured)

Ch1 : VOCSET, 0.5V/Div, DC Ch2 : IL, 10A/Div, DC Ch1 : VOCSET, 0.5V/Div, DC Ch2 : IL, 10A/Div, DC
Time : 2µS/Div BW = 20 MHz Time : 2µ S/Div BW = 20 MHz

6. OCSET Voltage RC Delay 7. Short-Circuit Test

Connecting a shutdown MOSFET

(APM2322) at OCSET Pin

Shorted by a wire

IL OCP OCP OCP OCP

VOUT
1
UVP

VOCSET
IL
1,2 CProber=8pF OCP 2
CAPM2322 =89pF (measured)

Ch1 : VOCSET, 0.5V/Div, DC Ch2 : IL, 10A/Div, DC Ch1 : VOUT, 1V/Div, DC Ch2 : IL, 10A/Div, DC
Time : 2µS/Div BW = 20 MHz Time : 5ms/Div BW = 20 MHz

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APW7120A

Pin Description
PIN
FUNCTION
NO. NAME
This pin provides ground referenced bias voltage to the high-side MOSFET driver. A bootstrap circuit with
1 BOOT
a diode connected to 5~12V is used to create a voltage suitable to drive a logic-level N-channel MOSFET.
Connect this pin to the high-side N-channel MOSFET gate. This pin provides gate drive for the high-side
2 UGATE
MOSFET.
The GND terminal provides return path for the IC bias current and the low-side MOSFET driver pull-low
3 GND
current. Connect the pin to the system ground via very low impedance layout on PCBs.
Connect this pin to the low-side N-channel MOSFET gate. This pin provides gate drive for the low-side
4 LGATE
MOSFET.
Connect this pin to a 5~12V supply voltage. This pin provides bias supply for the control circuitry and the
5 VCC
low-side MOSFET driver. The voltage at this pin is monitored for the Power-On-Reset (POR) purpose.
This pin is the inverting input of the internal Gm amplifier. Connect this pin to the output (VOUT) of the
converter via an external resistor divider for closed-loop operation. The output voltage set by the resistor
divider is determined using the following formula:
6 FB R1
VOUT = 0.8V ⋅ ( 1 + ) (V)
R2
where R1 is the resistor connected from VOUT to FB , and R2 is the resistor connected from FB to GND.
The FB pin is also monitored for under and over-voltage events.
The OCSET is a dual-function input pin for over-current protection and shutdown control. Connect a
resistor (ROCSET) from this pin to the Drain of the low-side MOSFET. This resistor, an internal 40µA current
source (IOCSET), and the MOSFET on-resistance (RDSON) set the converter over-current trip level (IPEAK)
according to the following formula:
7 OCSET 40µA ⋅ ROCSET - 0.4V
IPEAK = (A)
RDSON
Pulling and holding this pin below 0.15V with an open drain device, with very low parasitic capacitor, shuts
down the IC with floating output and also resets the over-current counter. Releasing OCSET pin initiates a
new soft-start and the converter works again.
The pin provides return path for the high-side MOSFET driver pull-low current. Connect this pin to the
8 PHASE
high-side MOSFET source.

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APW7120A

Block Diagram
VCC

3VCC

40µA

Regulator
Power-On- OCSET
Reset
OC 0.4V
2.5V
POR Enable
3VCC
67%VREF Soft-Start 0.15V
UV
and Fault
BOOT
Logic
OV
UGATE
118%VREF

Soft-Start Inhibit
PHASE
Gate
Control
FB COMP
PWM VCC

Gm
VREF Amplifier LGATE
0.8V
FOSC
300kHz
Oscillator GND

Typical Application Circuit

D1 L1
1µH
VBIAS 1N4148
+5V/12V VIN
C5 C3, C4 +5/12V
1µF 820µF x2
C2
1 0.1µF
BOOT
R4 2
Q1
UGATE APM2512
2.2
8
5 PHASE VOUT
VCC L2
C1 R5 1.5µH C6, C7
1.8V/15A
1µF 7
U1 OCSET 1000µF x2
APW7120A Q2
6 4
FB LGATE APM2512
GND

3 R1
1.5k

R2
Q3 1.2k
2N7002 R3
Shutdown C8
0.1µF 200

C3, C4 : 820µF/16V , ESR=25mΩ

C6, C7 : 1000µF/6.3V, ESR=30mΩ

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APW7120A

Function Description
Power-On-Reset (POR) at low operating duty, but very much at high operating
The APW7120A monitors the VCC voltage (VCC) for Power- duty, like the RC delay curve. Due to load regulation or
On-Reset function, preventing wrong logic operation dur- current-limit, heavy load normally reduces converter’s
ing powering on. When the VCC voltage is ready, the input voltage and increases the power loses. During heavy
APW7120A starts a start-up process and then ramps the load, the APW7120A regulates the output voltage by ex-
output voltage up to the target voltage. pending the duty. This rises up the OCP trip level at the
same time.
Soft-Start
Under-Voltage Protection (UVP)
The APW7120A has a built-in digital soft-start to control
The under-voltage function monitors the FB voltage (VFB)
the output voltage rise and limit the current surge at the
to protect the converter against short-circuit conditions.
start-up. During soft-start, an internal ramp connected to
When the VFB falls below the falling UVP threshold (67%
the one of the positive inputs of the Gm amplifier rises up
VREF), the APW7120A shuts off the converter. After a pre-
from 0V to 2V to replace the reference voltage (0.8V) until
ceding delay, which starts at the beginning of the under-
the ramp voltage reaches the reference voltage. The soft-
voltage shutdown, the APW7120A initiates a new soft-
start interval is about 3.2ms typical, independent of the
start to resume regulating. The under-voltage protection
converter’s input and output voltages.
shuts off and then re-starts the converter repeatedly with-
Over-Current Protection (OCP) out latching. The function is disabled during soft-start
The over-current function protects the switching converter process.
against over-current or short-circuit conditions. The con- Over-Voltage Protection (OVP)
troller senses the inductor current by detecting the drain-
The over-voltage protection monitors the FB voltage to
to-source voltage, product of the inductor’s current and
prevent the output from over-voltage. When the output
the on-resistance, of the low-side MOSFET during it’s on-
voltage rises to 118% of the nominal output voltage, the
state. This method enhances the converter’s efficiency
APW7120A turns on the low-side MOSFET until the out-
and reduces cost by eliminating a current sensing
put voltage falls below the OVP threshold, regulating the
resistor.
output voltage around the OVP thresholds.
A resistor (ROCSET), connected from the OCSET to the low-
side MOSFET’s drain, programs the over-current trip level. Adaptive Shoot-Through Protection
An internal 40µA (typical) current source flowing through
The gate driver incorporates adaptive shoot-through pro-
the ROCSET develops a voltage (VROCSET) across the ROCSET.
tection to high-side and low-side MOSFETs from con-
When the VOCSET (VROCSET+ VDS of the low-side MOSFET) is
ducting simultaneously and shorting the input supply. This
less than the internal over-current reference voltage (0.
is accomplished by ensuring the falling gate has turned
4V, typical), the IC shuts off the converter and then ini-
off one MOSFET before the other is allowed to rise.
tiates a new soft-start process. After 4 over-current events
During turn-off of the low-side MOSFET, the LGATE volt-
are counted, the device turns off both high-side and low-
age is monitored until it reaches a 1.5V threshold, at which
side MOSFETs and the converter’s output is latched to be
time the UGATE is released to rise after a constant delay.
floating.
During turn-off of the high-side MOSFET, the UGATE-to-
Please pay attention to the RC delay effect. It causes
PHASE voltage is also monitored until it reaches a 1.5V
the OCP trip level to be the function of the operating
threshold, at which time the LGATE is released to rise
duty. The parasitic capacitance (including the capacitance
after a constant delay.
inside the OCSET, external PCB trace capacitance and
the COSS of the shutdown MOSFET) must be minimized,
especially selecting a shutdown MOSFET with very small
COSS. The OCP trip level follows the duty to increase a little

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Rev. A.3 - Nov., 2009
APW7120A

Function Description (Cont.)

Shutdown Control

Pulling the OCSET voltage below 0.15V by an open drain

transistor, shown in typical application circuit, shuts down
the APW7120A PWM controller. In shutdown mode, the
UGATE and LGATE are pulled to PHASE and GND
respectively, the output is floating.

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Rev. A.3 - Nov., 2009
APW7120A

Application Information
Input Capacitor Selection T=1/FOSC

Use small ceramic capacitors for high frequency

decoupling and bulk capacitors to supply the surge cur- VUGATE
rent needed each time high-side MOSFET(Q1) turns on. DT I
IOUT
Place the small ceramic capacitors physically close to the
MOSFETs and between the drain of Q1 and the source of IL
low-side MOSFET(Q2).
IOUT
The important parameters for the bulk input capacitor are
IQ1
the voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and cur- I
ICOUT
rent ratings above the maximum input voltage and larg-
VOUT
est RMS current required by the circuit. The capacitor volt-
age rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times VOUT
is a conservative guideline. The RMS current of the bulk
input capacitor is calculated as the following equation : Figure 1. Buck Converter Waveforms

IRMS = IOUT ⋅ D ⋅ (1- D) (A) Output Capacitor Selection

For a through hole design, several electrolytic capacitors An output capacitor is required to filter the output and sup-
may be needed. For surface mount designs, solid tanta- ply the load transient current. The filtering requirements
lum capacitors can be used, but caution must be exer- are a function of the switching frequency and the ripple
cised with regard to the capacitor surge current rating. current. The output ripple is the sum of the voltages, hav-
ing phase shift, across the ESR and the ideal output
VIN
capacitor. The peak-to-peak voltage of the ESR is calcu-
IQ1 CIN
lated as the following equations :
Q1 VOUT = D ⋅ VIN (V) .......... . (1)
UGATE
IL IOUT
VOUT ⋅ (1 - D)
VOUT ∆I = (A) .......... .(2)
L FOSC ⋅ L
ESR VESR = ∆ I ⋅ ESR (V) .......... ..(3)
ICOUT
Q2 The peak-to-peak voltage of the ideal output capacitor is
LGATE
COUT
calculated as the following equation :
∆I
∆VCOUT = (V) ....... (4)
8 ⋅ FOSC ⋅ COUT

For general applications using bulk capacitors, the ∆VCOUT

is much smaller than the V ESR and can be ignored.
Therefore, the AC peak-to-peak output voltage is shown
below:
∆VOUT = ∆ I ⋅ ESR (V) ...........(5)

The load transient requirements are the function of the

slew rate (di/dt) and the magnitude of the transient load
current. These requirements are generally met with a
mix of capacitors and careful layout. Modern components
and loads are capable of producing transient load rates

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APW7120A

Application Information (Cont.)

Output Capacitor Selection (Cont.) tions give the approximate response time interval for ap-
plication and removal of a transient load:
above 1A/ns. High frequency capacitors initially supply
the transient and slow the current load rate seen by the L ⋅ ITRAN L ⋅ ITRAN
tRISE = , tFALL =
VIN − VOUT VOUT
bulk capacitors. The bulk filter capacitor values are gener-
ally determined by the ESR (Effective Series Resistance) where
and voltage rating requirements rather than actual ca- ITRAN is the transient load current step, tRISE is the response
pacitance requirements. time to the application of load, and tFALL is the response
High frequency decoupling capacitors should be placed time to the removal of load. The worst case response
as close to the power pins of the load as physically time can be either at the application or removal of load.
possible. Be careful not to add inductance in the circuit Be sure to check both of these equations at the transient
board wiring that could cancel the usefulness of these load current. These requirements are minimum and
low inductance components. maximum output levels for the worst case response time.
An aluminum electrolytic capacitor’s ESR value is related MOSFET Selection
to the case size with lower ESR available in larger case
In high-current applications, the MOSFET power
sizes. However, the Equivalent Series Inductance (ESL)
dissipation, package selection and heatsink are the domi-
of these capacitors increases with case size and can re-
nant design factors. The power dissipation includes two
duce the usefulness of the capacitor to high slew-rate
loss components, conduction loss and switching loss.
transient loading. In most cases, multiple electrolytic ca-
The conduction losses are the largest component of
pacitors of small case size perform better than a single
power dissipation for both the high-side and the low-side
large case capacitor.
MOSFETs. These losses are distributed between the two
Output Inductor Selection MOSFETs according to duty factor (see the equations
The output inductor is selected to meet the output voltage below). Only the high-side MOSFET has switching losses,
ripple requirements and minimize the converter’s re- since the low-side MOSFETs body diode or an external
sponse time to the load transient. The inductor value de- Schottky rectifier across the lower MOSFET clamps the
termines the converter’s ripple current and the ripple switching node before the synchronous rectifier turns on.
voltage, see equations (2) and (5). Increasing the value of These equations assume linear voltage-current transi-
inductance reduces the ripple current and voltage. tions and do not adequately model power loss due the
However, the large inductance values reduce the reverse-recovery of the low-side MOSFET’s body diode.
converter’s response time to a load transient. The gate-charge losses are dissipated by the APW7120A
One of the parameters limiting the converter’s response and don’t heat the MOSFETs. However, large gate-charge
to a load transient is the time required to change the in- increases the switching interval, tSW which increases the
ductor current. Given a sufficiently fast control loop design, high-side MOSFET switching losses. Ensure that both
the APW7120A will provide either 0% or 85%(Average) MOSFETs are within their maximum junction tempera-
duty cycle in response to a load transient. The response ture at high ambient temperature by calculating the tem-
time is the time required to slew the inductor current from perature rise according to package thermal-resistance
an initial current value to the transient current level. Dur- specifications. A separate heatsink may be necessary
ing this interval the difference between the inductor cur- depending upon MOSFET power, package type, ambient
rent and the transient current level must be supplied by temperature and air flow.
1
the output capacitor. Minimizing the response time can PHigh - Side = IOUT 2 ⋅ RDSON ⋅ D + ⋅ IOUT ⋅ VIN ⋅ tSW ⋅ FOSC
2
minimize the output capacitance required. PLow - Side = IOUT 2 ⋅ RDSON ⋅ (1 - D)
The response time to a transient is different for the appli- Where
cation of load and the removal of load. The following equa- tSW is the switching interval

Copyright  ANPEC Electronics Corp. 15 www.anpec.com.tw

Rev. A.3 - Nov., 2009
APW7120A

Application Information (Cont.)

Feedback Compensation quencies of the A1(S), A2(S), A3(S), and ACL(S) are shown
or calculated as the following equations:
The figure 2 shows the control system of the APW7120,
which consists of an internal voltage-mode PW M FZA21 = 0.4kHz (FZ)
modulator, an output L-C filter, a resistor-divider and an FPA21 = 430kHz (FP2)
internal compensation network. The R and C are the 1
F PA41,2 =
equivalent series resistance (ESR) and capacitance of 2 π x LC
the output capacitor; the L is the inductance of the output
1
inductor. F ZA41 =
2 π xRxC
VIN
where the FPA21 (or FP2) and FZA21 (or Fz) are the Pole and
Zero frequencies of the A2(S), the FPA41,2 and FZA41 are the
APW7120
UGATE
double-Pole and Zero frequencies of the A4(S), the VIN is
VOSC=1.6V L VOUT
VPHASE the input voltage of the PWM converter and the load resis-
tance of the converter is very large. For good converter
Driver R VO
stability, the values of the L, C, and R must be selected to
LGATE
C meet the following criteria:
VCOMP VFB 1. Make sure the double-pole frequency (FPA41,2) of the
FB R1
output filter is bigger than the zero frequency (FZA21) of
Internal the internal compensation network.
Compensation R2
Network 0.8V 2. The following equation must be true:
VIN R2 1 L
log( ) + log( ) − 2 ⋅ log( ⋅ ) + 1.2 > 0
∆VOSC R1 + R2 R C
Figure 2. APW7120 Control System 3. The converter crossover frequency (FCO) must be in the
range of 10%~30% of minimum FOSC of the converter.
The transfer functions are defined as following: The FCO is calculated by using the following equations:
VFB(S) R2
A1(S) = =  Gain at FZA41 
VO(S) R1 + R2 10% FOSC_MIN ≤  FCO = 10 20 ⋅ FZA41 ≤ 30% FOSC_MIN
 
A2(S) =
VCOMP(S)
(Internal Compensation)  
VFB(S) VIN R2
Gain at FZA41 = 20 ⋅ log( ) + 20 ⋅ log( )
VPHASE(S) VIN ∆VOSC R1 + R2
A3(S) = =
VCOMP(S) ∆VOSC 1 L
VOUT(S) R ⋅C⋅S +1 − 40 ⋅ log( ⋅ ) + 27
A4(S) = = R C
VPHASE(S) L ⋅ C ⋅ S2 + R ⋅ C ⋅ S + 1
4. The values of L, C, and R selected must meet the
VOUT(S)
ACL(S) = equations above over the operaing temperature,
VO(S)
VFB(S) VCOMP(S) VPHASE(S) VOUT (S) voltage, and current ranges.
= ⋅ ⋅ ⋅
VO(S) VFB(S) VCOMP(S) VPHASE(S)
= A1(S) ⋅ A2(S) ⋅ A3(S) ⋅ A4(S)

where A1(S) is the transfer function of the resistor-divider,

A2(S) is the transfer function of the feedback compensa-
tion network, A3(S) is the transfer function of the PWM
modulator, A4(S) is the transfer function of the output LC
filter, and ACL(S) is the transfer function of the closed-loop
control system. Refer to figure 3. The Pole and Zero fre-

Copyright  ANPEC Electronics Corp. 16 www.anpec.com.tw

Rev. A.3 - Nov., 2009
APW7120A

Application Information (Cont.)

Feedback Compensation (Cont.) 6. Keep the switching nodes (UGATE, LGATE, and PHASE)
away from sensitive small signal nodes since these
100
nodes are fast moving signals. Therefore, keep traces
80
to these nodes as short as possible.
60
FZA21 7. Place the decoupling ceramic capacitor CHF near the
Compensation Gain
40 Drain of the high-side MOSFET as close as possible.
Gain (dB)

20 The bulk capacitors CIN are also placed near the Drain.
FPA21
0 Converter Gain 8. Place the Source of the high-side MOSFET and the
FPA41,2 FCO
-20 FZA41
Drain of the low-side MOSFET as close as possible.
-40 Minimizing the impedance with wide layout plane be-
PWM &Filter Gain tween the two pads reduces the voltage bounce of the
-60
100 1K 10K 100K 1M 10M node.
Frequency (f, Hz)
9. Use a wide power ground plane, with low impedance,
Figure 3. Converter Gain vs. Frequency to connects the CHF, CIN, COUT, Schottky diode and the
Source of the low-side MOSFET to provide a low im-
Layout Consideration pedance path between the components for large and
In high power switching regulator, a correct layout is im- high frequency switching currents.
portant to ensure proper operation of the regulator.
VIN
In general, interconnecting impedances should be mini- CHF
mized by using short, wide printed circuit traces. Signal
and power grounds are to be kept separate and finally 5 CIN
VCC
combined using ground plane construction or single point
+
grounding. Figure 4 illustrates the layout, with bold lines 1
BOOT
indicating high current paths. Components along the bold
4
lines should be placed close together. Below is a check- LGATE
list for your layout: APW7120A
U 2 COUT
1. Begin the layout by placing the power components first. 1 UGATE Q1 Q2 +
Orient the power circuitry to chieve a clean power flow
PHASE 8
path. If possible, make all the connections on one side L1 VOUT
of the PCB with wide, copper filled areas.
2. Connect the ground of feedback divider directly to the Figure 4. Recommended Layout Digram
GND pin of the IC using a dedicated ground trace.
3. The VCC decoupling capacitor should be right next to
the VCC and GND pins. Capacitor CBOOT should be con-
nected as close to the BOOT and PHASE pins as
possible.
4. Minimize the length and increase the width of the trace
between UGATE/LGATE and the gates of the MOSFETs
to reduce the impedance driving the MOSFETs.
5. Use an dedicated trace to connect the ROCSET and the
Drain pad of the low-side MOSFET, Kevin connection,
for accurate current sensing.

Copyright  ANPEC Electronics Corp. 17 www.anpec.com.tw

Rev. A.3 - Nov., 2009
APW7120A

Package Information
SOP-8
D

SEE VIEW A

E1

h X 45

e b c
A2

0.25
A

GAUGE PLANE
SEATING PLANE
A1

L
VIEW A

S SOP-8
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 1.75 0.069

A1 0.10 0.25 0.004 0.010

A2 1.25 0.049

b 0.31 0.51 0.012 0.020

c 0.17 0.25 0.007 0.010

D 4.80 5.00 0.189 0.197

E 5.80 6.20 0.228 0.244

E1 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
h 0.25 0.50 0.010 0.020

L 0.40 1.27 0.016 0.050

0 0° 8° 0° 8°

Note: 1. Follow JEDEC MS-012 AA.

2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.

Copyright  ANPEC Electronics Corp. 18 www.anpec.com.tw

Rev. A.3 - Nov., 2009
APW7120A

Carrier Tape & Reel Dimensions

OD0 P0 P2 P1 A

E1
F

W
B0

K0 A0 OD1 B A
B

SECTION A-A

T
SECTION B-B

d
H
A

T1

Application A H T1 C d D W E1 F
12.4+2.00 13.0+0.50
330.0 2.00 50 MIN. 1.5 MIN. 20.2 MIN. 12.0 0.30 1.75 0.10 5.5 0.05
-0.00 -0.20
SOP-8 P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0 0.10 8.0 0.10 2.0 0.05 1.5 MIN. 6.40 0.20 5.20 0.20 2.10 0.20
-0.00 -0.40

(mm)

Devices Per Unit

Package Type Unit Quantity
SOP-8 Tape & Reel 2500

Copyright  ANPEC Electronics Corp. 19 www.anpec.com.tw

Rev. A.3 - Nov., 2009
APW7120A

Taping Direction Information

SOP-8

USER DIRECTION OF FEED

Classification Profile

Copyright  ANPEC Electronics Corp. 20 www.anpec.com.tw

Rev. A.3 - Nov., 2009
APW7120A

Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
100 °C 150 °C
Temperature min (Tsmin)
150 °C 200 °C
Temperature max (Tsmax)
60-120 seconds 60-120 seconds
Time (Tsmin to Tsmax) (ts)

Average ramp-up rate

3 °C/second max. 3°C/second max.
(Tsmax to TP)
Liquidous temperature (TL) 183 °C 217 °C
Time at liquidous (tL) 60-150 seconds 60-150 seconds
Peak package body Temperature
See Classification Temp in table 1 See Classification Temp in table 2
(Tp)*
Time (tP)** within 5°C of the specified
20** seconds 30** seconds
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max.

Time 25°C to peak temperature 6 minutes max. 8 minutes max.

* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
3 3
Package Volume mm Volume mm
Thickness <350 ≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
3 3 3
Package Volume mm Volume mm Volume mm
Thickness <350 350-2000 >2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C

Reliability Test Program

Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ 125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM 2KV
MM JESD-22, A115 VMM 200V
Latch-Up JESD 78 10ms, 1tr 100mA

Copyright  ANPEC Electronics Corp. 21 www.anpec.com.tw

Rev. A.3 - Nov., 2009
APW7120A

Customer Service

Anpec Electronics Corp.

Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050

Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838

Copyright  ANPEC Electronics Corp. 22 www.anpec.com.tw

Rev. A.3 - Nov., 2009