Final Project – RISC V Hard Macros Integration
Technology Node: 32nm
Presented By: Gembali Dinesh
Content
• Project Overview
• Physical Design Flow
• Input to Physical Design
• Hard Macro
• Synthesis
• Synthesis Report
• Physical Design
• Floor Planning
• Power Planning
• Placement
• Clock Tree Synthesis
• Routing
• Static Timing Analysis
• Final Reports
Project Overview
Objective: Design and Implemented RISC – V IP with Hard Macro Creation
and Integration
Key Focus Areas:
1. Designed and implemented two hard macros for RISC-V sub modules,
meeting area, power, and performance constraints.
2. Integrated the hard macros into the top-level design with optimized floor
planning, placement, and routing.
3. Optimized design to meet timing closure and power constraints using static
timing analysis.
Physical Design Flow
The Physical Design flow is the Back End where the Technology Independent
Behavioral RTL is converted into GDS II.
Physical Verification
ASIC Design Flow
Inputs to Physical Design
• Netlist (.v): A logical representation of the design, typically in formats like
Verilog or VHDL, that specifies the circuit's connectivity.
• Liberty File (.lib): Contains information about the timing, power, and
functional characteristics of standard cells used in the design.
• Design Constraints File (.sdc): Specifies timing, area, and power
constraints for the design.
• Technology File (.tf): Includes details about the manufacturing process,
such as metal layer stack-up, design rules, and parasitic models.
• Library Exchange Format (.lef) : Describe the physical design rules &
abstract views of the standard cells, macros.
• Design Exchange Format (.def): Describes the design layout, including
floorplan, cell placement, and routing information.
• Power Intent File (.upf): Specifies the power domains and power
management strategies for low-power designs.
• Table Lookup Plus File (.tluplus): These files are crucial in the backend
flow of VLSI physical design, specifically for parasitic extraction and delay
calculation. They provide interconnect resistance and capacitance values.
Hard Macros
Hard Macro are created by reading the GDS II files into the library manager
and converting the gds file into the NDM file.
Msrv32_alu GDS View Msrv32_alu Frame View
Hard Macros Ctd.
The synthesis is done using Synopsys Design Compiler and Pnr with ICC2.
Machine_Counter GDS View Machine_Counter Frame View
Synthesis
Synthesis is the process of converting the Functional Behavioral RTL
into a gate-level netlist. Synthesis is done using Synopsys Design Compiler.
SDC File
Synthesis Setup File
Synthesis ctd.
Synthesis Run File Gtech Mapped RTL
Synthesis Report
Technology Mapped RTL Area Report
Synthesis Report Ctd.
Msrv32_top Schematic View
Physical Design
Physical design is the process of transforming a Gate Level Netlist
into a physical layout on a chip (GDS II). The conversion of GLN to GDS II
by using Synopsys ICC2.
Setup File
Imported Design to ICC2
Floor Planning
Floor Planning is the Process where the die area, core area will be
created to place the macros, and the I/O ports are placed at this stage.
Report_design
Floor Planning Ctd.
The macros, Placement blockages and Boundary cells are placed in
the core of the design.
Macros, IO’s, Physical Cells
Placed
Power Planning
The UPF file defines power-related details such as supply ports,
power domains, and level shifters, where we intent the power details.
• create_supply_net
• create_supply_set
• create_power_domain
• create_supply_port
• connect_supply_net
• set_level_shifter
• add_power_state
Power Domain Network
Power Planning Ctd.
By using Power Domain Network (PDN) we will distribute equal
power to all the cells in the design.
• connect_pg_net
• create_pg_ring_pattern
• create_pg_macro_conn_pattern
• create_pg_std_cell_conn_pattern
• create_pg_mesh_pattern
• set_pg_strategy
• compile_pg
Power Mesh Network
Power Planning Ctd.
Rings around ALU & MC macros
Power Planning Ctd.
Reports of Power and Ground Planning
• Check_pg_drc
• Check_pg_connecitivity
• Check_pg_missing_vias
Power Checks
Placement
The Placement is a process where all the cells will be placed and get
aligned to the rows in the design. Commands – “create_placement,
magnet_placement, place_opt”
Create_Placement Magnet_placement
Placement Ctd.
Report_timing before place_opt
Placement Ctd.
Check_legality
Place_opt
Placement Ctd.
Report_timing after place_opt
Clock Tree Synthesis
Clock Tree Synthesis is a process where we provide the clock to all
the sink nodes of the cells with minimum skew or zero skew along with equal
nets. While doing cts we will provide the ndr rules. Command – “clock_opt”
Clock Cells
NDR Rules
Clock Tree Synthesis Ctd.
Clock_opt
Clock Tree Synthesis Ctd.
Report_Timing Clock_opt
Clock Tree Synthesis Ctd.
Report_clock
Routing
Routing is a stage where all the interconnections between the cells
will be placed in this stage. After completing routing, we will generate GDS
file.
Route_opt
Routing Ctd.
Filler Cells are the non-functional cells where it fills the gaps between
the functional cells.
Filler_cells Insertion
Routing Ctd.
Filler_cells Insertion
Check_lvs
Static Timing Analysis
Static Timing Analysis is a method used to evaluate all the paths in a
design to confirm whether they meet the required timing constraints.
Input Files
• .sdc
• .spef
• Routed netlist
• Libraries
Output Files
• Timing Reports
• Eco Files
Timing_Analysis_Window
Final Reports
Report_Timing
Final Reports Ctd.
Check_Drc
Check_lvs
Final Reports Ctd.
Report_Design
Report_qor -summary
Final Reports Ctd.
Report_constraints Report_utilization
Final Reports Ctd.
Global_congestion_map
