US010855201B1

( 12 ) Noman
Unitedet alStates Patent ( 10 ) Patent No .: US 10,855,201 B1
Dec. 1 , 2020
. (45 ) Date of Patent :
( 54 ) CASCADED MULTILEVEL INVERTER 8,259,480 B2 9/2012 Hasler
9,343,989 B2 * 5/2016 Baruschka HO2M 5/293
( 71 ) Applicant: KING SAUD UNIVERSITY , Riyadh 9,571,004 B2 * 2/2017 Lavieville HO2M 7/483
( SA) 9,893,532 B2 * 2/2018 Harrison HO2J 3/381
2015/0236611 A1 * 8/2015 Nakazawa HO2M 1/36
363/123
( 72 ) Inventors : Abdullah Mohammed Ali Noman , 2016/0139643 A1 * 5/2016 Hasler G06F 1/26
Riyadh ( SA ) ; Abdulaziz Abdullah 700/297
Alkuhayli , Riyadh ( SA )
FOREIGN PATENT DOCUMENTS
( 73 ) Assignee: KING SAUD UNIVERSITY , Riyadh
( SA ) CN 108377105 A 8/2018
CN 108418461 A 8/2018
( * ) Notice: Subject to any disclaimer, the term of this
patent is extended or adjusted under 35 OTHER PUBLICATIONS
U.S.C. 154 ( b ) by 0 days .
Yu et al . , “ Delta - Connected Cascaded H - Bridge Multilevel Con
( 21 ) Appl. No .: 16 /892,707 verters for Large -Scale Photovoltaic Grid Integration ”, IEEE Trans
actions on Industrial Electronics ( 2017 ) , vol . 64 , pp . 8877-8886
(22) Filed : Jun . 4 , 2020 ( Abstract only) .
( 51 ) Int. Ci . * cited by examiner
HO2M 7/483 ( 2007.01 )
HO2M 7/5387 ( 2007.01 )
HO2J 3/38 ( 2006.01 ) Primary Examiner Gary L Laxton
HO2M 1/00 ( 2006.01 ) (74 ) Attorney, Agent , or Firm — Nath , Goldberg &
( 52) U.S. CI . Meyer; Richard C. Litman
CPC HO2M 77483 (2013.01 ) ; HO2J 3/381
(2013.01 ) ; HO2M 7/53873 ( 2013.01 ) ; HO2M
2001/0003 ( 2013.01 ) ; HO2M 2001/007 ( 57 ) ABSTRACT
(2013.01 )
( 58 ) Field of Classification Search The cascaded multilevel inverter utilizes a delta polyphase
CPC HO2M 7/483 ; HO2M 7/53873 ; HO2M circuit and transformers in each leg using cross -phase con
2001/0003 ; HO2M 2001/007 ; HO2J 3/381 nection windings. Transformers corresponding to a number
USPC 363/65 , 71 of phases of the inverter use an in -phase connection winding
See application file for complete search history. and a cross -phase connection winding to respective other
legs , so that the respective transformers having the in -phase
( 56 ) References Cited connection windings are connected in series with a DC
U.S. PATENT DOCUMENTS power supply
4,847,745 A 7/1989 Shelchawat et al .
5,642,275 A 6/1997 Peng et al . 14 Claims , 10 Drawing Sheets

B
17
V9112 +
©
B1 B2

IB

Cpv DC -DC
Converter Vdci.ICdci
12
ANA
U.S. Patent Dec. 1 , 2020 Sheet 1 of 10 US 10,855,201 B1

VSA

VSB VSC
B

IB

FIG . 1A
( PRIOR ART)
A
IBA

VSA

VSB - VSC
iAC
B C
IC
IB

Q11.2012
013-5014
FIG . 1B
( PRIOR ART )
U.S. Patent Dec. 1 , 2020 Sheet 2 of 10 US 10,855,201 B1

OSA 2

+
VSA

2
2

IA IC

AC B2 2
.
FIG
12

V61B2
VaicaB
B1

IBA
Q14
PALIO
Frio
Q13
A1
i1 ww

A1A2
I
U.S. Patent Dec. 1 , 2020 Sheet 3 of 10 US 10,855,201 B1

VsC 2
VSA

2
VSB

IA IC IB

AC B2
12

FIG
3
.
B1B2
V
12
*

Vaca B1 +

,
Q14

IBA
012-6
Q1163
Cdci Q13
A1 1
DC
- VCodnvcerlt
11 iCB
VAA2 B
)
ead
.
U.S. Patent Dec. 1 , 2020 Sheet 4 of 10 US 10,855,201 B1

VACAT DC Link Voltage

Controller
VACAT Phase A
VACAN
Vrei
1
VACAN
PI o û x 3/2
DVret
W331 DC Link Voltage
Controller
VABI Phase B
VON
Vret Boote

PI idrei
IVCBN x 3 /2
Vref

Virt DC Link Voltage

Controller
VICT Phase C
- Vref
Vanes
1
PI
* / 3/ 2
CVret

FIG . 4
U.S. Patent Dec. 1 , 2020 Sheet 5 of 10 US 10,855,201 B1

Vsa
Abc /dq Vsb
-Vsc

engles
??
1
håret
Î x 3/2 Velo
V

igrei

Current Controller
WL
PI
1
V dc
dq /abc
TE
FIG . 5
U.S. Patent Dec. 1 , 2020 Sheet 6 of 10 US 10,855,201 B1

2 2 2

Vdca2 1.8
-Vdcb2 1.8
VA.RdDcAUD2E 1.8

Vdcal 1.6 Vdcb1 1.6 -Vdc 1 1.6

1.4 1.4

1.2 1.2
1.2
1
Time
Sec
(
)
. Time
Sec
{
)
. Time
Sec
)
.
1
6A
FIG
. 1
6B
.
FIG FIG
.
6C
0.8 0.8 0.8

0.6 0.6

0.4 0.4 0.4

0.2 0.2 0.2

0 0
95
115 110 105 100 95
115 110 105 100 115 110 105 100 95
Vw(w Voltages00 V Voltages V( Voltages
U.S. Patent Dec. 1 , 2020 Sheet 7 of 10 US 10,855,201 B1

1.305 Vix 1.305

CI 1.3
VBC w
.

---
no
**
VALA2
Wirts
1.295 1.295
VAB
1
67 1.29

1.285 Time(Sec.) 1.285 Time(Sec.)

*
w
WW 7A
.
FIG 7B
.
FIG
V2.NO
.
====
1.28 1.28
4. ...

1.275 1.275
me
Orth
1.27 1.27

1.265 1.265
ceny 0
600 400 200 -20 009 200 100 -10 -20
V Voltages
po k V Voltages
W
U.S. Patent Dec. 1 , 2020 Sheet 8 of 10 US 10,855,201 B1

IA . IB IC
000000000000

5
C[
]
A
ur ents

0.6 0.61 0.615 0.62 0.625 0.64 0.645 0.65

Time Sec.]
FIG . 8A
11 12 13
5
C(
Al
ur ents
-5
.

0.6 0.605 0.615 0.62 0.625 0.63 0.635 0.645 0.65

Time (Sec.]
FIG . 8B
U.S. Patent Dec. 1 , 2020 Sheet 9 of 10 US 10,855,201 B1

VSA

M
150

100
50
Current
[
Voltage
,
]
AIV
) 0
Win !

-50

-100
-150

0.6 0.605 0.61 0.615 0.62 0.625 0.63 0.635 0.64 0.645 0.65
Time [Sec.)
FIG . 9
U.S. Patent Dec. 1 , 2020 Sheet 10 of 10 US 10,855,201 B1

Fundamental ( 60Hz ) = 4.737 , THD = 3.44 %

3

2.5

F)ofMag(%undamental 1,5
0.5

0
2 3 4 ..... 7 8 9 10 11 12 13 14 15 16 17
Harmonics Order

FIG . 10
 US 10,855,201 B1
1 2
CASCADED MULTILEVEL INVERTER plurality of transformers corresponding to a number of
phases of the multilevel inverter. Each transformer has an
BACKGROUND in - phase connection winding and a cross -phase connection
1. Field
winding to respective other legs . A plurality of legs corre
5 spond to the number of phases of the multilevel inverter,
The disclosure of the present patent application relates to each comprising one of the transformers, with the respective
multilevel inverters, and particularly to a cascaded multi transformers having the in - phase connection windings con
level inverter based on a delta - connected cascaded H - bridge nected in series with a DC power supply. The transformers
topology for grid -connected applications. have their cross -phase connection windings connected to
10 different phase legs with different ones of the transformers
2. Description of the Related Art having their cross -phase connection windings connected on
opposite sides of the in - phase connection windings within
Inverters are often used to connect multiple DC power the leg connected to the cross -phase connection winding .
sources , e.g. , from solar or photovoltaic cells , to an AC In one particular exemplary configuration , the legs and
power grid. According to the number of output voltage 15 transformer connections are configured in multiples of three .
levels generated from an inverter, the inverter can be clas These and other features of the present disclosure will
sified into one of two groups: two - level inverters or multi become readily apparent upon further review of the follow
level inverters (MLI ) . The elementary concept of employing ing specification and drawings .
a multilevel converter to achieve higher power is to use a
series of power semiconductor switches with several lower 20 BRIEF DESCRIPTION OF THE DRAWINGS
voltage DC sources to perform the power conversion by
synthesizing a staircase voltage waveform . The term multi FIG . 1A is a schematic diagram of a multilevel inverter of
level began with the three - level converter . Subsequently, the prior art, showing an exemplary star - connected cascaded
several MLI topologies have been developed . The higher the H -bridge topology.
number of output voltage levels , the better the output voltage 25 FIG . 1B is a schematic diagram of a multilevel inverter of
and current quality. In addition , the sizes of the output filters the prior art, showing an exemplary delta - connected cas
and the voltage stresses on semiconductor switches could be caded H -bridge topology.
reduced . Furthermore , due to minimizing the switching FIG . 2 is a schematic diagram showing a cascaded mul
frequency, the efficiency of MLIs is high . tilevel inverter topology according to the present disclosure .
The most common MLI topologies can be classified into 30 FIG . 3 is a schematic diagram showing the cascaded
three types: neutral point MLI , flying capacitor MLI , and
cascaded H -bridge. The cascaded H -bridge (CHB ) MLI is multilevel inverter of FIG . 2 configured for grid -connected
considered one of the most suitable configurations to be used photovoltaic ( PV ) application .
in next - generation large -scale photovoltaic ( PV ) power FIG . 4 is a schematic diagram showing a configuration
plants, attracting significant research interest both from the DC - link voltage controllers for a three -phase delta- con
technical and financial perspective . The CHB MLI includes 35 nected cascaded multilevel inverter configured as in FIG . 2 .
a series connection of several H -bridge cells . Compared to FIG . 5 is a schematic diagram of an exemplary current
the other conventional MLI topologies , it uses fewer semi controller for use in the configurations of FIGS . 2 and 3 .
conductor switches at the same levels . Due to the separated FIGS . 6A , 6B , and 6C are waveform diagrams from a
DC source feature of the CHB topology, it can be used for simulation with two cascaded H -bridge inverters ( as in FIG .
numerous applications, such as standalone systems , grid- 40 2 ) per phase , showing the DC - link voltages compared to the
connected PV systems, and active filters. The CHB configu reference voltage.
ration can be connected as a star as well as a delta connec FIG . 7A is a graph of the three -phase line - line voltages
tion . Each connection has different applications. The delta generated in the simulation of FIGS . 6A - 6C .
connected CHB MLI can be used for static synchronous FIG . 7B is a graph of the voltage generated by the
compensation (STATCOM ), and it is easy to implement 45 cascaded H -Bridge of phase a of the simulation of FIGS.
individual phase control. It has received great attention in 6A - 6C , as well as the voltages generated across the trans
STATCOM applications required to handle negative formers.
sequence reactive power. The delta - connected H - bridge FIGS . 8A and 8B are graphs of currents for the simulation
inverter has recently drawn attention as a promising alter of FIGS . 6A - 6C , showing grid currents (FIG . 8A) , and
native to the star - connected bridge inverter in PV applica- 50 currents passing in the cascaded H -bridge of each phase
tions . (FIG . 8B ) .
Nevertheless, to avoid under -balanced PV generation , the FIG . 9 is a graph showing grid current and grid voltage in
delta connection requires a greater number of bridges cas phase a for the simulation of FIGS . 6A - 6C , showing the
caded in series than the star connection to reach the line power factor kept at unity.
to - line grid voltage , thus inevitably increasing the size of the 55 FIG . 10 is a chart showing the harmonic spectrum of the
converter. Therefore, the delta - connected H -bridges are grid current for the simulation of FIGS . 6A - 6C .
more costly than star - connected H - bridges to synthesize the Similar reference characters denote corresponding fea
same line - line voltages . It requires a bridge number 3 times tures consistently throughout the attached drawings.
larger, since one phase leg must synthesize the line - to - line
voltage . 60 DETAILED DESCRIPTION OF THE
Thus, a cascaded multilevel inverter solving the afore PREFERRED EMBODIMENTS
mentioned problems is desired.
The cascaded multilevel inverter is a three -phase cas
SUMMARY caded multilevel inverter for grid - connected photovoltaic
65 (PV) applications. The inverter is based on a delta - connected
A cascaded multilevel inverter is configured as a delta or cascaded H -bridge ( CHB ) , wherein three coupled transform
end - connected polyphase circuit . The circuit comprises a ers are substituted for the inductors to thereby synthesize the
 US 10,855,201 B1
3 4
line - line voltage levels . Through the use of these coupled duced to modify the delta - connected CHB in order to
transformers, the line - line voltage levels of the disclosed generate line - line voltage levels as the same line - line voltage
topology are the same as the line - line voltage levels of the levels of the star - connected CHB from the same number of
star - connected CHB topology, unlike previous delta -con H -bridges.
nected CHBs . 5 The multilevel inverter is a modified topology for the
The multilevel inverter introduces a technique based on a delta - connected cascaded H -bridge MLI . FIG . 2 is a sche
delta -connected CHB configuration to increase the number matic diagram showing CHB topology configured according
of voltage levels of the line - line voltages to the number of to the present disclosure . As shown in this Figure, three
levels generated by the star - connected CHB . The number of coupled transformers are used instead of the inductors to
required H -bridges are the same to generate the same 10 synthesize the line - line voltage levels . With the help of these
line - line voltage levels . The configuration is mathematically coupled transformers, the line voltage levels of the present
modeled and it is built in the SIMULINK environment to cascaded multilevel inverter is the same as the line - line
test its accuracy and effectiveness. Simulation results are voltage levels of the star - connected CHB topology. The
provided to prove the disclosed topology. same number of switches to generate a certain number of
The multilevel inverter relates to a three -phase cascaded 15 line - line voltage levels can be used in the present multilevel
multilevel inverter topology. The conventional delta -con inverter to generate the same levels .
nected cascaded H -bridge multilevel inverter topology has a In addition , there is no need to use interface inductors for
drawback compared to the star - connected cascaded grid - connection application . On the other hand, the coupled
H - bridge multilevel inverter. It requires a greater number of transformers in the present multilevel inverter can also be
H - bridges cascaded in series than the star connection to 20 used to step up the generated voltage without the need to use
reach the line - to - line grid voltage , thus inevitably increasing an external step up transformer at the point of coupling with
the size of the inverter. Therefore , the present multilevel the utility.
inverter introduces a new topology for the delta - connected Using a CHB configuration such as the configuration
cascaded H -bridge inverter for grid - connected photovoltaic shown in FIG . 2 , applying KVL yields :
( PV ) applications. The multilevel inverter has the same 25 VsA - VC2A1 - VA1A2 - V $ B = 0
number of the line - line voltage levels generated by the
star - connected CHB for the same number of switches . VsB - VA2B1 - VB1B2 - V % C = 0
Mathematical modeling of the disclosed topology and the Vsc - VB2C1 - Vc1c2 - VsA = 0 (1)
simulation results are presented to verify the disclosed
topology's effectiveness and reliability. 30 Assuming that the turn ratios of the coupled transformers are
The cascaded multilevel inverter relates to a three -phase unity, equation ( 1 ) can be written as :
multilevel inverter, which can be used for different applica VAB = VB2B1 + VA1A2
tions such as PV - grid connection, active power filters, STAT
COMs , etc. It is based on a delta -connected cascaded VBC = Vc2ci + VB1B2
H - bridge multilevel inverter. The disclosed technique 35
improves the performance of the delta -connected cascaded VCA = VA2A1 + VC1C2 (2)
H - bridge by inserting three coupled transformers instead of The root -mean square (RMS ) values of the voltages across
the three inductors in the conventional delta - connected the H - bridge cell in the disclosed topology can be given as :
cascaded H - bridge inverter. These transformers are con
nected in such a way as to increase the number of voltage 40
levels compared to the conventional delta - connected cas VA1A2 Nma Vdc L 0 ° (3 )
caded H -bridge inverter for the same number of switches . V2
The cascaded multilevel inverter provides an improved Nm Vác L 120°
multilevel inverter based on a delta - connected cascaded V8182 =

multilevel inverter for high voltage/high power grid -con- 45 V2

nected applications . The cascaded multilevel inverter uses Vc1c2
Nma VdcL + 1200
=

fewer semiconductor devices than conventional multilevel v2

inverters . A method for controlling the cascaded multilevel
inverter supplies an approximately sinusoidal power wave Substituting equation (3 ) into equation (2 ) , we get :
form for an AC high voltage , high power system from a 50
plurality of DC voltage sources for a variety of applications. VAB =V3Nm . Vde sin ( wt + 30 °)
FIGS . 1A and 1B (prior art) are schematic diagrams VBC= V3NmVde sin (wt - 90 °)
showing ( FIG . 1A) a star - connected cascaded H - bridge
(CHB ) topology and ( FIG . 1B ) a conventional delta - con VcA=V3NmeVde sin (Wt + 150 °) (4)
nected CHB topology. The number of the line - line voltage 55 Equation ( 4 ) demonstrates that the generated line - line volt
levels of the delta - connected CHB is the same as the
age of the disclosed topology is the same as the line - line
line- neutral voltage levels of the star - connected CHB MLI , voltage
as can be seen in FIG . 1A . FIG . 1B shows a conventional of the star - connected CHB .
delta - connected CHB topography. At the same line - line given The internal currents of the CHB in each phase can be
voltage , the number of H -bridges of the delta - connected 60 as :
CHB MLI is V3 times larger than the number of H - bridges
of the star - connected CHB , which, in turn , increases the cost iz - ix (5 )
of the delta -connected CHB . Moreover, the switching losses iz - iy
and the conduction losses are higher, and hence the inverter
efficiency of the delta - connected CHB is lower than the 65 ly - iz
efficiency of the star -connected CHB at the same line - line
voltage levels . Therefore, the disclosed technique is intro
 US 10,855,201 B1
5 6
where ix, in, and i, are the currents flowing in the primary -continued
side of the coupled transformers T , T , and T ,, respectively. ( VAT ) = VA1A2lzrms = V6
NmaVdcl
Assuming the magnetizing inductances of the coupled
transformers are high, so that: 5

iz +in +i< =0, ( 6) where VAT, VAT, and VAT are the apparent powers of the
coupled transformers of phases a , b , and c , respectively.
from equations ( 5 ) and ( 6 ) , the currents of each coupled Equation ( 12 ) demonstrates the apparent power of each
transformer can be expressed as : coupled transformer is ( 1/3) of the CHB cells of one phase .
10 Moreover, the total apparent power of the disclosed
topology can be expressed as :
iy V2 sinsin((wt + 150 ° )
wt + 90 °)
V3 sin( wt – 309 )
( VAT ) = V3 VABIAMS 3 NmaVdc
2
( 13 )
15

In addition, the grid currents can be given as : The cascaded multilevel inverter can be used in various
applications, such as grid -connected PV applications, active
?? -iz – ix + iy ( 8) power filters, etc. In the present disclosure, it is exemplified
20 as used for a grid -connected PV application .
18 =
- 11 - iy ++ iz FIG . 3 is a schematic diagram showing the present CHB
Ic . - 12 - iz + ix topology configured for photovoltaic (PV )-grid connection
purposes. Each H - bridge is connected to PV modules via a
DC -DC converter for maximum power point tracking pur
Substituting equations ( 7 ) and ( 8 ) into equation ( 5 ) , the 25 poses . The main aim of the inverter controller is to generate
three -phase grid currents can be given as : reference currents in the synchronous frame such that the
disclosed topology provides only available active power at
the DC - links to the grid with zero reactive power to guar
antee unity power factor.
03-5-7
?? sin (wt)
V21 sin( wt - 120 ° ) 30 FIG . 4 is a schematic diagram showing a configuration for
Ic sin ( W7 + 120 ° )
DC -link voltage controllers as used in the configurations of
FIGS . 2 and 3. FIG . 5 is a schematic diagram showing a
configuration for an example current controller as used in
where i is the RMS grid current. the configurations of FIGS . 2 and 3. The disclosed control
strategy is based on the classical control scheme of the
Equation (9) proves that the grid currents and the internal 35 inverter. This scheme is extended to control the disclosed
currents in each CHB phase in the disclosed topology are the multilevel inverter. The DC - links of phase a , Cdcal,
same. Moreover, the currents, iac, iCB and iba can be given Cdc42, ... , Cdcan , are sharing the same active grid current
as :
of phase a , where Cdcal, CdA2, . Cdcan are the DC - link
capacitors connected to H -bridge cell 1 , 2 , ... , N , respec
40 tively, of phase a . The DC - link voltages of these capacitors
iac istic sin ( wt - 180 ° ) ( 10 ) are compared with their respective reference voltages .
??? = ( 1 ++ iB iz = V21 sin (wt -60 °) Assuming that the control system accurately regulates the
??? iz tia sin ( wt + 60 ° ) DC - link voltages , then :
Vdea = Vacb = V dec = V detot ( 14)
45
The total apparent power of the N H - bridge cells con where V dCA Vdcb and Vdcc are the equivalent DC voltage
nected to each phase satisfies the following equations: across the DC - link capacitors connected to the phases a , b
and c , respectively.
The modeling technique is based on Kirchhoff's law of
the MLI in the dq frame, so that one gets :
(VAcells a ) = VA1A2 /1ms NaVac
( 11 ) 50
V2
V Acells_b VB1B2 / 2rms Nma
=
V2
Vdc did
Vd = Ls dt (WLs ) ig + dnd Vdctot
( 15)

V Acells_c = Vc1c2 / 3ms Nma2Vdc 1 55 Va = Lsdia

dt (WL )id + dnd Vdctot

In addition , the apparent power of each coupled transformer where Ls , represents the leakage reactance of the coupled
can be given as : transformer, and dry, is defined as the sequential function
60 and is given by :
NmaVacl ( 12)
( VAT; ) = VB1B2 Ixrms = V5 dna CA
1
( 16 )
dnB = ??
=
( CA + CB + CC )
Nma Vdcl
(VAT, ) = Vcicz?yms V6
65 dnc
 US 10,855,201 B1
7 8
where CA, CB and Cc are the equivalent DC - link capacitors The disclosed control scheme based on the analysis above
connected to the phases a , b , and c , respectively . is shown in FIGS . 4 and 5. The reference active current of
The DC current can be defined as : the grid i dref is compared with the actual active current id .
The resulting error is inserted into the PI controller in order
5
to keep the actual active current following the reference
Cdc dVdctot
dt - dndid + dngia
( 17 ) active current. On the other hand, the reference reactive
current of the grid ( igrer 0 ) is compared with the actual
reactive grid current i , to guarantee unity power factor.The
A new equivalent model can be introduced to analyze the 10
resulting signals, dnd and dng are transformed into abc
nonlinearity problems . These inputs may be written as : modulation waveforms (Mrefa, Mrefb , and Mrefc). These
u F (WLs)ig - Und V detor + Vd modulation waveforms are then applied to the phase shifted
pulse -width modulation (PSPWM) in order to generate the
Ug= (WL )id - dngVdctor + Va ( 18 ) required IGBTs pulses. PSPWM modulation technique
15 causes equal sharing of losses among different switches . In
As stated above , the active current id is responsible to addition , PSPWM needs only one carrier signal to generate
regulate the DC link voltages and compensates for losses in the various necessary switching signals, and helps to reduce
the dissipative elements of the inverter. In addition, the the THD in the generated MLI output voltage .
reactive current i , should be set to zero to guarantee unity The disclosed topology is built in the SIMULINK envi
power factor . Therefore, equation ( 17 ) can be written as : 20 ronment to evaluate its performance. The system parameters
used for simulation are shown in table 1 :

Udc =:Cac
dVdctot ( 19) TABLE 1
dt = andid
Parameters for SIMULINK testing
25 System Parameters
DC Link Capacitor 4 mF
Udc ( 20 ) DC - DC converter switching frequency fs 30 kHz
id =

and Inverter switching frequency finv 900 Hz

Per phase grid rated RMS voltage 120 V
30 Reference voltage 100 V
Coupling transformers 1 : 1 turn ratios, L = 2 mH
In normal operation and under accurate current loop
control, the following properties apply :
FIG . 6 is a graph showing DC - link voltages at reference
voltages . For simplicity, two cascaded H -bridge cells are
3 ( 21 ) 35 considered for each phase in the disclosed topology. The
Vd ~ dnd Vdctot dnd Vdctot NI Vmax control scheme succeed in keeping the DC - link voltages at
the reference voltages as illustrated in FIG . 6 .
FIGS . 7A and 7B are graphs of voltages at the CHB ,
, is the maximum value of the grid voltage . showing ( FIG . 7A) the voltages across the three legs show
where V???
Replacing equation ( 21 ) into equation ( 20 ) , one gets: 40 ing the generated three -phase line - line voltage , and ( FIG .
7B ) the voltages generated by the CHB of the phase across
the transformers. As can be seen in FIGS . 7A and 7B , nine
2 Udc ( 22) voltage levels are generated . This result coincides with the
id
3 Vmax Vectot analysis of the disclosed topology in which it could generate
45 seven line - line voltage levels ( since only two cascaded
H -bride cell are used per phase ) as star - connected CHB do ,
The active current id is the active current, which is while using the same number of switches. Three H - bridge
responsible to regulate the DC -link capacitors of each phase . cells must be used per phase in the conventional delta
From equation (22 ) , the active reference current, which is connected CHB inverter of FIG . 1A in order to generate
responsible to regulate the DC - link capacitors of phase a , 50 these same nine line - line voltage levels . In addition, FIG . 7B
can be expressed as : shows the voltages generated by the CHB of phase a
(VA1A2 ), as well as the voltage generated across the trans
formers TS .
2 Udca ( 23 ) FIGS . 8A and 8B are waveform diagrams of currents at
ida
Ž Imax Vdca 55 the CHB for the three phases, showing (FIG . 8A) grid
currents, and (FIG . 8B ) internal currents . As stated in the
analysis, the grid currents coincide with the phase currents
The reference active current of the grid is the sum of the passing in each CHB . FIG . 8A shows the three - phase grid
three active current id: currents and FIG . 8B shows the currents passing in each
60 CHB of each phase.
FIG . 9 is a waveform diagram showing grid current and
idref = ida + ide + idc ( 24 ) grid voltage in phase , showing the power factor kept at unity.
FIG . 10 is the harmonic spectrum of the current through the
2 UdcA 2 UdcA 2 UdcA CHB . The current controller scheme succeeded in keeping
3 VmaxVdca ŽVmaxVdca + ŽV max Vaca
+
65 the grid current in phase with the grid voltage , and hence the
power factor is kept unity, as demonstrated in FIG . 9. The
THD of the grid current i , is 3.44 % , which has acceptable
 US 10,855,201 B1
9 10
harmonic content less than 5 % defined by IEEE standard . a connection for an external DC power supply ;
The harmonic spectrum of the grid current i4 is shown in a DC - DC converter capable of providing a DC output at
FIG . 10. The magnitude of the fifth harmonic order is a design output voltage ; and
approximately 1 % . The magnitude of the other harmonic an H -bridge circuit receiving the DC output, the plurality
orders are less than 1 % . 5
of circuits being connected in series for each respective
It is to be understood that the cascaded multilevel inverter phase.
is not limited to the specific embodiments described above, 8. A method of inverting DC current to provide a poly
but encompasses any and all embodiments within the scope phase AC output, comprising the steps of:
of the generic language of the following claims enabled by connecting a plurality of legs , at end connections, and
the embodiments described herein , or otherwise shown in 10 cross - connecting the legs with at least one transformer
the drawings or described above in terms sufficient to enable per leg , cross - connected to at least two other legs of the
one of ordinary skill in the art to make and use the claimed plurality of legs , each of the at least one transformers
subject matter. having an in- phase connection winding and a cross
We claim :
1. A cascaded multilevel inverter, comprising a delta- 15 phase connection winding to respective other legs of
connected polyphase circuit having: the plurality of legs ;
a plurality of transformers corresponding to a number of for each of the legs , connecting a DC power supply in
phases of the multilevel inverter; series with the respective leg , so that each of the legs
a plurality of legs corresponding to the number of phases includes one of the at least one transformers, the
of the multilevel inverter, each leg including one of the 20 respective transformers having the in -phase connection
transformers, the respective transformers each having windings connected in series with a DC power supply ;
an in -phase connection winding connected in series and
with a DC power supply and a cross -phase connection configuring the legs and transformer connections in mul
winding , the cross - phase connection winding being tiples of three.
connected to respective ones of the other legs ; and 25 9. The method of claim 8 , further comprising configuring
the plurality of transformers having their cross -phase the legs and transformer connections as a three -phase delta
connection windings connected to different phase legs connected inverter.
with different ones of the transformers having their 10. The method of claim 8 , further comprising configur
cross -phase connection windings connected on oppo ing said inverter as a three -phase delta - connected cascaded
site sides of the in -phase connection windings within 30 H -bridge multilevel inverter.
the leg connected to the cross -phase connection wind 11. The method of claim 8 , further comprising configuring
ing , the legs and transformer connections being con the plurality of transformers to comprise three transformers
figured in multiples of three. in a three -phase delta - connected H - bridge multilevel
2. The cascaded multilevel inverter of claim 1 , wherein
the multilevel inverter is a three - phase inverter. 35 inverter, the transformers performing an inductance function
3. The cascaded multilevel inverter of claim 1 , wherein in each leg of the delta - connected H - bridge multilevel
the multilevel inverter is a three -phase delta - connected inverter.
cascaded H -bridge multilevel inverter. 12. The method of claim 8 , further comprising providing
4. The cascaded multilevel inverter of claim 1 , wherein the inverter as a polyphase star - connected output connection
the plurality of transformers comprises three transformers in 40 with a number of phases corresponding to the number of
a three -phase delta - connected H -bridge multilevel inverter, phases of the inverter, and supplied from respective output
the transformers performing an inductance function in each nodes from delta circuit .
leg of the delta - connected H -bridge multilevel inverter. 13. The method of claim 8 , wherein the DC power supply
5. The cascaded multilevel inverter of claim 1 , further comprises at least one circuit having:
comprising a polyphase star - connected output connection 45 a connection for an external DC power supply ;
with a number of phases corresponding to the number of a DC - DC converter capable of providing a DC output at
phases of the inverter, and supplied from respective output a design output voltage ; and
nodes from delta circuit . an H -bridge circuit receiving the DC output.
6. The cascaded multilevel inverter of claim 1 , wherein 14. The method of claim 8 , wherein the DC power supply
the
ing : DC power supply comprises at least one circuit includ- 50 includes a plurality of circuits, each circuit having:
a connection for an external DC power supply ; a connection for an external DC power supply ;
a DC - DC converter capable of providing a DC output at a DC - DC converter capable of providing a DC output at
a design output voltage ; and a design output voltage ; and
an H -bridge circuit receiving the DC output. 55 an H -bridge circuit receiving the DC output, the plurality
7. The cascaded multilevel inverter of claim 1 , wherein of circuits being connected in series for each respective
the DC power supply comprises at a plurality of circuits, phase .
each of the circuits including :