IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO.

12, DECEMBER 2005 2753

Effects of Layout Methods of RF

CMOS on Noise Performance
Wen Wu, Student Member, IEEE, Sang Lam, and Mansun Chan, Senior Member, IEEE

Abstract—This paper presents a study on the effects of different

layout methods on the noise performance of RF CMOS transis-
tors. The optimization of RF characteristics using multifinger
layout and a more compact waffle layout with Manhattan-oriented
polysilicon gate are studied. The waffle layout is demonstrated
to have a larger design window through the simulation as well
as the experimental data. The improvement of both the max-
imum oscillation frequency max and the cutoff frequency
at the same biasing condition leads to the improvement on RF
noise performance for the waffle MOSFETs. Compared with the
multifinger devices, the SpectreRF simulation reveals that 10%
reduction in noise figure is achieved when the waffle MOSFETs
are used in CMOS low-noise amplifiers.
Fig. 1. Small-signal model for microwave applications.
Index Terms—Cutoff frequency, layout, maximum oscillation
frequency, MOSFET, noise, radio frequency (RF).
of multifinger MOSFETs are studied in Section III and that of
I. INTRODUCTION waffle MOSFETs in Section IV. In Section V, we compared the
performance of devices and circuits utilizing the two different

W ITH THE significant improvement in operating speed

and the prolific use in radio frequency (RF) design,
CMOS technology shows the capability in the realization of
layout methods based on measurements and circuit simulations.
Finally, we conclude the paper in Section VI.
low-noise circuits for multigigahertz portable communication
systems [1], [2]. In the design of analog transistors with large II. METHODOLOGY AND EXPERIMENTAL PROCEDURES
W/L ratio that provides a sufficient power gain, multifinger
The layout effects on noise performance are mainly caused
layouts are widely used to reduce the gate resistance . At
by the extrinsic parasitic components. To understand effects of
the same time, some layout dependent parasitic elements are
various components on the noise performance, a high-frequency
introduced. Researchers have analyzed the optimum layout
model of MOSFETs is constructed based on the physical struc-
for wide transistors in high frequency applications [3], [4].
ture. Fig. 1 shows the details of this small-signal model for
However, the noise characteristics are less emphasized. In this
RF/microwave applications. The gate resistance affects both
paper, we studied the tradeoff between the number of fingers
the power matching errors of the device to source impedance
and the finger length in multifinger MOSFETs with different
(e.g., 50 ) and the power gain which influences the noise figure.
W/L ratios. We optimize the layout of transistors for low noise
and are the drain and source parasitic resistances, respec-
operations. In addition, we study the MOSFETs that are de-
tively. is the equivalent channel resistance from the gate to
signed with a more compact but less traditional waffle layout
source at the input. The device transconductance is denoted as
method. Comparisons between the multifinger MOSFETs and
and is related to the output conductance . The drain-
the waffle MOSFETs demonstrate that the waffle MOSFETs
bulk capacitance and resistance, and , are included to
provide a higher and a higher to meet the low-noise
account for the substrate influence on the output admittance
requirement for the wireless systems nowadays. A small-signal
. and are the gate-to-source and gate-to-drain ca-
model is also developed to explain the design tradeoff, and the
pacitances, respectively with the overlap and fringing capaci-
results obtained from actual silicon are reported.
tance included. The gate to substrate capacitance plays an
The paper is organized as follows. In Section II, a detailed
important role in the RF characteristics of MOSFETs. The ex-
description of our methodology and experimental procedures
trinsic part of corresponding to the gate pads outside of the
is given. The effects of design parameters on the performance
active area cannot be ignored for the wide devices operating
in RF situations, although the source/drain conducting plane
Manuscript received March 11, 2005; revised August 12, 2005. This work was shields the intrinsic part of in the active area when devices
supported by the Research Grant Council of Hong Kong under a Competitive
Earmarked Research Grant. The review of this paper was arranged by Editor M. operate in the saturation region. We define as the sum of
J. Deen. , and . In our paper, we assume that the body of
The authors are with the Department of Electrical and Electronic Engineering, transistors is connected to the source and grounded.
The Hong Kong University of Science and Technology, Kowloon, Hong Kong
(e-mail: eewuwen@ee.ust.hk). In this three-terminal model, the gate terminal acts as port 1
Digital Object Identifier 10.1109/TED.2005.859694 and the drain terminal acts as port 2. The parasitic resistances
0018-9383/$20.00 © 2005 IEEE
2754 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 12, DECEMBER 2005

, , and at the terminals are extracted from the Z-param- analyzer. All the parasitic components of the input and output
eter network converted by S-parameters at 0V pads are removed before the extraction process. A de-embed-
[5], at which the contribution of and becomes zero. The ding procedure is carried out by subtracting Y-parameters of
effect of bias on and is very small and can be ignored. the open pad structure from the Y-parameters of the measured
Details of the extraction are given in (1)–(3) below devices. All the small-signal parameters are extracted using
(1)–(12).
Re (1)
Re Re (2) III. DESIGN OPTIMIZATION OF THE MULTIFINGER MOSFETS
Re (3) Two most important figures of merit (FoM) for RF CMOS
transistors in the literature are the cutoff frequency and the
After eliminating the influence of and from Z-parame- maximum oscillation frequency . They are given by
ters at the desirable bias condition, we acquire the intrinsic Y-pa-
rameters after the conversion of the new Z-parameters. Transad-
mittance Y-parameters can be approximated [6], [7] by (4)–(7), (13)
under the assumption that 1. The validity of this
assumption can be shown after the small-signal parameters are
extracted
(14)
(4)
(5)
It is reasonable to assume that
(6)
at RF range [9] for (14). The maximum
power gain given in (15) quantifies the power delivered
by the device when both input and output ports are matched to
the source and load impedance, respectively

(15)

By setting to unity, we can derive . Since

(7) contains most of the intrinsic and parasitic electrical elements,
it has more influence on the noise properties than cutoff fre-
All components in the equivalent circuit are extracted by the quency [10]. In other words, incapable to suppress input-re-
Y-parameter analysis. Analytical equations are derived from real ferred noise at a reduced may cause the malfunction of
and imaginary parts of the Y-parameters. Some pivotal extrac- some noise-sensitive components such as CMOS LNA in RF
tion equations are given in (8)–(11) transceivers.
The gate resistance and parasitic source/drain junction capac-
Re (8) itance of a MOSFET can be reduced by distributing the total
device width into smaller parallel transistors in the multifinger
Re (9) layout structure. The configuration of using contacts on one side
of the fingers leads to an overall gate resistance [11]
Im
(10)
Im (16)
(11)

After the extraction of substrate components and where is the sheet resistance of the polysilicon gate mate-
from (Details are given in [8]), can be obtained by rial (typically, 5 10 sq). and are the total width and
using (7) and it is expressed as channel length of MOSFETs, respectively. is the number
of parallel fingers. Although (16) indicates that the gate resis-
Im tance can be reduced by increasing , the increase of
will lead to an increase of extrinsic gate-bulk parasitic capac-
(12) itance [12] caused by the gate pads outside of the active area.
The extraction method is used to extract the parameters of Also, more gate-source and gate-drain overpasses are required
MOSFETs that are fabricated in a 0.35- m CMOS technology for more parallel polysilicon gates. The tradeoff between and
with a typical device width of 200 m. S-parameters are gate resistance results in the existence of a maximum
measured in the common source-substrate configuration using when an optimum number of fingers is used, which is shown
on-wafer RF probes and an Agilent 8722ES vector network in Fig. 2 for a typical 0.35- m process technology.
WU et al.: EFFECTS OF LAYOUT METHODS OF RF CMOS ON NOISE PERFORMANCE 2755

Fig. 2. Simulated maximum oscillation frequency f varies with the Fig. 3. Simulated minimum noise figure NF and cut-off frequency f as
number of finger N for the multifinger MOSFETs at different device width a function of the unit finger length for the multifinger MOSFETs. Devices are
range. Devices are biased at V = 1 V and V = 2 V with the 0.35-m biased at V = 1 V and V = 2 V with the standard 0.35-m and 0.18-m
process technology. technologies. The operating frequency for NF is chosen as a typical value
2 GHz.

For low noise applications, the minimum noise figure TABLE I

NF of a MOSFET is an important indicator of RF noise SIMULATION RESULTS FOR THE MULTIFINGER DEVICES WITH TWO KINDS OF
OPTIMAL DESIGN, 3-BY-3, 4-BY-4, AND 5-BY-5 WAFFLE MOSFETS WITH THE
performance and is given by [12] and [13] 0.35-m AND 0.18-m TECHNOLOGIES. ALL OF THE SIMULATED NF ,
f , AND f IN THE 0.35-m TECHNOLOGY ARE BASED ON THE
EXTRACTED PARAMETERS LISTED IN TABLE II

NF 1 2
(17)
where is the operation frequency, and is a constant. Note
that (17) is restricted to the drain noise current. The induced
gate noise current is neglected for the frequency range in this
paper, as well as the correlation between the drain and gate noise
current sources. To further study the input noise, we use the
well-known noise figure equation [14]

NF (18)
IV. DESIGN OPTIMIZATION OF WAFFLE MOSFETS
where and are the equivalent noise resistance and noise In addition to the traditional multifinger MOSFETs, a more
conductance, respectively. is the signal source compact waffle layout can be used in RF CMOS circuits. Fig. 5
admittance. If the noise matching is not perfect (in other words, shows a basic unit cell of a waffle-layout MOSFET, which con-
is not exactly equal to ), smaller reduces the contri- sists of a square active area divided by multiple Manhattan-ori-
bution of the mismatch effect to the total noise figure. entated polysilicon gates partitioning the source/drain diffusion
Fig. 3 shows the high-frequency noise properties at 2-GHz regions. This layout allows the source/drain diffusion area to be
and the cut-off frequency as functions of unit finger length shared by more transistor gates to reduce the total transistor ac-
for the 0.35- and 0.18- m technologies. is degraded tive area and source/drain diffusion capacitance. The corners of
when decreases, which is due to the increase of the para- the metal covering the contacts are clipped to reduce the metal
sitic gate capacitances. Fig. 4 shows the NF and the as line spacing. The minimum size of the waffle unit cell is re-
functions of the for the two processing technologies. For stricted by the first layer metal width and the spacing, thus the
the 0.35 m technology, the that minimizes the NF polysilicon gate pitch is larger than the minimum dimension al-
is around 7 m. When the unit finger length is below 7 m, lowed. The unit cell can be duplicated in the diagonal exten-
substrate effects influence the NF , hence NF increases sion directions to achieve the desired device width as shown in
with the increase of . However, the unit finger length Fig. 5. Depending on the total width of transistors, other struc-
that maximizes is around 2.2 m regardless of the device tures with n-by-n 3 unit cell configuration can be applied.
sizes. Therefore, the tradeoff between the NF minimization Fig. 6 shows the 3-by-3 [Fig. 6(a)], 4-by-4 [Fig. 6(b)] and 5-by-5
and maximization should be considered during the deter- [Fig. 6(c)] waffle unit cells investigated in this work. One draw-
mination of the optimal unit finger length. Table I summarizes back of the waffle layout is that the device width is restricted
the detailed results of simulation for the 200- m devices. to some discrete values. In general, however, the restriction of
2756 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 12, DECEMBER 2005

Fig. 4. Simulated maximum oscillation frequency f and minimum

noise figure NF as a function of the unit finger length for the multifinger
MOSFETs. Different unit finger lengths are found for the minimization of
NF and the maximization of f .Devices are biased at V = 1V
and V = 2 V with the standard 0.35-m and 0.18-m technologies. The
operating frequency for NF is chosen as a typical value 2 GHz.

Fig. 5. Layout of the waffle MOSFET with Manhattan-oriented polysilicon

gates. A 3-by-3 unit cell is demonstrated. Wide devices can be obtained by Fig. 6. Three kinds of unit cell configurations for n-by-n waffle MOSFETs:
duplicating the unit cell in the diagonal direction. (a) 3-by-3, (b) 4-by-4, and (c) 5-by-5.

device width is not important because it can be overcome by

(17) is used. With the increase of , increases while de-
tuning the parameters of the other components in RF ICs.
creases when the device width is kept constant. The resulting
For a given device width, a waffle MOSFET with 5-by-5
NF is about the same for the three waffle MOSFETs with
unit cell configuration requires the fewest number of unit cells
different unit cells, as shown in Table I. As a result, the waffle
among the three structures in our paper. It is equivalent to the
MOSFET with the 3-by-3 configuration is the optimal waffle
multifinger case with long fingers. Similarly, the of a 5-by-5
layout structure. The simulated performance of the waffle MOS-
waffle MOSFET is the least susceptible to the gate parasitic
FETs based on experimentally extracted parameter in this paper
components among the three configurations. Compared with
is shown in Table I.
4-by-4 and 3-by-3 structures, the improvement in using the
5-by-5 configuration is not significant due to the process tech-
nology used in this paper. On the other hand, using a larger unit V. COMPARISON BETWEEN MULTIFINGER MOSFETS AND
cell makes a waffle MOSFET less compact and increases the WAFFLE MOSFETS
gate resistance . Fig. 7 shows the experimentally measured To compare the performance of MOSFETs with different lay-
and gate resistance with different device sizes fabricated outs, 200- m MOSFETs with 24 fingers, 48 fingers, and 3-by-3
with the 0.35- m technology. The figure indicates that is waffle layout are fabricated in a 0.35- m technology. Fig. 8
strongly correlated with . Therefore, the 3-by-3 structure of- shows the measured and at 1 V and
fers the highest among the three configurations. To esti- 2 V. The performance of the waffle MOSFET is comparable to
mate the minimum noise figure NF of the waffle MOSFET, that of the multifinger MOSFETs, but can be layout in a much
WU et al.: EFFECTS OF LAYOUT METHODS OF RF CMOS ON NOISE PERFORMANCE 2757

TABLE II
AVERAGE VALUES OF THE EXTRACTED PARAMETERS FOR THE 3-BY-3 WAFFLE
AND MULTIFINGER n-MOSFETS BIASED AT V = 1 V AND V = 2 V. THE
TRANSCONDUCTANCES g =W FOR THE 3-BY-3 WAFFLE AND MULTIFINGER
n-MOSFETS ARE EQUAL TO 150 mS/mm. THE DEVICE WIDTHS ARE 200 m
FOR THE THREE MOSFETS WITH THE 0.35-m CHANNEL LENGTH

Fig. 7. Measured f (solid symbol and solid line) and the gate resistance
R (hollow symbol and dashed line) as a function of device width for the 3-by-3,
4-by-4, and 5-by-5 waffle MOSFETs. Devices are biased at V = 1 V and
V = 2 V in the 0.35-m technology. 3-by-3 waffle MOSFET gives largest
f and smallest R due to the most compact structure feature among the
three devices.

Fig. 8. Measured jH j and MSG/MAG at V = 1 V and V =2 V in the

0.35-m technology. The previous simulation results match the measured f
and f . The waffle MOSFET shows a higher maximum oscillation frequency
(f ) than those multifinger MOSFETs in small-signal applications.

smaller area. From the experimental data, the extracted parame-

ters, based on the model given in Fig. 1, are listed in Table II. The
value of is found to be 0.048, which is much smaller
than one even at the 10-GHz operating frequency. It justified our
assumption of 1 as discussed in Section II.
For fairness in the comparisons, we compared the waffle
MOSFETs with multifinger MOSFETs with the same width
while the number of fingers is chosen to given the optimal
performance based on the extracted parameters. For waffle Fig. 9. Comparison results of the 3-by-3 waffle MOSFETs and multifinger
layout structures, the optimal overall performance is provided counterparts (N = 30 and N = 90) used in LNA. (a) Schematic of
inductively degenerated single-ended LNA. (b) Simulated LNA noise figure
by 3-by-3 waffle MOSFETs. For the multifinger MOSFETs, and S at 5.2 GHz.
maximization of and minimization of NF are achieved
at the different number of fingers. The calculated and Because of low Q factors of on-chip passive components,
NF are listed in Table I. The 3-by-3 MOSFETs achieve the noise reduction for noise sensitive circuits such as low-noise
optimum or even better performance in terms of , and amplifier (LNA) is extremely important. The impact of different
NF even when the multifinger MOSFETs are individually layout methods on the performance of an inductively degen-
optimized. As and NF cannot be optimized together, erated single-ended LNA is studied. Fig. 9(a) gives the LNA
the waffle MOSFET provides a way to achieve both. schematic with RLC components indicated in the figure. Based
2758 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 12, DECEMBER 2005

maximum 90 , the waffle layout also provides a

lower noise figure, which is due to the higher and the lower
NF of waffle MOSFETs. Furthermore, the larger periphery
of 90-finger multifinger devices adopted in RF ICs results in
additional parasitic inductances and capacitances.

VI. CONCLUSION
In this paper, we studied the design of RF devices and trade-
offs between the gain and noise performance. Two different
layout methods, namely the multifinger MOSFETs and a more
compact waffle MOSFET, were optimized and compared.
The advantages of waffle layout devices were demonstrated
especially from the low-noise aspect. Compared with multi-
Fig. 10. Voltage gains of LNA using waffle MOSFETs and LNA using
finger devices configured with NF optimization, the waffle
multifinger MOSFETs (N = 30 and N = 90) under varying operating MOSFETs provided larger and with almost the same
frequencies. NF . The result is based on extracted experimental data
from a 0.35- m process and is applied to a transistor model.
on physically extracted device parameters, the comparison of Through simulation, we verified that about 10% reduction in
LNAs constructed by the different layout methods is performed the noise figure of a CMOS LNA can be achieved when the
through circuit simulation with Cadence SpectreRF. The device waffle MOSFETs are used instead of multifinger devices.
widths of , and in the schematic of LNA are 200,
200, and 2.8 m, with 0.35- m channel length. All parasitic
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WU et al.: EFFECTS OF LAYOUT METHODS OF RF CMOS ON NOISE PERFORMANCE 2759

Wen Wu (S’00) received the B.S. degree in elec- Mansun Chan (S’92–M’95–SM’01) received the
trical engineering from Fudan University, Shanghai, B.S. degree in electrical engineering (with highest
China, in 2002. She is currently pursuing the Ph.D. honors) and the B.S. degree in computer sciences
degree in electrical and electronic engineering at the (with highest honors) from the University of Cal-
Hong Kong University of Science and Technology, ifornia at San Diego, La Jolla, in 1990 and 1991,
Kowloon. respectively, and the M.S. and Ph.D. degrees from
Her research interests include high-performance the University of California, Berkeley, in 1994 and
RF CMOS device characterization and modeling, 1995, respectively.
design of RF/microwave ICs, and CMOS fabrication During his undergraduate study, he worked with
technologies. Rockwell International Laboratory on HBT mod-
eling, where he developed the self-heating SPICE
model for HBT. His research at Berkeley covered a broad area in silicon devices
ranging from process development to device design, characterization, and
Sang Lam was born in China and raised in Hong modeling. A major part of his work was on the development of record-breaking
Kong. He received the B.Eng. and M.Phil degrees SOI technologies. He has also maintained a strong interest in device modeling
from the Department of Electrical and Electronic En- and circuit simulation. He is one of the major contributors to the unified BSIM3
gineering, and the M.Sc. degree in physics from the model for SPICE, which has been accepted by most U.S. companies, and
Hong Kong University of Science and Technology SEMATECH as an industrial standard model. In January 1996, he joined the
(HKUST), Kowloon, in 1999, 2001, and 2003, re- faculty of The Hong Kong University of Science and Technology, Kowloon,
spectively. Hong Kong, where he is currently an Associate Professor. His research interests
Upon graduation, he remained in Prof. M. Chans include nanodevice technologies, image sensors, SOI technologies, high-per-
research group as full-time Research Staff. In Au- formance IC, 3D Circuit Technology, device modeling and Nano BIOMEMS
gust 2003, he joined the YMCA of Hong Kong Chris- technology. In July 2001, he became a Visiting Professor at the University of
tian College as a Founding Teacher. He taught various California at Berkeley, and the Co-Director of the BSIM program there. He
science subjects including physics, mathematics, and computer and informa- currently holds three U.S. patents. He is a Distinguished Lecturer for the IEEE.
tion technology at senior forms as well as integrated science at junior forms. Dr. Chan received the UC Regents Fellowship, the Golden Keys Scholarship
After teaching one year, he returned to HKUST and joined the newly founded for Academic Excellence, the SRC Inventor Recognition Award, the Rockwell
Microsystems Packaging Institute of the Research And Development Depart- Research Fellowship, and the R&D 100 Award (for the BSIM3v3 project), as
ments Applied Technology Center. Currently, he is an Assistant Scientific Of- well as the Teaching Excellence Appreciation Award (1999).
ficer working on the research and development of RF systems packaging.