Step 1: select Vivado 2016.
2 from Desktop
Step 2: click “create new project” from Quick start
Step 3: Click “Next” in the icon Create a New Vivado Project
Step 4: Enter project name and also select proper project location. Then click “Next”
For Ex: C:/Users/Administrator/Desktop/test
Step 5: Select RTL project and then click “Next”
Step 6: Select Parts and type XC7a35tcpg236-1 in the search line and then click “Next”
Step 7: New project summary gets displayed and click “Finish “
Step 8: The below window gets displayed
Step 9: Select Add Sources at left corner and select “Add or create design source” and then click “Next”
Step 10: Select “ create file”
Step 11: After Selecting create file, enter File name as ”Halfadder” and then click “ok”
Step 12: File name gets displayed and then click “Finish”
Step 13: Define Module name with input and output ports
Step 14: Define input and output ports. Then click “OK”
Step 15: Filename is visible now
Step 16: Verilog Code is written
Step 17: Goto “Add sources” and select “add or create simulation source”. Then click “Next”
Step 18: Select Create Source file and enter file name as “ adder_tb”. Then Click “ok”
Step 19
-Select Create Source file and enter file name as “ adder_tb”. Then Click “ok”
-Assigning input and output ports are not needed for testbench. Then click “Finish”
-Type testbench Code for design file “adder” as shown below.
Step 20: Select adder_tb code and click “ Run Simulation”
Step 21: Select adder_tb code and click “ Run Simulation—Run Behavioral simulation”
Step 22: Select “ RTL analysis” and and click “ elaborated design”. Now Schematic of design is visible.
Step 23: Under Project summary : Post-Implementation results with LUT and IOs are available.
Step 24: Desktop: open Folder “Test” ---click folder Adder—and then track Vivado Project file with
filename “adder” as shown below.
