4.
ADVANCE IN MATERIALS
As silicon transistors approach their limits, researchers are
exploring carbon nanotube field-effect transistors (CNFETs) for
their potential. However, challenges remain in placing
nanotubes precisely, ensuring uniform orientation, and doping
them. A recent MIT-Analog Devices collaboration developed a
16-bit carbon nanotube processor by using a silicon surface
with metal features to align multiple nanotubes, eliminating the
need for individual placement. To advance semiconductor
technology, improving wafer processing techniques like
coating, polishing, and deposition is also essential for boosting
device performance and mobility.
5. Advances in Transistor Structure
To improve transistor performance, there are efforts to
enhance the structures at different stages: front-end-of-line
(FEOL), middle-of-line (MOL), and back-end-of-line (BEOL). As
transistors shrink, scaling down gate lengths increases leakage
currents and reduces the difference between the ON and OFF
states due to effects like drain-induced barrier lowering (DIBL)
and other short-channel effects (SCE). To address this,
increasing the gate-to-channel capacitance can help, and high-
k gate insulators boost capacitance. However, below 28-25 nm,
these issues worsen. Ultimately, current transistor designs aim
for the highest current ratio, which today is around 10.
Fig. 1. Various MOSFET Types
5.1FINFET
FinFETs, introduced in 2011, use a 3D structure where the
gate surrounds the channel, improving control over current
and reducing resistance. As technology advances, the "fin"
becomes thinner, but shrinking it too much can lower carrier
mobility and make manufacturing harder. By 2019, experts
estimated the smallest FinFET could have two fins spaced just
5 nm apart. However, as fins get closer, lithography limitations
make it harder to scale further. At 3 nm nodes and beyond,
designers must choose between continuing with FinFETs or
switching to alternatives like GAAFETs or MBC FETs, with new
materials like germanium offering potential but also
challenges.
5.2GAAFET and MBCFET
In general, GAAFETs (Gate-All-Around FETs) offer better
performance than FinFETs. For example, a 3 nm GAAFET has a
lower threshold voltage and can reduce power consumption by
15-20% compared to a 3 nm FinFET. However, both GAAFETs
and FinFETs share similar
back-end-of-line (BEOL) and middle-of-line (MOL) processes,
which limits the performance improvement to around 8%.
The BEOL step is crucial in semiconductor manufacturing,
where tiny metal interconnects are created to link various parts
of the chip. As technology scales down, these metal wiring
systems become more congested, leading to increased
resistance and capacitance. This results in delays (RC delay)
that affect the performance of electronic chips, and addressing
this challenge is critical as nodes shrink.
5.3 NSFET/MBCFET
As FinFETs reach their limits, chipmakers are turning to
NSFETs (Nano-Sheet FETs), which are like sideways
FinFETs with stacked
horizontal sheets. Each sheet has its own channel, and a gate
surrounds all sides, offering better performance and lower
leakage. These sheets are typically 12-16 nm wide and 5 nm
thick, and wider sheets allow for higher current.
Despite their advantages, NSFETs face challenges like n/p
imbalance, gate control, and fabrication issues such as line
edge roughness. While NSFETs are more resistant to some
variations than nanowire FETs (NWFETs), NWFETs perform
better in other areas like sub-threshold slope.
Samsung’s 3 nm multi-bridge channel FETs (MBCFETs) marked
the start of NSFETs in industry. Research groups like IMEC are
working on advanced designs, such as CFETs, which combine
both n-type and
p-type channels to save space and boost efficiency.
6. DISCUSSION
Semiconductor manufacturing has advanced through process
improvements and structural innovations. Transistor channel
lengths have shrunk from micrometers to nanometers, and
planar transistors have evolved into complex designs like tri-
gate FinFETs for better current control. To continue Moore's
Law, breakthroughs in device architecture and EUV lithography
are needed.
As FinFETs scale down, performance suffers, leading to designs
like vertically stacked nanosheet devices and complementary
FETs (CFETs), which use 3D stacking for smaller, more efficient
cells. While transistor density increases, performance gains are
slowing due to challenges in lowering voltage. Materials like
tungsten disulfide (WS2) are being explored for better scaling
than silicon.
In addition to Front-End-Of-Line (FEOL) advancements,
Back-End-Of-Line (BEOL) issues like routing congestion and RC
delays are becoming bottlenecks. Hybrid metallization with
materials like ruthenium and molybdenum, along with new
alloys replacing copper, are being researched to improve
conductivity and reduce resistance.
