Computer Organization and Architecture

JAIN COLLEGE OF ENGINEERING

DEPARTMENT OF COMPUTER SCINCE & ENGG

SUBJECT COMPUTER ORGANIZATION AND ARCHITECTURE

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MODULE 3 : MEMORY SYSTEM

Module 3 syllabus
Memory System: Basic Concepts, Semiconductor RAM Memories, Read Only Memories, Speed, Size,
and Cost, Cache Memories – Mapping Functions,
Textbooks
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Computer Organization, 5th Edition, Tata McGraw
Hill

BASIC CONCEPTS
• Maximum size of memory that can be used in any computer is determined by addressing mode.

• If MAR is k-bits long then

Figure 3.1: Connection of the memory of the processor

→ memory may contain upto 2K addressable-locations

• If MDR is n-bits long, then
→ n-bits of data are transferred between the memory and processor.
• The data-transfer takes place over the processor-bus (Figure 3.1).
• The processor-bus has
1) Address-Line
2) Data-line &

3) Control-Line (R/W‟, MFC – Memory Function Completed).

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• The Control-Line is used for coordinating data-transfer.

• The processor reads the data from the memory by
→ loading the address of the required memory-location into MAR and
→ setting the R/W‟ line to 1.
• The memory responds by
→ placing the data from the addressed-location onto the data-lines and
→ confirms this action by asserting MFC signal.
• Upon receipt of MFC signal, the processor loads the data from the data-lines into MDR.
• The processor writes the data into the memory-location by
→ loading the address of this location into MAR &
→ setting the R/W‟ line to 0.
• Memory Access Time: It is the time that elapses between
→ initiation of an operation &
→ completion of that operation.
• Memory Cycle Time: It is the minimum time delay that required between the initiation of the two
successive memory-operations.

RAM (Random Access Memory)

• In RAM, any location can be accessed for a Read/Write-operation in fixed amount of time,
Cache Memory
 It is a small, fast memory that is inserted between
→ larger slower main-memory and
→ processor.
 It holds the currently active segments of a program and their data.
Virtual Memory
 The address generated by the processor is referred to as a virtual/logical address.
 The virtual-address-space is mapped onto the physical-memory where data are actually stored.
 The mapping-function is implemented by MMU. (MMU = memory management unit).
 Only the active portion of the address-space is mapped into locations in the physical-memory.
 The remaining virtual-addresses are mapped onto the bulk storage devices such as magnetic disk.

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 As the active portion of the virtual-address-space changes during program execution, the MMU
→ changes the mapping-function &
→ transfers the data between disk and memory.
 During every memory-cycle, MMU determines whether the addressed-page is in the memory. If the
page is in the memory.
Then, the proper word is accessed and execution proceeds.
Otherwise, a page containing desired word is transferred from disk to memory.
• Memory can be classified as follows:
1) RAM which can be further classified as follows:
i) Static RAM
ii) Dynamic RAM (DRAM) which can be further classified as synchronous & asynchronous DRAM.
2) ROM which can be further classified as follows:
i) PROM
ii) EPROM
iii) EEPROM &
iv) Flash Memory which can be further classified as Flash Cards & Flash Drives.

SEMI CONDUCTOR RAM MEMORIES

INTERNAL ORGANIZATION OF MEMORY-CHIPS
• Memory-cells are organized in the form of array (Figure 3.2).
• Each cell is capable of storing 1-bit of information.
• Each row of cells forms a memory-word.
• All cells of a row are connected to a common line called as Word-Line.
• The cells in each column are connected to Sense/Write circuit by 2-bit-lines.
• The Sense/Write circuits are connected to data-input or output lines of the chip.
• During a write-operation, the sense/write circuit
→ receive input information &
→ store input info in the cells of the selected word.

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Figure 3.2: Organization of bit cells in a memory chip

• The data-input and data-output of each Sense/Write circuit are connected to a single bidirectional
data-line.
• Data-line can be connected to a data-bus of the computer.
• Following 2 control lines are also used:
1) R/W’ - Specifies the required operation.
2) CS’ - Chip Select input selects a given chip in the multi-chipmemory-system.

Organization for 1k x 1 format is shown below:

• In this case a 10 bit address lines are needed, but there is only one data line, resulting in 15 external
connections. Address lines=10; data line=1; R/W and CS = 2; Power supply & ground=2.
• The required 10 bit address is divided into two groups of 5 bits each to form the row and column
addresses for the cell array. A row address selects a row of 32 cells, all of which can be accessed in parallel.
However according to the column address, only one of these cells is connected to the external data line by

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the output multiplexer and input demultiplexer.

Figure 3.3: Organization of a 1K X 1 memory chip

STATIC MEMORIES
• Memories consist of circuits capable of retaining their state as long as power is applied are known.

Figure 3.4: A static RAM cell

• Two inverters are cross connected to form a latch (Figure 3.4).
• The latch is connected to 2-bit-lines by transistors T1 and T2.
• The transistors act as switches that can be opened/closed under the control of the word-line.
• When the word-line is at ground level, the transistors are turned off and the latch retain its state.
Read Operation

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• To read the state of the cell, the word-line is activated to close switches T1 and T2.
• If the cell is in state 1, the signal on bit-line b is high and the signal on the bit-line b‟ is low.
• Thus, b and b‟ are complement of each other.
• Sense/Write circuit
→ monitors the state of b & b‟ and
→ sets the output accordingly.
Write Operation
• The state of the cell is set by
→ placing the appropriate value on bit-line b and its complement on b‟ and
→ then activating the word-line. This forces the cell into the corresponding state.
• The required signal on the bit-lines is generated by Sense/Write circuit.

Figure 3.5: An example of a CMOS memory cell

CMOS Cell
• Transistor pairs (T3, T5) and (T4, T6) form the inverters in the latch (Figure 3.5).
• In state 1, the voltage at point X is high by having T5, T6 ON and T4, T5 are OFF.
• Thus, T1 and T2 returned ON (Closed), bit-line b and b‟ will have high and low signals respectively.
Advantages:
1) It has low power consumption „.‟ the current flows in the cell only when the cell is active.
2) Static RAM‟s can be accessed quickly. It access time is few nanoseconds.
• Disadvantage: SRAMs are said to be volatile memories „.‟ their contents are lost when power
is interrupted.
ASYNCHRONOUS DRAMS
• Less expensive RAMs can be implemented if simple cells are used.
• Such cells cannot retain their state indefinitely. Hence they are called Dynamic RAM (DRAM).

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• The information stored in a dynamic memory-cell in the form of a charge on a capacitor.

• This charge can be maintained only for tens of milliseconds.
• The contents must be periodically refreshed by restoring this capacitor charge to its full value.

• In order to store information in the cell, the transistor T is turned „ON‟ (Figure 3.6).
• The appropriate voltage is applied to the bit-line which charges the capacitor.
• After the transistor is turned off, the capacitor begins to discharge.
• Hence, info. stored in cell can be retrieved correctly before threshold value of capacitor drops down.
• During a read-operation,
→ transistor is turned „ON‟
→ a sense amplifier detects whether the charge on the capacitor is above the threshold value.
 If (charge on capacitor) > (threshold value) Bit-line will have logic value „1‟.
 If (charge on capacitor) < (threshold value) Bit-line will set to logic value „0‟.

Figure 3.6: A single dynamic memory cell

ASYNCHRONOUS DRAM DESCRIPTION

• The 4 bit cells in each row are divided into 512 groups of 8 (Figure 3.7).
• 21 bit address is needed to access a byte in the memory. 21 bit is divided as follows:
1) 12 address bits are needed to select a row.
i.e. A8-0 → specifies row-address of a byte.
2) 9 bits are needed to specify a group of 8 bits in the selected row.

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i.e. A20-9 → specifies column-address of a byte.

Figure 3.7: Internal organization of a 2MX8 dynamic memory chip

• During Read/Write-operation,
→ row-address is applied first.
→ row-address is loaded into row-latch in response to a signal pulse on RAS’ input of chip. (RAS
= Row-address Strobe CAS = Column-address Strobe)
• When a Read-operation is initiated, all cells on the selected row are read and refreshed.
• Shortly after the row-address is loaded, the column-address is
→ applied to the address pins &
→ loaded into CAS’.
• The information in the latch is decoded.
• The appropriate group of 8 Sense/Write circuits is selected.
R/W’=1(read-operation) - Output values of selected circuits are transferred to data-lines D0-D7.
R/W’=0(write-operation) - Information on D0-D7 are transferred to the selected circuits.
• RAS‟ & CAS‟ are active-low so that they cause latching of address when they change from high
to low.
• To ensure that the contents of DRAMs are maintained, each row of cells is accessed periodically.
• A special memory-circuit provides the necessary control signals RAS‟ & CAS‟ that govern the timing.
• The processor must take into account the delay in the response of the memory.
Fast Page Mode

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 Transferring the bytes in sequential order is achieved by applying the consecutive sequence of
column-address under the control of successive CAS‟ signals.
 This scheme allows transferring a block of data at a faster rate.
 The block of transfer capability is called as fast page mode.
SYNCHRONOUS DRAM
• The operations are directly synchronized with clock signal (Figure 3.8).
• The address and data connections are buffered by means of registers.
• The output of each sense amplifier is connected to a latch.
• A Read-operation causes the contents of all cells in the selected row to be loaded in these latches.
• Data held in latches that correspond to selected columns are transferred into data-outputregister.
• Thus, data becoming available on the data-output pins.
• First, the row-address is latched under control of RAS‟ signal (Figure 3.9).
• The memory typically takes 2 or 3 clock cycles to activate the selected row.
• Then, the column-address is latched under the control of CAS‟ signal.
• After a delay of one clock cycle, the first set of data bits is placed on the data-lines.
• SDRAM automatically increments column-address to access next 3 sets of bits in the selected row.

Figure 3.8: Synchronous DRAM

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Figure 3.9: Burst read of length 4 in an SDRAM

LATENCY & BANDWIDTH
• A good indication of performance is given by 2 parameters: 1) Latency 2) Bandwidth.
Latency
• It refers to the amount of time it takes to transfer a word of data to or from the memory.
• For a transfer of single word, the latency provides the complete indication of memory performance.
• For a block transfer, the latency denotes the time it takes to transfer the first word of data.
Bandwidth
• It is defined as the number of bits or bytes that can be transferred in one second.
• Bandwidth mainly depends on
1) The speed of access to the stored data &
2) The number of bits that can be accessed in parallel.

DOUBLE DATA RATE SDRAM (DDR-SDRAM)

• The standard SDRAM performs all actions on the rising edge of the clock signal.
• The DDR-SDRAM transfer data on both the edges (loading edge, trailing edge).
• The Bandwidth of DDR-SDRAM is doubled for long burst transfer.
• To make it possible to access the data at high rate, the cell array is organized into two banks.
• Each bank can be accessed separately.
• Consecutive words of a given block are stored in different banks.
• Such interleaving of words allows simultaneous access to two words.
• The two words are transferred on successive edge of the clock.

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STRUCTURE OF LARGER MEMORIES

Dynamic Memory System
• The physical implementation is done in the form of memory-modules.
If a large memory is built by placing DRAM chips directly on the Motherboard, then it will occupy large
amount of space on the board.
• These packaging considerations have led to the development of larger memory units known as
SIMM‟s & DIMM‟s.
1) SIMM - Single Inlinememory-module
2) DIMM - Dual Inline memory-module
• SIMM/DIMM consists of many memory-chips on small board that plugs into a socket on motherboard.

Figure 3.10: Organization of a 2M X 32 memory using 512K X 8 memory chips

 Implementing a memory unit of 2M words of 32 bits each.
 Using 512x8 static memory chips. Each column consists of 4 chips. Each chip implements one
byte position.

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 A chip is selected by setting its chip select control line to 1. Selected chip places its data on the
data output line, outputs of other chips are in high impedance state.
 21 bits to address a 32-bit word. High order 2 bits are needed to select the row, by activating the
four Chip Select signals.
 19 bits are used to access specific byte locations inside the selected chip.
MEMORY-SYSTEM CONSIDERATIONS
• To reduce the number of pins, the dynamic memory-chips use multiplexed-address inputs.
• The address is divided into 2 parts:
1) High Order Address Bit
 Select a row in cell array.
 It is provided first and latched into memory-chips under the control of RAS‟signal.
2) Low Order Address Bit
 Selects a column.
 They are provided on same address pins and latched using CAS‟ signals.

Figure 3.11: Use of a memory controller

• The Multiplexing of address bit is usually done by Memory Controller Circuit (Figure 3.11).

• The Controller accepts a complete address & R/W‟ signal from theprocessor.
• A Request signal indicates a memory access operation is needed.
• Then, the Controller
→ forwards the row & column portions of the address to the memory.
→ generates RAS‟ & CAS‟ signals &
→ sends R/W‟ & CS‟ signals to the memory.

RAMBUS MEMORY
• The usage of wide bus is expensive.

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• Rambus developed the implementation of narrow bus.

• Rambus technology is a fast signaling method used to transfer information between chips.
• The signals consist of much smaller voltage swings around a reference voltage Vref.
• The reference voltage is about 2V.
• The two logical values are represented by 0.3V swings above and below Vref.
• This type of signaling is generally is known as Differential Signaling.
• Rambus provides a complete specification for design of communication called as Rambus Channel.
• Rambus memory has a clock frequency of 400 MHz.
• The data are transmitted on both the edges of clock so that effective data-transfer rate is 800MHZ.
Circuitry needed to interface to Rambus channel is included on chip. Such chips are called RDRAM.
(RDRAM = Rambus DRAMs).
• Rambus channel has:

1) 9 Data-lines (1st-8th line ->Transfer the data, 9th line->Paritychecking).

2) Control-Line &
3) Power line.
• A two channel rambus has 18 data-lines which has no separate Address-Lines.
• Communication between processor and RDRAM modules is carried out by means of packets
transmitted on the data-lines.
• There are 3 types of packets:
1) Request
2) Acknowledge &
3) Data.

READ ONLY MEMORIES (ROM)

• Both SRAM and DRAM chips are volatile, i.e. They lose the stored information if power is turned
off. Many application requires non-volatile memory which retains the stored information if power is
turned off.
• For ex:
OS software has to be loaded from disk to memory i.e. it requires non-volatile memory.
• Non-volatile memory is used in embedded system.
• Since the normal operation involves only reading of stored data, a memory of this type is called ROM.

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 At Logic value ‘0’ - Transistor(T) is connected to the ground point(P).

Transistor switch is closed & voltage on bit-line nearly drops to zero (Figure 3.12).
 At Logic value ‘1’ - Transistor switch is open. The
bit-line remains at high voltage.

Figure 3.12: A ROM cell

• To read the state of the cell, the word-line is activated.
• A Sense circuit at the end of the bit-line generates the proper output value.
TYPES OF ROM
• Different types of non-volatile memory are
1) PROM
2) EPROM
3) EEPROM &
4) Flash Memory (Flash Cards & Flash Drives)

PROM (PROGRAMMABLE ROM)

• PROM allows the data to be loaded by the user.
• Programmability is achieved by inserting a „fuse‟ at point P in a ROM cell.
• Before PROM is programmed, the memory contains all 0‟s.
• User can insert 1‟s at required location by burning-out fuse using highcurrent-pulse.
• This process is irreversible.
• Advantages:
1) It provides flexibility.
2) It is faster.
3) It is less expensive because they can be programmed directly by the user.

EPROM (ERASABLE REPROGRAMMABLE ROM)

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• EPROM allows
→ stored data to be erased and
→ new data to be loaded.
• In cell, a connection to ground is always made at „P‟ and a special transistor is used.
• The transistor has the ability to function as
→ a normal transistor or
→ a disabled transistor that is always turned „off‟.
• Transistor can be programmed to behave as a permanently open switch, by injecting charge into it.
• Erasure requires dissipating the charges trapped in the transistor of memory cells.
This can be done by exposing the chip to ultraviolet light.
• Advantages:
1) It provides flexibility during the development phase of the digital system.
2) It is capable of retaining stored information for a long time.
• Disadvantages:
1) The chip must be physically removed from the circuit for reprogramming.
2) The entire contents need to be erased by UV light.
EEPROM (ELECTRICALLY ERASABLE ROM)
• Advantages:
1) It can be both programmed and erased electrically.
2) It allows the erasing of all cell contents selectively.
• Disadvantage: It requires different voltage for erasing, writing and reading the stored data.

FLASH MEMORY
• In EEPROM, it is possible to read & write the contents of a single cell.
• In a Flash device, it is possible to read the contents of a single cell & write entire contents of a block.
• Prior to writing, the previous contents of the block are erased.
Eg. In MP3 player, the flash memory stores the data that represents sound.
• Single flash chips cannot provide sufficient storage capacity for embedded-system.
• Advantages:
1) Flash drives have greater density which leads to higher capacity & low cost per bit.
2) It requires single power supply voltage & consumes less power.
• There are 2 methods for implementing larger memory: 1) Flash Cards & 2) Flash Drives
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1) Flash Cards
 One way of constructing larger module is to mount flash-chips on a small card.
 Such flash-card have standard interface.
 The card is simply plugged into a conveniently accessible slot.
 Memory-size of the card can be 8, 32 or 64MB.
 Eg: A minute of music can be stored in 1MB of memory. Hence 64MB flash cards can store an hour
of music.
2) Flash Drives
 Larger flash memory can be developed by replacing the hard disk-drive.
 The flash drives are designed to fully emulate the hard disk.
 The flash drives are solid state electronic devices that have no movable parts.
Advantages:
1) They have shorter seek & access time which results in faster response.
2) They have low power consumption. .‟. they are attractive for battery driven application.
3) They are insensitive to vibration.
Disadvantages:
1) The capacity of flash drive (<1GB) is less than hard disk (>1GB).
2) It leads to higher cost per bit.
3) Flash memory will weaken after it has been written a number of times (typically at least 1
million times).

SPEED, SIZE COST

The main-memory can be built with DRAM (Figure 3.13)

• Thus, SRAM‟s are used in smaller units where speed is of essence.

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• The Cache-memory is of 2 types:

1) Primary/Processor Cache (Level1 or L1 cache)
 It is always located on the processor-chip.
2) Secondary Cache (Level2 or L2 cache)
 It is placed between the primary-cache and the rest of the memory.
• The memory is implemented using the dynamic components (SIMM, RIMM, DIMM).
Figure 3.13: Memory hierarchy

• The access time for main-memory is about 10 times longer than the access time for L1 cache.
CACHE MEMORIES
• The effectiveness of cache mechanism is based on the property of Locality of Reference’. Locality
of Reference
• Many instructions in the localized areas of program are executed repeatedly during some time period
• Remainder of the program is accessed relatively infrequently (Figure 3.14).
• There are 2 types:
1) Temporal
 The recently executed instructions are likely to be executed again very soon.
2) Spatial
 Instructions in close proximity to recently executed instruction are also likely to be executed soon.
• If active segment of program is placed in cache-memory, then total execution time can be reduced.
• Block refers to the set of contiguous address locations of some size.
• The cache-line is used to refer to the cache-block.

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Figure 3.14: Use of a cache memory

• The Cache-memory stores a reasonable number of blocks at a given time.
• This number of blocks is small compared to the total number of blocks available in main-memory.
• Correspondence b/w main-memory-block & cache-memory-block is specified by mapping-function.
• Cache control hardware decides which block should be removed to create space for the new block.
• The collection of rule for making this decision is called the Replacement Algorithm.
• The cache control-circuit determines whether the requested-word currently exists in the cache.
• The write-operation is done in 2 ways: 1) Write-through protocol & 2) Write-back protocol.
Write-Through Protocol
 Here the cache-location and the main-memory-locations are updated simultaneously.
Write-Back Protocol
 This technique is to
→ update only the cache-location &
→ mark the cache-location with associated flag bit called Dirty/Modified Bit.
 The word in memory will be updated later, when the marked-block is removed from cache.
During Read-operation
• If the requested-word currently not exists in the cache, then read-miss will occur.
• To overcome the read miss, Load–through/Early restart protocol is used.
Load–Through Protocol
 The block of words that contains the requested-word is copied from the memory into cache.
 After entire block is loaded into cache, the requested-word is forwarded to processor.
During Write-operation
• If the requested-word not exists in the cache, then write-miss will occur.
1) If Write Through Protocol is used, the information is written directly into main-memory.
2) If Write Back Protocol is used,
→ then block containing the addressed word is first brought into the cache &

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→ then the desired word in the cache is over-written with the new information.
MAPPING-FUNCTION
• Here we discuss about 3 different mapping-function:
1) Direct Mapping
2) Associative Mapping

3) Set-Associative Mapping

DIRECT MAPPING
• The block-j of the main-memory maps onto block-j modulo-128 of the cache (Figure 3.15).
• When the memory-blocks 0, 128, & 256 are loaded into cache, the block is stored in cache-block 0.
Similarly, memory-blocks 1, 129, 257 are stored in cache-block 1.
• The contention may arise when
1) When the cache is full.
2) When more than one memory-block is mapped onto a given cache-block position.
• The contention is resolved by allowing the new blocks to overwrite the currently resident-block.
• Memory-address determines placement of block in the cache.

Figure 3.15: Direct-mapped cache

• The memory-address is divided into 3 fields:
1) Low Order 4 bit field
 Selects one of 16 words in a block.

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2) 7 bit cache-block field

 7-bits determine the cache-position in which new block must be stored.
3) 5 bit Tag field
 5-bits memory-address of block is stored in 5 tag-bits associated with cache-location.
• As execution proceeds, 5-bit tag field of memory-address is compared with tag-bits associated with
cache-location. If they match, then the desired word is in that block of the cache.
Otherwise, the block containing required word must be first read from the memory. And then the word
must be loaded into the cache.

ASSOCIATIVE MAPPING
• The memory-block can be placed into any cache-block position. (Figure 3.16).
• 12 tag-bits will identify a memory-block when it is resolved in the cache.
• Tag-bits of an address received from processor are compared to the tag-bits of each block of cache.
• This comparison is done to see if the desired block is present.

Figure 3.16: Associative-mapped cache

• It gives complete freedom in choosing the cache-location.
• A new block that has to be brought into the cache has to replace an existing block if the cache is full.
• The memory has to determine whether a given block is in the cache.
• Advantage: It is more flexible than direct mapping technique.
• Disadvantage: Its cost is high.

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SET-ASSOCIATIVE MAPPING
• It is the combination of direct and associative mapping. (Figure 3.17).
• The blocks of the cache are grouped into sets.
• The mapping allows a block of the main-memory to reside in any block of the specified set.
• The cache has 2 blocks per set, so the memory-blocks 0, 64, 128…....... 4032 maps into cache set 0
• The cache can occupy either of the two block position within the set.
6 bit set field -Determines which set of cache contains the desired block.
6 bit tag field - The tag field of the address is compared to the tags of the two blocks of the set.
 This comparison is done to check if the desired block is present.

Figure 3.17: Set-associative mapped cache with two blocks per set
• The cache which contains 1 block per set is called direct mapping.
• A cache that has „k‟ blocks per set is called as“k-way set associative cache‟.
• Each block contains a control-bit called a valid-bit.
• The Valid-bit indicates that whether the block contains valid-data.
• The dirty bit indicates that whether the block has been modified during its cache residency.
Valid-bit=0 When power is initially applied to system.

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Valid-bit=1 When the block is loaded from main-memory at first time.

• If the main-memory-block is updated by a source & if the block in the source is already exists in
the cache, then the valid-bit will be cleared to “0‟.
• If Processor & DMA uses the same copies of data then it is called as Cache Coherence Problem.
• Advantages:
1) Contention problem of direct mapping is solved by having few choices for block placement.
2) The hardware cost is decreased by reducing the size of associative search.

REPLACEMENT ALGORITHM
• In direct mapping method, the position of each block is pre-determined and there is no need of replacement
strategy.
• In associative & set associative method, the block position is not pre-determined. If the cache is full and
if new blocks are brought into the cache, then the cache-controller must decide which of the old blocks
has to be replaced.
• When a block is to be overwritten, the block with longest time w/o being referenced is over-written.
• This block is called Least recently Used (LRU) block & the technique is called LRU algorithm.
• The cache-controller tracks the references to all blocks with the help of block-counter.
• Advantage: Performance of LRU is improved by randomness in deciding which block is to be
over- written.
Eg:
Consider 4 blocks/set in set associative cache.
 2 bit counter can be used for each block.
 When a ‘hit’ occurs, then block counter=0; The counter with values originally lower than
the referenced one are incremented by 1 & all others remain unchanged.
 When a ‘miss’ occurs & if the set is full, the blocks with the counter value 3 is removed, the
new block is put in its place & its counter is set to “0‟ and other block counters are incremented
by 1.

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Module 3 Questions
1 Explain synchronous DRAMS with a block diagram.
2 With a diagram, explain the internal organization of 2M X 8 asynchronous DRAM chip.
3 With diagram, describe the internal organization of a 128 X 8 memory chip.
4 With a neat diagram, explain the design of 2M X 32 memory module using 1M X 8 memory chips.
5 Draw and explain the working of 16 Mega Bit DRAM chip configured as 2M X 8.
6 Describe organization of a 2M X 32 memory using 512K X 8 memory chips.
7 With diagram of basic SRAM (Static RAM) and DRAM (Asynchronous DRAM) chip (cell), explain
the read and write operations on each of them.
8 Define ROM. Explain various types of ROMs.
9 Define cache memory, explain various types of it with neat block diagram.
10 Describe any 2 mapping functions in cache. (with diagram)
11 Explain Associative mapping technique and set associative mapping technique.
12 Explain in detail the working of set associative mapped cache with 2 blocks per set with relevant
diagram.

Dept. of CSE, JCE BELGAVI 24