Unit 5 : Processor

Instructions & Processor

Enhancement
 Elements of a Machine Instruction

•Operation code: Specifies the operation to be performed (e.g., ADD, I/O).

The operation is specified by a binary code, known as the operation code, or
opcode.
•Source operand reference: The operation may involve one or more source
operands, that is, operands that are inputs for the operation.

•Result operand reference: The operation may produce a result.

•Next instruction reference: This tells the processor where to fetch the next
instruction after the execution of this instruction is complete.
Instruction Format:-
Instruction is a command to microprocessor to perform a given task
on a specified data.

Each instruction has two parts :-

□ One is the task to be performed called Operational code
(OPCODE)

□ Second is the data to be operated on called Operand.

TYPES OF OPERATIONS
The number of different opcodes varies widely from machine to
machine. However, the same general types of operations are
found on all machines. A useful and typical categorization is the
following:

□ Data transfer
□ Arithmetic
□ Logical
□ Conversion
□ I/O
□ System control
□ Transfer of control
Addressing Modes :-
The different ways in which
the location of an operand is
specified in an instruction
are referred to as addressing
modes. It is a method used
to determine which part of
memory is being referred by
a machine instruction
□ Register mode
Operand is the content of a processor register. The register name/address is given
in the instruction. Value of R2 is moved to R1.

Example: MOV R1, R2

□ Absolute mode (direct)
Operand is in the memory location. Address of the location is given explicitly.
Here value in A is moved to 1000H.

Example: MOV 1000, A

□ Immediate mode:
Address and data constants can be given explicitly in the instruction. Here value
constant 200 is moved to R0 register.

Example: MOV #200, R0

□ Indirect Mode:
The processor will read the register content (R1) in this case, which will not have
direct value. Instead, it will be the address or location in which, the value will be
stored. Then the fetched value is added with the value in R0 register.
□ Example: ADD (R1), R0

□ Indexed / Relative Addressing Mode:

The processor will take R1 register address as base address and adds the value
constant 20 (offset / displacement) with the base address to get the derived or actual
memory location of the value i.e., stored in the memory. It fetches the value then adds
the value to R2 register.
□ Example: ADD 20(R1), R2

□ Auto increment mode and Auto decrement Mode:

The value in the register / address that is supplied in the instruction is incremented or
decremented.
Ex: Increment R1 (Increments the given register / address content by one)
Ex: Decrement R2 (Decrements the given register / address content by one
 Addressing modes Example Meaning When used
Instruction

Register Add R4,R3 R4 <- R4 + R3 When a value is in a register

Immediate Add R4, #3 R4 <- R4 + 3 For constants
Displacement Add R4, 100(R1) R4 <- R4 + M[100+R1] Accessing local variables
Register Add R4,(R1) R4 <- R4 + M[R1] Accessing using a pointer or a
deffered computed address

Useful in array addressing: R1 - base

Indexed Add R3, (R1 + R2) R3 <- R3 + M[R1+R2] of array
R2 - index amount

Direct Add R1, (1001) R1 <- R1 + M[1001] Useful in accessing static data
Memory If R3 is the address of a
deferred Add R1, @(R3) R1 <- R1 + M[M[R3]] pointer p, then mode yields *p

Useful for stepping through arrays in a

Auto- increment R1 <- R1 +M[R2] R2 <- R2 loop.
Add R1, (R2)+ +d R2 - start of array
d - size of an element

Same as autoincrement. Both can also

Auto- decrement R2 <-R2-d be used to implement a stack as push
Add R1,-(R2) R1 <- R1 + M[R2] and pop

Used to index arrays. May be applied to

Add R1, R1<- R1+M[100+R2+R3*d] any base addressing mode in some
Scaled 100(R2)[R3] machines.
Reduced Instruction Set Computer (RISC)
□ In Reduced Instruction Set Computer (RISC) architecture, the
instruction set of the computer is simplified to reduce the execution
time.
□ RISC has a small set of instructions, which generally include
register-to-register operations.
□ In RISC, all instructions have simple register addressing and hence
use less number of addressing modes.
Complex Instruction Set Computer CISC :-
□ It comprises a complex instruction set. It incorporates a
variable-length instruction format. Instructions that require register
operands may take only two bytes.
□ If the computer has 32-bit words (four bytes), the first instruction
occupies half a word, while the second instruction needs one word
in addition to one byte in the next word. Packing variable
instruction formats in a fixed-length memory word require special
decoding circuits that count bytes within words and frame the
instructions according to their byte length.
Interrupt in Computer Architecture :-
□ An interrupt is an event that alters the sequence in which the processor
executes instructions.
□ An interrupt might be planned (specifically requested by the currently
running program) or unplanned (caused by an event that might or might
not be related to the currently running program).
 Types of interrupts
Interrupts are classified into two types:
I. Hardware interrupt
A hardware interrupt is an electronic signal from an external hardware device that
indicates it needs attention from the OS.
Example of this is moving a mouse or pressing a keyboard key. In these examples of
interrupts, the processor must stop to read the mouse position or keystroke at that
instant.
In this type of interrupt, all devices are connected to the Interrupt Request Line (IRL).
Typically, a hardware IRQ has a value that associates it with a particular device. This
makes it possible for the processor to determine which device is requesting service by
raising the IRQ, and then provide service accordingly.
There are two types of hardware interrupts:
Maskable interrupts
In a processor, an internal interrupt mask register selectively enables and
disables hardware requests. When the mask bit is set, the interrupt is
enabled. When it is clear, the interrupt is disabled. Signals that are affected
by the mask are maskable interrupts.

Non-maskable interrupts
In some cases, the interrupt mask cannot be disabled so it does not affect
some interrupt signals. These are non-maskable interrupts and are usually
high-priority events that cannot be ignored.
II. Software interrupts
□ A software interrupt occurs when an application program terminates or
requests certain services from the OS. Usually, the processor requests
a software interrupt when certain conditions are met by executing a
special instruction. This instruction invokes the interrupt and functions
like a subroutine call.
□ Software interrupts are commonly used when the system interacts with
device drivers or when a program requests OS services.
□ In some cases, software interrupts may be triggered unexpectedly by
program execution errors rather than by design. These interrupts are
known as exceptions or traps.
Exception :-
An exception is an unexpected event from within the processor.
Interrupt is an unexpected event from outside the process.
Instruction Pipelining :-
Pipeline processing can happen not only in the data stream but also in the instruction
stream. To perform tasks such as fetching, decoding and execution of
instructions, most digital computers with complicated instructions would require an
instruction pipeline.
In general, each and every instruction must be processed by the computer in the
following order:
1. Fetching the instruction from memory
2. Decoding the obtained instruction
3. Calculating the effective address
4. Fetching the operands from the given memory
5. Execution of the instruction
6. Storing the result in a proper place
Pipelining hazards
Whenever any pipeline needs to stall due to any reason, it is known
as a pipeline hazard. Some of the pipelining hazards are data
dependency, memory delay, branch delay, and resource limitation.
□ Structural Hazard
□ Hardware resource conflicts among the instructions in the pipeline cause
structural hazards.
□ Memory, a GPR Register, or an ALU might all be used as resources here.
When more than one instruction in the pipe requires access to the very same
resource in the same clock cycle, a resource conflict is said to arise. In an
overlapping pipelined execution, this is a circumstance where the hardware
cannot handle all potential combinations.
Data Hazards :-
Data hazards in pipelining emerge when the execution of one instruction is
dependent on the results of another instruction that is still being processed in
the pipeline.
The order of the READ or WRITE operations on the register is used to
classify data threats into three groups.
1. read-after-write (RAW),
2. write-after-read (WAR),
3. write-after-write (WAW).
Control Hazards
Branch hazards are caused by branch instructions and are known as
control hazards in computer architecture. The flow of program/instruction
execution is controlled by branch instructions.
Multiprocessor
Most computer systems are single processor systems i.e they only have one
processor. However, multiprocessor or parallel systems are increasing in
importance nowadays. These systems have multiple processors working in parallel
that share the computer clock, memory, bus, peripheral devices etc.