New Product

SiS406DN
Vishay Siliconix

N-Channel 30-V (D-S) MOSFET

PRODUCT SUMMARY FEATURES

VDS (V) RDS(on) (Ω) ID (A) • Halogen-free
0.011 at VGS = 10 V
• TrenchFET® Power MOSFET
14
30 • PWM Optimized RoHS
0.0145 at VGS = 4.5 V 12.2
• New Low Thermal Resistance PowerPAK® COMPLIANT

Package with Low 1.07 mm Profile

• 100 % Rg Tested
• 100 % UIS Tested
APPLICATIONS
PowerPAK 1212-8 • Adaptor Switch
• Load Switch

3.30 mm S
3.30 mm D
1
S
2
S
3
G
4
D
8
D
7
G
D
6
D
5

Bottom View
S
Ordering Information: SiS406DN-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFET

ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted

Parameter Symbol 10 s Steady State Unit
Drain-Source Voltage VDS 30
V
Gate-Source Voltage VGS ± 25
TA = 25 °C 14 9
Continuous Drain Current (TJ = 150 °C)a ID
TA = 70 °C 12.2 7.3
Pulsed Drain Current IDM 50 A
Continuous Source Current (Diode Conduction)a IS 3.3 1.4
Single Pulse Avalanche Current IAS 20
L = 0.1 mH
Avalanche Energy EAS 20 mJ
TA = 25 °C 3.7 1.5
Maximum Power Dissipationa PD W
TA = 70 °C 2.3 1.0
Operating Junction and Storage Temperature Range TJ, Tstg - 55 to 150
°C
Soldering Recommendations (Peak Temperature)b, c 260

THERMAL RESISTANCE RATINGS

Parameter Symbol Typical Maximum Unit
t ≤ 10 s 28 34
Maximum Junction-to-Ambienta RthJA
Steady State 66 81 °C/W
Maximum Junction-to-Case (Drain) Steady State RthJC 2.0 2.4
Notes:
a. Surface Mounted on 1" x 1" FR4 board.
b. See Solder Profile (http://www.vishay.com/ppg?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed
copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and
is not required to ensure adequate bottom side solder interconnection.
c. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.

Document Number: 68805 www.vishay.com

S-82301-Rev. A, 22-Sep-08 1
 New Product
SiS406DN
Vishay Siliconix

SPECIFICATIONS TJ = 25 °C, unless otherwise noted

Parameter Symbol Test Conditions Min. Typ. Max. Unit
Static
Drain-Source Breakdown Voltage VDS VGS = 0 V, ID = 250 µA 30 V
VDS Temperature Coefficient ΔVDS/TJ 32
ID = 250 µA mV/°C
VGS(th) Temperature Coefficient ΔVGS(th)/TJ - 6.6
Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA 1.0 3.0 V
Gate-Source Leakage IGSS VDS = 0 V, VGS = ± 25 V ± 100 nA
VDS = 30 V, VGS = 0 V 1
Zero Gate Voltage Drain Current IDSS µA
VDS = 30 V, VGS = 0 V, TJ = 55 °C 10
On-State Drain Currenta ID(on) VDS ≥ 5 V, VGS = 10 V 30 A
VGS = 10 V, ID = 12 A 0.0088 0.011
Drain-Source On-State Resistancea RDS(on) Ω
VGS = 4.5 V, ID = 10 A 0.0115 0.0145
Forward Transconductancea gfs VDS = 15 V, ID = 12 A 32 S
b
Dynamic
Input Capacitance Ciss 1100
Output Capacitance Coss VDS = 15 V, VGS = 0 V, f = 1 MHz 215 pF
Reverse Transfer Capacitance Crss 95
VDS = 15 V, VGS = 10 V, ID = 16 A 18.2 28
Total Gate Charge Qg
8.4 13
nC
Gate-Source Charge Qgs VDS = 15 V, VGS = 4.5 V, ID = 16 A 2.9
Gate-Drain Charge Qgd 2.4
Gate Resistance Rg f = 1 MHz 0.45 2.2 4.4 Ω
Turn-On Delay Time td(on) 10 20
Rise Time tr VDD = 15 V, RL = 15 Ω 10 20
Turn-Off Delay Time td(off) ID ≅ 1 A, VGEN = 10 V, Rg = 1 Ω 22 35
Fall Time tf 8 16
ns
Turn-On Delay Time td(on) 20 35
Rise Time tr VDD = 15 V, RL = 15 Ω 12 24
Turn-Off Delay Time td(off) ID ≅ 1 A, VGEN = 4.5 V, Rg = 1 Ω 25 40
Fall Time tf 12 24
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current IS TC = 25 °C 16
A
Pulse Diode Forward Currenta ISM 50
Body Diode Voltage VSD IS = 2.3 A 0.75 1.1 V
Body Diode Reverse Recovery Time trr 20 40 ns
Body Diode Reverse Recovery Charge Qrr 12 25 nC
IF = 3.2 A, dI/dt = 100 A/µs, TJ = 25 °C
Reverse Recovery Fall Time ta 11
ns
Reverse Recovery Rise Time tb 9
Notes:
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %.
b. Guaranteed by design, not subject to production testing.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

www.vishay.com Document Number: 68805

2 S-82301-Rev. A, 22-Sep-08
 New Product
SiS406DN
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
50 2.0

VGS = 10 thru 4 V TC = - 55 °C
40
1.5

I D - Drain Current (A)

I D - Drain Current (A)

30

1.0

20
TC = 25 °C
VGS = 3 V
0.5
10
TC = 125 °C

0 0.0
0.0 0.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0

VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V)

Output Characteristics Transfer Characteristics

0.016 1500

0.014 1200 Ciss

R DS(on) - On-Resistance (Ω)

C - Capacitance (pF)

VGS = 4.5 V
0.012 900

0.010 VGS = 10 V 600

Coss
0.008 300

Crss
0.006 0
0 10 20 30 40 50 0 6 12 18 24 30

ID - Drain Current (A) VDS - Drain-to-Source Voltage (V)

On-Resistance vs. Drain Current and Gate Voltage Capacitance

10 1.7

ID = 16 A ID = 12 A
VDS = 7.5 V VGS = 10 V
VGS - Gate-to-Source Voltage (V)

8 1.5
R DS(on) - On-Resistance

VDS = 15 V
(Normalized)

6 1.3
VGS = 4.5 V
VDS = 22.5 V
4 1.1

2 0.9

0 0.7
0 5 10 15 20 - 50 - 25 0 25 50 75 100 125 150

Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C)

Gate Charge On-Resistance vs. Junction Temperature

Document Number: 68805 www.vishay.com

S-82301-Rev. A, 22-Sep-08 3
 New Product
SiS406DN
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

100 0.030

ID = 12 A

10 0.024

R DS(on) - On-Resistance (Ω)

I S - Source Current (A)

TJ = 150 °C TJ = 25 °C

1 0.018
TJ = 125 °C

0.1 0.012

TJ = - 50 °C TJ = 25 °C
0.01 0.006

0.001 0.000
0.0 0.2 0.4 0.6 0.8 1.0 1.2 2 3 4 5 6 7 8 9 10

VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V)

Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage

0.5 150

0.2 120
VGS(th) Variance (V)

- 0.1
Power (W)

90

ID = 5 mA
- 0.4 60

ID = 250 µA
- 0.7 30

- 1.0 0
--50 --25 0 25 50 75 100 125 150 0.001 0.01 0.1 1 10

TJ - Temperature (°C) Time (s)

Threshold Voltage Single Pulse Power, Junction-to-Ambient

100
Limited by RDS(on)*
100 µs

10
I D - Drain Current (A)

1 ms

10 ms
1
100 ms

1s
10 s
0.1
100 s
TA = 25 °C DC
Single Pulse BVDSS Limited

0.01
0.1 1 10 100
VDS - Drain-to-Source Voltage (V)
* VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area, Junction-to-Ambient

www.vishay.com Document Number: 68805

4 S-82301-Rev. A, 22-Sep-08
 New Product
SiS406DN
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted

60

50

I D - Drain Current (A)

40

30

20 Package Limited

10

0
0 25 50 75 100 125 150

TC - Case Temperature (°C)

Current Derating*

70 2.20

60
1.76
50
Power (W)
Power (W)

1.32
40

30
0.88

20
0.44
10

0 0.00
0 25 50 75 100 125 150 0 25 50 75 100 125 150

TC - Case Temperature (°C) TA - Ambient Temperature (°C)

Power, Junction-to-Case Power, Junction-to-Ambient

* The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper
dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package
limit.

Document Number: 68805 www.vishay.com

S-82301-Rev. A, 22-Sep-08 5
 New Product
SiS406DN
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
1

Duty Cycle = 0.5

Normalized Effective Transient
Thermal Impedance

0.2

0.1 Notes:
0.1
PDM
0.05
t1
t2
t1
0.02 1. Duty Cycle, D =
t2
2. Per Unit Base = RthJA = 81 °C/W

Single Pulse 3. TJM - TA = PDMZthJA(t)

4. Surface Mounted
0.01
10 -4 10 -3 10 -2 10 -1 1 10 100 1000
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient

1
Duty Cycle = 0.5
Normalized Effective Transient
Thermal Impedance

0.2

0.1

0.1 0.05

0.02

Single Pulse

0.01
10 -4 10 -3 10 -2 10 -1 1
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Case

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?68805.

www.vishay.com Document Number: 68805

6 S-82301-Rev. A, 22-Sep-08
 Package Information
www.vishay.com
Vishay Siliconix
PowerPAK® 1212, (Single/Dual)
L
H E2 K

D4
W E4

θ
M
8
1 1

e
Z
2

D1

D2

D5
2

D
3

4 5 4

b
θ
L1 E3
θ θ A1
Backside View of Single Pad
L
H K
A

E2
E4
c

D2 D3(2x) D4
H
2
1
E1 Detail Z D1
E 2

D5
Notes: 3

K1
1. Inch will govern D2
4

b
2 Dimensions exclusive of mold gate burrs
3. Dimensions exclusive of mold flash and cutting burrs
E3
Backside View of Dual Pad

MILLIMETERS INCHES
DIM.
MIN. MAX. MIN. MAX.
A 0.79 1.12 0.031 0.044
A1 0 0.05 0 0.002
b 0.23 0.41 0.009 0.016
c 0.13 0.33 0.005 0.013
D 3.00 3.61 0.118 0.142
D1 2.95 3.21 0.116 0.126
D2 1.98 2.70 0.078 0.106
D4 0.31 TYP. 0.012 TYP.
E 3.00 3.61 0.118 0.142
E1 2.95 3.21 0.116 0.126
E2 1.47 2.21 0.058 0.087
E3 1.75 1.98 0.069 0.078
E4 0.535 TYP. 0.021 TYP.
e 0.65 BSC 0.026 BSC
K 0.61 0.024
K1 0.35 0.014
H 0.15 0.51 0.006 0.020
L 0.15 0.56 0.006 0.022
L1 0.051 0.204 0.002 0.008
θ 0° 12° 0° 12°
W 0.15 0.36 0.006 0.014
M 0.125 TYP. 0.005 TYP.
ECN: C15-0077-Rev. K, 26-Jan-15
DWG: 5882

Revison: 26-Jan-15 1 Document Number: 71656

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
 AN822
Vishay Siliconix

PowerPAK® 1212 Mounting and Thermal Considerations

Johnson Zhao

MOSFETs for switching applications are now available The PowerPAK 1212-8 has a footprint area compara-
with die on resistances around 1 mΩ and with the ble to TSOP-6. It is over 40 % smaller than standard
capability to handle 85 A. While these die capabilities TSSOP-8. Its die capacity is more than twice the size
represent a major advance over what was available of the standard TSOP-6’s. It has thermal performance
just a few years ago, it is important for power MOSFET an order of magnitude better than the SO-8, and 20
packaging technology to keep pace. It should be obvi- times better than TSSOP-8. Its thermal performance is
ous that degradation of a high performance die by the better than all current SMT packages in the market. It
package is undesirable. PowerPAK is a new package will take the advantage of any PC board heat sink
technology that addresses these issues. The PowerPAK capability. Bringing the junction temperature down also
1212-8 provides ultra-low thermal impedance in a increases the die efficiency by around 20 % compared
small package that is ideal for space-constrained with TSSOP-8. For applications where bigger pack-
applications. In this application note, the PowerPAK ages are typically required solely for thermal consider-
1212-8’s construction is described. Following this, ation, the PowerPAK 1212-8 is a good option.
mounting information is presented. Finally, thermal
and electrical performance is discussed. Both the single and dual PowerPAK 1212-8 utilize the
same pin-outs as the single and dual PowerPAK SO-8.
THE PowerPAK PACKAGE The low 1.05 mm PowerPAK height profile makes both
versions an excellent choice for applications with
The PowerPAK 1212-8 package (Figure 1) is a deriva-
space constraints.
tive of PowerPAK SO-8. It utilizes the same packaging
technology, maximizing the die area. The bottom of the
PowerPAK 1212 SINGLE MOUNTING
die attach pad is exposed to provide a direct, low resis-
tance thermal path to the substrate the device is To take the advantage of the single PowerPAK 1212-8’s
mounted on. The PowerPAK 1212-8 thus translates thermal performance see Application Note 826,
the benefits of the PowerPAK SO-8 into a smaller Recommended Minimum Pad Patterns With Outline
package, with the same level of thermal performance. Drawing Access for Vishay Siliconix MOSFETs. Click
(Please refer to application note “PowerPAK SO-8 on the PowerPAK 1212-8 single in the index of this
Mounting and Thermal Considerations.”) document.
In this figure, the drain land pattern is given to make full
contact to the drain pad on the PowerPAK package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an
area of about 0.3 to 0.5 in2 of will yield little improve-
ment in thermal performance.

Figure 1. PowerPAK 1212 Devices

Document Number 71681 www.vishay.com

03-Mar-06 1
AN822
Vishay Siliconix

PowerPAK 1212 DUAL

To take the advantage of the dual PowerPAK 1212-8’s ture profile used, and the temperatures and time
thermal performance, the minimum recommended duration, are shown in Figures 2 and 3. For the lead
land pattern can be found in Application Note 826, (Pb)-free solder profile, see http://www.vishay.com/
Recommended Minimum Pad Patterns With Outline doc?73257.
Drawing Access for Vishay Siliconix MOSFETs. Click
on the PowerPAK 1212-8 dual in the index of this doc-
ument.
The gap between the two drain pads is 10 mils. This
matches the spacing of the two drain pads on the Pow-
erPAK 1212-8 dual package.
This land pattern can be extended to the left, right, and
top of the drawn pattern. This extension will serve to
increase the heat dissipation by decreasing the ther-
mal resistance from the foot of the PowerPAK to the
PC board and therefore to the ambient. Note that
increasing the drain land area beyond a certain point
will yield little decrease in foot-to-board and foot-to-
ambient thermal resistance. Under specific conditions
of board configuration, copper weight, and layer stack,
experiments have found that adding copper beyond an Ramp-Up Rate + 6 °C /Second Maximum
area of about 0.3 to 0.5 in2 of will yield little improve- Temperature at 155 ± 15 °C 120 Seconds Maximum
ment in thermal performance. Temperature Above 180 °C 70 - 180 Seconds
Maximum Temperature 240 + 5/- 0 °C
Time at Maximum Temperature 20 - 40 Seconds
REFLOW SOLDERING
Ramp-Down Rate + 6 °C/Second Maximum
Vishay Siliconix surface-mount packages meet solder
reflow reliability requirements. Devices are subjected
Figure 2. Solder Reflow Temperature Profile
to solder reflow as a preconditioning test and are then
reliability-tested using temperature cycle, bias humid-
ity, HAST, or pressure pot. The solder reflow tempera-

10 s (max)
210 - 220 °C

3 ° C/s (max) 4 ° C/s (max)

183 °C
140 - 170 °C

50 s (max)

3° C/s (max) 60 s (min) Reflow Zone

Pre-Heating Zone

Maximum peak temperature at 240 °C is allowed.

Figure 3. Solder Reflow Temperatures and Time Durations

www.vishay.com Document Number 71681

2 03-Mar-06
 AN822
Vishay Siliconix

TABLE 1: EQIVALENT STEADY STATE PERFORMANCE

Package SO-8 TSSOP-8 TSOP-8 PPAK 1212 PPAK SO-8
Configuration Single Dual Single Dual Single Dual Single Dual Single Dual
Thermal Resiatance RthJC(C/W) 20 40 52 83 40 90 2.4 5.5 1.8 5.5

PowerPAK 1212 Standard SO-8 Standard TSSOP-8 TSOP-6

49.8 °C 85 °C 149 °C 125 °C

2.4 °C/W 20 °C/W 52 °C/W 40 °C/W

PC Board at 45 °C

Figure 4. Temperature of Devices on a PC Board

THERMAL PERFORMANCE

Introduction Spreading Copper

A basic measure of a device’s thermal performance is Designers add additional copper, spreading copper, to
the junction-to-case thermal resistance, Rθjc, or the the drain pad to aid in conducting heat from a device. It
junction to- foot thermal resistance, Rθjf. This parameter is helpful to have some information about the thermal
is measured for the device mounted to an infinite heat performance for a given area of spreading copper.
sink and is therefore a characterization of the device Figure 5 and Figure 6 show the thermal resistance of a
only, in other words, independent of the properties of the PowerPAK 1212-8 single and dual devices mounted on
object to which the device is mounted. Table 1 shows a a 2-in. x 2-in., four-layer FR-4 PC boards. The two inter-
comparison of the PowerPAK 1212-8, PowerPAK SO-8, nal layers and the backside layer are solid copper. The
standard TSSOP-8 and SO-8 equivalent steady state internal layers were chosen as solid copper to model the
performance. large power and ground planes common in many appli-
By minimizing the junction-to-foot thermal resistance, the cations. The top layer was cut back to a smaller area and
MOSFET die temperature is very close to the tempera- at each step junction-to-ambient thermal resistance
ture of the PC board. Consider four devices mounted on measurements were taken. The results indicate that an
a PC board with a board temperature of 45 °C (Figure 4). area above 0.2 to 0.3 square inches of spreading copper
Suppose each device is dissipating 2 W. Using the junc- gives no additional thermal performance improvement.
tion-to-foot thermal resistance characteristics of the A subsequent experiment was run where the copper on
PowerPAK 1212-8 and the other SMT packages, die the back-side was reduced, first to 50 % in stripes to
temperatures are determined to be 49.8 °C for the Pow- mimic circuit traces, and then totally removed. No signif-
erPAK 1212-8, 85 °C for the standard SO-8, 149 °C for icant effect was observed.
standard TSSOP-8, and 125 °C for TSOP-6. This is a
4.8 °C rise above the board temperature for the Power-
PAK 1212-8, and over 40 °C for other SMT packages. A
4.8 °C rise has minimal effect on rDS(ON) whereas a rise
of over 40 °C will cause an increase in rDS(ON) as high
as 20 %.

Document Number 71681 www.vishay.com

03-Mar-06 3
AN822
Vishay Siliconix

105 130

Spreading Copper (sq. in.) 120 Spreading Copper (sq. in.)

95
110
85
100

RthJ A (°C/W)
RthJA (°C/W)

75 90

80
65 50 % 100 %
70
100 %
55 0%
50 % 60
0%
45 50

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00

Figure 5. Spreading Copper - Si7401DN Figure 6. Spreading Copper - Junction-to-Ambient Performance

CONCLUSIONS
As a derivative of the PowerPAK SO-8, the PowerPAK The PowerPAK 1212-8 combines small size with attrac-
1212-8 uses the same packaging technology and has tive thermal characteristics. By minimizing the thermal
been shown to have the same level of thermal perfor- rise above the board temperature, PowerPAK simplifies
mance while having a footprint that is more than 40 % thermal design considerations, allows the device to run
smaller than the standard TSSOP-8. cooler, keeps rDS(ON) low, and permits the device to
Recommended PowerPAK 1212-8 land patterns are handle more current than a same- or larger-size MOS-
provided to aid in PC board layout for designs using this FET die in the standard TSSOP-8 or SO-8 packages.
new package.

www.vishay.com Document Number 71681

4 03-Mar-06
 Application Note 826
Vishay Siliconix

RECOMMENDED MINIMUM PADS FOR PowerPAK® 1212-8 Single

0.152
(3.860)

0.039 0.068 0.010

(0.990) (1.725) (0.255)

0.016
(0.405)

(2.235)

(2.390)
0.088

0.094
0.026
(0.660)

0.025 0.030
(0.635) (0.760)

Recommended Minimum Pads

Dimensions in Inches/(mm)

Return to Index

Return to Index

APPLICATION NOTE

Document Number: 72597 www.vishay.com

Revision: 21-Jan-08 7
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Disclaimer
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definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
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requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
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Revision: 02-Oct-12 1 Document Number: 91000