CMEN 501: INTEGRATED CIRCUITS AND SYSTEM DESIGN

INTRODUCTION

The significance of semiconductors on general advancement in technology is enormous. This is because

microelectronics is acting as a technology driver that facilitates a range of other industrial, commercial, and

service activities. These include:

1. The computer and software industry,

2. The telecommunications and media industry,

3. Commerce, logistics, and transportation,

4. Natural science and medicine,

5. Power generation and distribution,

6. Finance and administration, etc.

DEFINITION

An integrated circuit (IC) is an electronic component that incorporates and interconnects a multitude of

miniature electronic devices, mostly transistors, on a single piece of semiconductor material, typically silicon.2

Many such circuits are jointly manufactured on a thin semiconductor wafer with a diameter of 200 or 300 mm

before they get cut apart to become (naked) dies. The sizes of typical dies range between a pinhead and a large

postage stamp. The vast majority of ICs, or (micro) chips as they are colloquially referred to, gets individually

encapsulated in a hermetic package before being soldered onto printed circuit boards (PCB).

SIZING OF ICs IS BASED ON:

1. Die size, 2. Transistor count 3. Gate equivalents

TYPES BY COMPONENT COUNT

1. circuit complexity GEs of logic + bits of memory
2. small-scale integration (SSI) 1–10
3. medium-scale integration (MSI) 10–100
4. large-scale integration (LSI) 100–10 000
5. very-large-scale integration (VLSI) 10 000–1 000 000
6. ultra-large-scale integration (ULSI) 1 000 000 . . .

TYPES BY APPLICATION
 1. General-purpose ICs

The function of a general-purpose IC is either so simple or so generic that the component is being

used in a multitude of applications and typically sold in huge quantities. Examples include gates,

flip-flops, counters, and other components of the various 7400 families but also RAMs, ROMs,

microcomputers, and most digital signal processors (DSPs).

2. Application-specific integrated circuits

Application-specific integrated circuits (ASICs) are being specified and designed with a particular purpose,

equipment, or processing algorithm in mind. Initially, the term had been closely associated with glue logic, that

is with all those bus drivers, decoders, multiplexers, registers, interfaces, etc. that exist in almost any system

assembled from highly integrated parts. ASICs have evolved from substituting a single package for many such

ancillary functions that originally had to be dispersed over several SSI/MSI circuits

a. Application-specific standard product (ASSP). While designed and optimized for a highly

specific task, an application-specific standard product circuit is being sold to various customers for

incorporation into their own products. Examples include graphics accelerators, multimedia chips, data

compression circuits, forward error correction devices, ciphering/deciphering circuits, smart card chips,

chip sets for cellular radio, serial-ATA and Ethernet interfaces, wireless LAN chips, and driver circuits

for power semiconductor devices, to name just a few

b. User-specific integrated circuit (USIC). As opposed to ASSPs, user-specific ICs are being

designed and produced for a single company that seeks a competitive advantage for their products; they are

not intended to be marketed as such. Control of innovation and protection of proprietary know-how are

high-ranking motivations for designing circuits of this category. Parts are often fabricated in relatively

modest quantities.
NB: glue logic is the custom logic circuitry used to interface a number of off-the-shelf integrated circuits

TYPES BY FABRICATION

FULL-CUSTOM ICS

Integrated circuits are manufactured by patterning multiple layers of semiconductor materials, metals, and

dielectrics. In a full-custom IC, all such layers are patterned according to user specifications. Fabricating a

particular design requires wafers to go through all processing steps under control of a full set of lithographic

photomasks all of which are made to order for this very design. This is relevant from an economic point of

view because mask manufacturing is a dominant contribution to non-recurring VLSI fabrication costs. A very

basic CMOS process featuring two layers of metal requires some 10 to 12 fabrication masks, any additional

metal layer requires two more masks.

SEMI-CUSTOM ICS

Only a small subset of fabrication layers is unique to each design. Customization starts from preprocessed

wafers that include large quantities of prefabricated but largely uncommitted primitive items such as transistors

or logic gates. These so-called master wafers then undergo a few more processing steps during which those

primitives get interconnected in such a way as to complete the electrical and logic circuitry required for a

particular design. As an example, fig.1.5 shows how a logic gate is manufactured from a few pre-existing

MOSFETs by etching open contact holes followed by deposition and patterning of one metal layer.
 MOS THEORY
REVIEW OF FET
This type of transistor is constructed using only one type of doped semiconductor material, that is, either p-type
or n-type material. Therefore, its operation is based on the flow of majority carriers only. The flow of current
from one end of the material to the other is controlled by means of applied voltage which creates an electric
field. The two ends of the material are called source and drain (with no physical difference) while the point
where the control voltage is applied between them is called the gate. There are different types JFETs and
MOSFETs. Distance between source and drain is called channel length (typically from 0.3 to 1.0µm).

METAL-OXIDE SEMICONDUCTOR FET (MOSFET)

Unlike the JFET already discussed, this type of field effect transistor (FET) called MOSFET is different in
make. Its n-channel type is made by using a slab of p-type silicon material as the base on which the n-channel is
formed. This base is called “substrate”. The source (S) and drain (D) terminals are connected through metallic
contacts to the n-doped regions and the two are linked together by the n-channel. The gate is also connected to
the similar metal contact which is insulated from the n-channel.

A very thin silicon dioxide (

SiO 2 ) layer is used as a special type of insulator known as dielectric (thickness of
0.01 – 0.03µm). This dielectric material sets up opposing electric field when external electric field is applied to
it.

N-Channel MOSFET
The n-channel MOSFET is biased by applying voltage
V GS =0 V between gate and source while a positive

voltage
V DS is applied between drain and source as shown in Fig. 4.8(a). This makes more free electrons move
I
freely along the n-channel (conduction) from source to drain producing the drain current D similar to JFET.
 V
The application of this positive voltage GS that causes increase in the current
I D is called ‘enhancement
mode’ operation of the n-channel MOSFET.

Also, in this case, the relationship between the voltage

V GS and the current I D remains the same as that of
JFET, implying.

( )
2
V GS
I DS 1−
ID = VP

P-Channel MOSFET
The p-channel MOSFET is constructed in the same way as the n-channel. In this type, the n-type material is
used to form the substrate as shown in Fig. (a). In a p-channel MOSFET application, the positive gate voltage
V GS sets it in depletion mode while negative voltage V GS sets MOSFET in enhancement mode operation. This
phenomena is illustrated by the characteristic curve of Fig. (b).

These two MOSFET (n-channel and p-channel) are basically known as n-channel and p-channel depletion-
type MOSFET, respectively. Their common symbols are given in Fig. below.
Enhancement Type of N-Channel MOSFET

The characteristic curve of the enhancement type MOSFET is given in Fig. (b). This transfer characteristic
I
curve shows that the current D remains zero for any applied voltage
V GS ≤V T . However, from V GS =V T
upwards the drain current increases in accordance with equation (4.4).
Enhancement Type of P-Channel MOSFET
The construction of p-channel enhancement type MOSFET is exactly the reverse of the n-channel discussed
earlier as illustrated in Fig. (a) and its characteristic curves, Fig. (b).
The typical cross section of MOS is given below. The gate was historically made using metals, but now
polysilicon is used (which is heavily doped amorphous silicon) because it helps dimension of the transistor to be
more accurate during patterning. This is due to self-align process that gives smaller and faster transistors.

BASIC OPERATION OF MOS

Assuming both source and drain and grounded, the MOS acts like capacitor with gate as one plate, SiO 2 as
dielectric and surface under it as other plate.

When gate voltage is negative that plate would have excess electrons and make the other positive with excess
holes. The charge accumulation would be:

Where COX = gate capacitance VGS = gate to source voltage Vth = threshold voltage Veff = effective voltage

Hence,

Cox is gate capacitance per unit area given as:

Kox is relative permittivity of SiO2 and ε ox is the thickness of the oxide under the gate.

When drain voltage is increased above 0V, the PD between drain and source causes a drain current:
 W
I D =μn Qn V
L DS

A 3-D cross section of MOS transistor is shown above.

Small-Signal Modelling in the Active Region

In this modelling all the capacitors are ignored by replacing them with open circuit. The voltage controlled
current source gmVgs is the most significant element and gm (transconductance) is gven by:

The corresponding current is given by:

(*)
The equivalent circuit of this model is given below:

Neglecting the capacitors makes the model to be in low frequency and hence the final circuit is given as
follows:
Differentiating (*) we have:

This shows that the transconductance of MOS is directly proportional to the effective voltage (V eff).
We can also from equation express VGS and Veff as:

SUBTHRESHOLD OPERATION

All the preceeding equations are on the assumption that V eff (i.e. VGS – Vt) is above 100 mV and the device is in
strong inversion. In situation where these conditions are not satisfied, the accuracy of the equations is very low,
and the device is now in subthreshold region. Exponential relationship is more accurate and is given as:

The assumptions here are: VS = 0 and VDS > 75 mV and the constant ID0 is around 20 nA