VERILOG CODE (SIS0 BEHAVIORAL):

SISO
module siso(

input clk,rst,SI,

output S0

);

reg[3:0] shift_reg;

always @(posedge clk or posedge rst)

begin

if(rst) shift_reg <=0;

else shift_reg <= {shift_reg[2:0],SI};

end

assign S0 = shift_reg[3];

endmodule

TESTBENCH :

module siso_tb;

reg clk,SI,rst;

wire S0;

siso s1(clk,rst,SI,S0);

always #5 clk = ~clk;

initial begin

clk=0;rst=1;SI=0;

#10 rst =0;

#10 SI = 1;

#10 SI = 0;

#10 SI = 1;

#10 SI = 1;

#10 SI = 0;

#50 $finish;

End

Endmodule
RTL SCHEMATIC :

SIMULATION WAVEFORM :

SYNTHESIS REPORT :
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.

---------------------------------------------------------------------------------------------------------------------------------------------

| Tool Version : Vivado v.2024.1 (win64) Build 5076996 Wed May 22 18:37:14 MDT 2024

| Date : Tue Nov 25 12:17:05 2024

| Host : RICHA running 64-bit major release (build 9200)

| Command : report_utilization -file siso_utilization_synth.rpt -pb siso_utilization_synth.pb

| Design : siso

| Device : xc7a35tcpg236-1

| Speed File : -1

| Design State : Synthesized

---------------------------------------------------------------------------------------------------------------------------------------------
Utilization Design Information

Table of Contents

-----------------

1. Slice Logic

1.1 Summary of Registers by Type

2. Memory

3. DSP

4. IO and GT Specific

5. Clocking

6. Specific Feature

7. Primitives

8. Black Boxes

9. Instantiated Netlists

1. Slice Logic

--------------

+-------------------------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+-------------------------+------+-------+------------+-----------+-------+

| Slice LUTs* | 0| 0| 0| 20800 | 0.00 |

| LUT as Logic | 0| 0| 0| 20800 | 0.00 |

| LUT as Memory | 0| 0| 0| 9600 | 0.00 |

| Slice Registers | 4| 0| 0| 41600 | <0.01 |

| Register as Flip Flop | 4 | 0| 0| 41600 | <0.01 |

| Register as Latch | 0| 0| 0| 41600 | 0.00 |

| F7 Muxes | 0| 0| 0| 16300 | 0.00 |

| F8 Muxes | 0| 0| 0| 8150 | 0.00 |

+-------------------------+------+-------+------------+-----------+-------+

* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design
after synthesis, if not already completed, for a more realistic count.

Warning! LUT value is adjusted to account for LUT combining.

Warning! For any ECO changes, please run place_design if there are unplaced instances
1.1 Summary of Registers by Type

--------------------------------

+-------+--------------+-------------+--------------+

| Total | Clock Enable | Synchronous | Asynchronous |

+-------+--------------+-------------+--------------+

|0 | _| -| -|

|0 | _| -| Set |

|0 | _| -| Reset |

|0 | _| Set | -|

|0 | _| Reset | -|

|0 | Yes | -| -|

|0 | Yes | -| Set |

|4 | Yes | -| Reset |

|0 | Yes | Set | -|

|0 | Yes | Reset | -|

+-------+--------------+-------------+--------------+

2. Memory

---------

+----------------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+----------------+------+-------+------------+-----------+-------+

| Block RAM Tile | 0 | 0| 0| 50 | 0.00 |

| RAMB36/FIFO* | 0 | 0| 0| 50 | 0.00 |

| RAMB18 | 0| 0| 0| 100 | 0.00 |

+----------------+------+-------+------------+-----------+-------+

* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one
FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1

3. DSP

------
+-----------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+-----------+------+-------+------------+-----------+-------+

| DSPs | 0| 0| 0| 90 | 0.00 |

+-----------+------+-------+------------+-----------+-------+

4. IO and GT Specific

---------------------

+-----------------------------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+-----------------------------+------+-------+------------+-----------+-------+

| Bonded IOB | 4| 0| 0| 106 | 3.77 |

| Bonded IPADs | 0| 0| 0| 10 | 0.00 |

| Bonded OPADs | 0| 0| 0| 4 | 0.00 |

| PHY_CONTROL | 0| 0| 0| 5 | 0.00 |

| PHASER_REF | 0| 0| 0| 5 | 0.00 |

| OUT_FIFO | 0| 0| 0| 20 | 0.00 |

| IN_FIFO | 0| 0| 0| 20 | 0.00 |

| IDELAYCTRL | 0| 0| 0| 5 | 0.00 |

| IBUFDS | 0| 0| 0| 104 | 0.00 |

| GTPE2_CHANNEL | 0| 0| 0| 2 | 0.00 |

| PHASER_OUT/PHASER_OUT_PHY | 0 | 0| 0| 20 | 0.00 |

| PHASER_IN/PHASER_IN_PHY | 0| 0| 0| 20 | 0.00 |

| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0| 0| 250 | 0.00 |

| IBUFDS_GTE2 | 0| 0| 0| 2 | 0.00 |

| ILOGIC | 0| 0| 0| 106 | 0.00 |

| OLOGIC | 0| 0| 0| 106 | 0.00 |

+-----------------------------+------+-------+------------+-----------+-------+

5. Clocking

-----------

+------------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

| BUFGCTRL | 1 | 0| 0| 32 | 3.13 |

| BUFIO | 0| 0| 0| 20 | 0.00 |

| MMCME2_ADV | 0 | 0| 0| 5 | 0.00 |

| PLLE2_ADV | 0 | 0| 0| 5 | 0.00 |

| BUFMRCE | 0 | 0| 0| 10 | 0.00 |

| BUFHCE | 0| 0| 0| 72 | 0.00 |

| BUFR | 0| 0| 0| 20 | 0.00 |

+------------+------+-------+------------+-----------+-------+

6. Specific Feature

-------------------

+-------------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+-------------+------+-------+------------+-----------+-------+

| BSCANE2 | 0| 0| 0| 4 | 0.00 |

| CAPTUREE2 | 0 | 0| 0| 1 | 0.00 |

| DNA_PORT | 0 | 0| 0| 1 | 0.00 |

| EFUSE_USR | 0 | 0| 0| 1 | 0.00 |

| FRAME_ECCE2 | 0 | 0| 0| 1 | 0.00 |

| ICAPE2 | 0| 0| 0| 2 | 0.00 |

| PCIE_2_1 | 0 | 0| 0| 1 | 0.00 |

| STARTUPE2 | 0 | 0| 0| 1 | 0.00 |

| XADC | 0| 0| 0| 1 | 0.00 |

+-------------+------+-------+------------+-----------+-------+

7. Primitives

-------------

+----------+------+---------------------+

| Ref Name | Used | Functional Category |

+----------+------+---------------------+

| FDCE | 4| Flop & Latch |

| IBUF | 3| IO |

| OBUF | 1| IO |
| BUFG | 1| Clock |

+----------+------+---------------------+

8. Black Boxes

--------------+----------+------+

| Ref Name | Used |

+----------+------+

9. Instantiated Netlists

------------------------

+----------+------+

| Ref Name | Used |

+----------+------+

TIMING SUMMARY :

POWER REPORT :
VERILOG CODE (SIPO BEHAVIORAL):
SIPO
module sipo(

input clk, rst, SI,

output reg [3:0] PO

);

always @(posedge clk or posedge rst) begin

if (rst)

PO <= 0; // Reset the output to 0

else

PO <= {PO[2:0], SI}; // Shift in the serial input (SI)

end

endmodule

TESTBENCH :

module sipo_tb;

reg clk, SI, rst;

wire [3:0] P;

// Instantiate the SIPO module

sipo s1 (

.clk(clk),

.rst(rst),

.SI(SI),

.PO(P)

);

// Clock generation with a period of 10 time units (5 time units for half-period)

always #5 clk = ~clk;

initial begin
 // Initial values

clk = 0; rst = 1; SI = 0;

// Apply reset (rst is 1 initially)

#10 rst = 0; // Release reset after 10 time units

// Shift in the serial data

#10 SI = 1; // Shift in '1'

#10 SI = 0; // Shift in '0'

#10 SI = 1; // Shift in '1'

#10 SI = 1; // Shift in '1'

#10 SI = 0; // Shift in '0'

// End simulation after sufficient time to observe the output

#50 $finish;

end

endmodule

RTL SCHEMATIC :

SIMULATION WAVEFORM :
SYNTHESIS REPORT :
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.

---------------------------------------------------------------------------------------------------------------------------------------------

| Tool Version : Vivado v.2024.1 (win64) Build 5076996 Wed May 22 18:37:14 MDT 2024

| Date : Tue Nov 25 12:12:35 2024

| Host : RICHA running 64-bit major release (build 9200)

| Command : report_utilization -file sipo_utilization_synth.rpt -pb sipo_utilization_synth.pb

| Design : sipo

| Device : xc7a35tcpg236-1

| Speed File : -1

| Design State : Synthesized

---------------------------------------------------------------------------------------------------------------------------------------------

Utilization Design Information

Table of Contents

-----------------

1. Slice Logic

1.1 Summary of Registers by Type

2. Memory

3. DSP

4. IO and GT Specific

5. Clocking
6. Specific Feature

7. Primitives

8. Black Boxes

9. Instantiated Netlists

1. Slice Logic

--------------

+-------------------------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+-------------------------+------+-------+------------+-----------+-------+

| Slice LUTs* | 0| 0| 0| 20800 | 0.00 |

| LUT as Logic | 0| 0| 0| 20800 | 0.00 |

| LUT as Memory | 0| 0| 0| 9600 | 0.00 |

| Slice Registers | 4| 0| 0| 41600 | <0.01 |

| Register as Flip Flop | 4 | 0| 0| 41600 | <0.01 |

| Register as Latch | 0| 0| 0| 41600 | 0.00 |

| F7 Muxes | 0| 0| 0| 16300 | 0.00 |

| F8 Muxes | 0| 0| 0| 8150 | 0.00 |

+-------------------------+------+-------+------------+-----------+-------+

* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design
after synthesis, if not already completed, for a more realistic count.

Warning! LUT value is adjusted to account for LUT combining.

Warning! For any ECO changes, please run place_design if there are unplaced instances

1.1 Summary of Registers by Type

--------------------------------

+-------+--------------+-------------+--------------+

| Total | Clock Enable | Synchronous | Asynchronous |

+-------+--------------+-------------+--------------+

|0 | _| -| -|

|0 | _| -| Set |

|0 | _| -| Reset |

|0 | _| Set | -|
|0 | _| Reset | -|

|0 | Yes | -| -|

|0 | Yes | -| Set |

|4 | Yes | -| Reset |

|0 | Yes | Set | -|

|0 | Yes | Reset | -|

+-------+--------------+-------------+--------------+

2. Memory

---------

+----------------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+----------------+------+-------+------------+-----------+-------+

| Block RAM Tile | 0 | 0| 0| 50 | 0.00 |

| RAMB36/FIFO* | 0 | 0| 0| 50 | 0.00 |

| RAMB18 | 0| 0| 0| 100 | 0.00 |

+----------------+------+-------+------------+-----------+-------+

* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one
FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1

3. DSP

------

+-----------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+-----------+------+-------+------------+-----------+-------+

| DSPs | 0| 0| 0| 90 | 0.00 |

+-----------+------+-------+------------+-----------+-------+

4. IO and GT Specific

---------------------
+-----------------------------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+-----------------------------+------+-------+------------+-----------+-------+

| Bonded IOB | 7| 0| 0| 106 | 6.60 |

| Bonded IPADs | 0| 0| 0| 10 | 0.00 |

| Bonded OPADs | 0| 0| 0| 4 | 0.00 |

| PHY_CONTROL | 0| 0| 0| 5 | 0.00 |

| PHASER_REF | 0| 0| 0| 5 | 0.00 |

| OUT_FIFO | 0| 0| 0| 20 | 0.00 |

| IN_FIFO | 0| 0| 0| 20 | 0.00 |

| IDELAYCTRL | 0| 0| 0| 5 | 0.00 |

| IBUFDS | 0| 0| 0| 104 | 0.00 |

| GTPE2_CHANNEL | 0| 0| 0| 2 | 0.00 |

| PHASER_OUT/PHASER_OUT_PHY | 0 | 0| 0| 20 | 0.00 |

| PHASER_IN/PHASER_IN_PHY | 0| 0| 0| 20 | 0.00 |

| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0| 0| 250 | 0.00 |

| IBUFDS_GTE2 | 0| 0| 0| 2 | 0.00 |

| ILOGIC | 0| 0| 0| 106 | 0.00 |

| OLOGIC | 0| 0| 0| 106 | 0.00 |

+-----------------------------+------+-------+------------+-----------+-------+

5. Clocking

-----------

+------------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+------------+------+-------+------------+-----------+-------+

| BUFGCTRL | 1 | 0| 0| 32 | 3.13 |

| BUFIO | 0| 0| 0| 20 | 0.00 |

| MMCME2_ADV | 0 | 0| 0| 5 | 0.00 |

| PLLE2_ADV | 0 | 0| 0| 5 | 0.00 |

| BUFMRCE | 0 | 0| 0| 10 | 0.00 |

| BUFHCE | 0| 0| 0| 72 | 0.00 |

| BUFR | 0| 0| 0| 20 | 0.00 |
+------------+------+-------+------------+-----------+-------+

6. Specific Feature

-------------------

+-------------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+-------------+------+-------+------------+-----------+-------+

| BSCANE2 | 0| 0| 0| 4 | 0.00 |

| CAPTUREE2 | 0 | 0| 0| 1 | 0.00 |

| DNA_PORT | 0 | 0| 0| 1 | 0.00 |

| EFUSE_USR | 0 | 0| 0| 1 | 0.00 |

| FRAME_ECCE2 | 0 | 0| 0| 1 | 0.00 |

| ICAPE2 | 0| 0| 0| 2 | 0.00 |

| PCIE_2_1 | 0 | 0| 0| 1 | 0.00 |

| STARTUPE2 | 0 | 0| 0| 1 | 0.00 |

| XADC | 0| 0| 0| 1 | 0.00 |

+-------------+------+-------+------------+-----------+-------+

7. Primitives

-------------

+----------+------+---------------------+

| Ref Name | Used | Functional Category |

+----------+------+---------------------+

| OBUF | 4| IO |

| FDCE | 4| Flop & Latch |

| IBUF | 3| IO |

| BUFG | 1| Clock |

+----------+------+---------------------+

8. Black Boxes

--------------
+----------+------+

| Ref Name | Used |

+----------+------+

9. Instantiated Netlists

------------------------

+----------+------+

| Ref Name | Used |

+----------+------+

TIMING SUMMARY :

POWER REPORT :

VERILOG CODE (PISO BEHAVIORAL):

input clk,

input rst,

input load,

input [3:0] PI,

output SO

);

reg[3:0] shift_reg;

always @(posedge clk or posedge rst)

begin

if(rst) shift_reg <= 0;

else if (load)shift_reg<=PI;

else shift_reg <={shift_reg[2:0],1'b0};

end

assign SO = shift_reg[3];

endmodule

TESTBENCH :

module piso_tb;

reg clk, rst, load; // Control signals: clock, reset, load

reg [3:0] P_in; // Parallel input (4-bit for this example)

wire SO; // Serial output

piso p1(clk, rst, load, P_in, SO);

always #5 clk = ~clk;

initial begin

clk = 0; rst = 1; load = 0; P_in = 4'b0000;

#10 rst = 0;

#10 load = 1; P_in = 4'b1101;

#10 load = 0;

#50 $finish;
 end

endmodule

RTL SCHEMATIC :

SIMULATION WAVEFORM :

SYNTHESIS REPORT :
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.

---------------------------------------------------------------------------------------------------------------------------------------------

| Tool Version : Vivado v.2024.1 (win64) Build 5076996 Wed May 22 18:37:14 MDT 2024

| Date : Tue Nov 25 12:52:42 2024

| Host : RICHA running 64-bit major release (build 9200)

| Command : report_utilization -file piso_utilization_synth.rpt -pb piso_utilization_synth.pb

| Design : piso

| Device : xc7a35tcpg236-1

| Speed File : -1

| Design State : Synthesized

---------------------------------------------------------------------------------------------------------------------------------------------

Utilization Design Information

-----------------

1. Slice Logic

1.1 Summary of Registers by Type

2. Memory

3. DSP

4. IO and GT Specific

5. Clocking

6. Specific Feature

7. Primitives

8. Black Boxes

9. Instantiated Netlists

1. Slice Logic

--------------

+-------------------------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+-------------------------+------+-------+------------+-----------+-------+

| Slice LUTs* | 2| 0| 0| 20800 | <0.01 |

| LUT as Logic | 2| 0| 0| 20800 | <0.01 |

| LUT as Memory | 0| 0| 0| 9600 | 0.00 |

| Slice Registers | 4| 0| 0| 41600 | <0.01 |

| Register as Flip Flop | 4 | 0| 0| 41600 | <0.01 |

| Register as Latch | 0| 0| 0| 41600 | 0.00 |

| F7 Muxes | 0| 0| 0| 16300 | 0.00 |

| F8 Muxes | 0| 0| 0| 8150 | 0.00 |

+-------------------------+------+-------+------------+-----------+-------+

* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design
after synthesis, if not already completed, for a more realistic count.

Warning! LUT value is adjusted to account for LUT combining.

Warning! For any ECO changes, please run place_design if there are unplaced instances

1.1 Summary of Registers by Type

+-------+--------------+-------------+--------------+

| Total | Clock Enable | Synchronous | Asynchronous |

+-------+--------------+-------------+--------------+

|0 | _| -| -|

|0 | _| -| Set |

|0 | _| -| Reset |

|0 | _| Set | -|

|0 | _| Reset | -|

|0 | Yes | -| -|

|0 | Yes | -| Set |

|4 | Yes | -| Reset |

|0 | Yes | Set | -|

|0 | Yes | Reset | -|

+-------+--------------+-------------+--------------+

2. Memory

---------

+----------------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+----------------+------+-------+------------+-----------+-------+

| Block RAM Tile | 0 | 0| 0| 50 | 0.00 |

| RAMB36/FIFO* | 0 | 0| 0| 50 | 0.00 |

| RAMB18 | 0| 0| 0| 100 | 0.00 |

+----------------+------+-------+------------+-----------+-------+

* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one
FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1

3. DSP

+-----------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+-----------+------+-------+------------+-----------+-------+
| DSPs | 0| 0| 0| 90 | 0.00 |

+-----------+------+-------+------------+-----------+-------+

4. IO and GT Specific

+-----------------------------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+-----------------------------+------+-------+------------+-----------+-------+

| Bonded IOB | 8| 0| 0| 106 | 7.55 |

| Bonded IPADs | 0| 0| 0| 10 | 0.00 |

| Bonded OPADs | 0| 0| 0| 4 | 0.00 |

| PHY_CONTROL | 0| 0| 0| 5 | 0.00 |

| PHASER_REF | 0| 0| 0| 5 | 0.00 |

| OUT_FIFO | 0| 0| 0| 20 | 0.00 |

| IN_FIFO | 0| 0| 0| 20 | 0.00 |

| IDELAYCTRL | 0| 0| 0| 5 | 0.00 |

| IBUFDS | 0| 0| 0| 104 | 0.00 |

| GTPE2_CHANNEL | 0| 0| 0| 2 | 0.00 |

| PHASER_OUT/PHASER_OUT_PHY | 0 | 0| 0| 20 | 0.00 |

| PHASER_IN/PHASER_IN_PHY | 0| 0| 0| 20 | 0.00 |

| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0| 0| 250 | 0.00 |

| IBUFDS_GTE2 | 0| 0| 0| 2 | 0.00 |

| ILOGIC | 0| 0| 0| 106 | 0.00 |

| OLOGIC | 0| 0| 0| 106 | 0.00 |

+-----------------------------+------+-------+------------+-----------+-------+

5. Clocking

--

+------------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+------------+------+-------+------------+-----------+-------+

| BUFGCTRL | 1 | 0| 0| 32 | 3.13 |

| BUFIO | 0| 0| 0| 20 | 0.00 |

| MMCME2_ADV | 0 | 0| 0| 5 | 0.00 |

| PLLE2_ADV | 0 | 0| 0| 5 | 0.00 |

| BUFMRCE | 0 | 0| 0| 10 | 0.00 |

| BUFHCE | 0| 0| 0| 72 | 0.00 |

| BUFR | 0| 0| 0| 20 | 0.00 |
+------------+------+-------+------------+-----------+-------+

6. Specific Feature

+-------------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+-------------+------+-------+------------+-----------+-------+

| BSCANE2 | 0| 0| 0| 4 | 0.00 |

| CAPTUREE2 | 0 | 0| 0| 1 | 0.00 |

| DNA_PORT | 0 | 0| 0| 1 | 0.00 |

| EFUSE_USR | 0 | 0| 0| 1 | 0.00 |

| FRAME_ECCE2 | 0 | 0| 0| 1 | 0.00 |

| ICAPE2 | 0| 0| 0| 2 | 0.00 |

| PCIE_2_1 | 0 | 0| 0| 1 | 0.00 |

| STARTUPE2 | 0 | 0| 0| 1 | 0.00 |

| XADC | 0| 0| 0| 1 | 0.00 |

+-------------+------+-------+------------+-----------+-------+

7. Primitives

-------------

+----------+------+---------------------+

| Ref Name | Used | Functional Category |

+----------+------+---------------------+

| IBUF | 7| IO |

| FDCE | 4| Flop & Latch |

| LUT3 | 3| LUT |

| OBUF | 1| IO |

| LUT2 | 1| LUT |

| BUFG | 1| Clock |

+----------+------+---------------------+

8. Black Boxes

+----------+------+

| Ref Name | Used |

+----------+------+

9. Instantiated Netlists

------------------------

+----------+------+
| Ref Name | Used |

+----------+------+

TIMING SUMMARY :

POWER REPORT :
VERILOG CODE (PIPO BEHAVIORAL):
PIPO
module pipo(

input clk,

input rst,

input load,

input [3:0] PI,

output reg [3:0] PO

);

always @(posedge clk or posedge rst)

begin

if (rst)

PO <= 4'b0; // Reset the output to 0

else if (load)

PO <= PI; // Load the parallel input into the register

End

endmodule

TESTBENCH :

module pipo_tb;

reg clk, rst, load;

reg [3:0] PI;

wire [3:0] PO;

// Instantiate the PIPO module

pipo p1 (

.clk(clk),

.rst(rst),

.load(load),

.PI(PI),
 .PO(PO)

);

// Clock generation

always #5 clk = ~clk;

// Test sequence

initial begin

// Initialize signals

clk = 0;

rst = 1; // Assert reset

load = 0;

PI = 4'b0000;

// Apply reset

#10 rst = 0; // Deassert reset

// Test case 1: Load 4'b1010 into the register

#10 load = 1; PI = 4'b1010;

#10 load = 0;

// Test case 2: Load 4'b1100 into the register

#10 load = 1; PI = 4'b1100;

#10 load = 0;

// Test case 3: Load 4'b0011 into the register

#10 load = 1; PI = 4'b0011;

#10 load = 0;

// End simulation after some time

#50 $finish;

end
endmodule

RTL SCHEMATIC :

SIMULATION WAVEFORM :

SYNTHESIS REPORT :
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.

---------------------------------------------------------------------------------------------------------------------------------------------

| Tool Version : Vivado v.2024.1 (win64) Build 5076996 Wed May 22 18:37:14 MDT 2024

| Date : Tue Nov 25 12:59:01 2024

| Host : RICHA running 64-bit major release (build 9200)

| Command : report_utilization -file pipo_try_utilization_synth.rpt -pb pipo_try_utilization_synth.pb

| Design : pipo_try

| Device : xc7a35tcpg236-1

| Speed File : -1

| Design State : Synthesized

---------------------------------------------------------------------------------------------------------------------------------------------
Utilization Design Information

Table of Contents

-----------------

1. Slice Logic

1.1 Summary of Registers by Type

2. Memory

3. DSP

4. IO and GT Specific

5. Clocking

6. Specific Feature

7. Primitives

8. Black Boxes

9. Instantiated Netlists

1. Slice Logic

--------------

+-------------------------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+-------------------------+------+-------+------------+-----------+-------+

| Slice LUTs* | 0| 0| 0| 20800 | 0.00 |

| LUT as Logic | 0| 0| 0| 20800 | 0.00 |

| LUT as Memory | 0| 0| 0| 9600 | 0.00 |

| Slice Registers | 4| 0| 0| 41600 | <0.01 |

| Register as Flip Flop | 4 | 0| 0| 41600 | <0.01 |

| Register as Latch | 0| 0| 0| 41600 | 0.00 |

| F7 Muxes | 0| 0| 0| 16300 | 0.00 |

| F8 Muxes | 0| 0| 0| 8150 | 0.00 |

+-------------------------+------+-------+------------+-----------+-------+

* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design
after synthesis, if not already completed, for a more realistic count.

Warning! LUT value is adjusted to account for LUT combining.

Warning! For any ECO changes, please run place_design if there are unplaced instances
1.1 Summary of Registers by Type

--------------------------------

+-------+--------------+-------------+--------------+

| Total | Clock Enable | Synchronous | Asynchronous |

+-------+--------------+-------------+--------------+

|0 | _| -| -|

|0 | _| -| Set |

|0 | _| -| Reset |

|0 | _| Set | -|

|0 | _| Reset | -|

|0 | Yes | -| -|

|0 | Yes | -| Set |

|4 | Yes | -| Reset |

|0 | Yes | Set | -|

|0 | Yes | Reset | -|

+-------+--------------+-------------+--------------+

2. Memory

---------

+----------------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+----------------+------+-------+------------+-----------+-------+

| Block RAM Tile | 0 | 0| 0| 50 | 0.00 |

| RAMB36/FIFO* | 0 | 0| 0| 50 | 0.00 |

| RAMB18 | 0| 0| 0| 100 | 0.00 |

+----------------+------+-------+------------+-----------+-------+

* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one
FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1

3. DSP

------+-----------+------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |

+-----------+------+-------+------------+-----------+-------+

| DSPs | 0| 0| 0| 90 | 0.00 |

+-----------+------+-------+------------+-----------+-------+

4. IO and GT Specific

+-----------------------------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+-----------------------------+------+-------+------------+-----------+-------+

| Bonded IOB | 11 | 0| 0| 106 | 10.38 |

| Bonded IPADs | 0| 0| 0| 10 | 0.00 |

| Bonded OPADs | 0| 0| 0| 4 | 0.00 |

| PHY_CONTROL | 0| 0| 0| 5 | 0.00 |

| PHASER_REF | 0| 0| 0| 5 | 0.00 |

| OUT_FIFO | 0| 0| 0| 20 | 0.00 |

| IN_FIFO | 0| 0| 0| 20 | 0.00 |

| IDELAYCTRL | 0| 0| 0| 5 | 0.00 |

| IBUFDS | 0| 0| 0| 104 | 0.00 |

| GTPE2_CHANNEL | 0| 0| 0| 2 | 0.00 |

| PHASER_OUT/PHASER_OUT_PHY | 0 | 0| 0| 20 | 0.00 |

| PHASER_IN/PHASER_IN_PHY | 0| 0| 0| 20 | 0.00 |

| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0| 0| 250 | 0.00 |

| IBUFDS_GTE2 | 0| 0| 0| 2 | 0.00 |

| ILOGIC | 0| 0| 0| 106 | 0.00 |

| OLOGIC | 0| 0| 0| 106 | 0.00 |

+-----------------------------+------+-------+------------+-----------+-------+

5.. Clocking

-----------

+------------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+------------+------+-------+------------+-----------+-------+

| BUFGCTRL | 1 | 0| 0| 32 | 3.13 |

| BUFIO | 0| 0| 0| 20 | 0.00 |

| MMCME2_ADV | 0 | 0| 0| 5 | 0.00 |

| PLLE2_ADV | 0 | 0| 0| 5 | 0.00 |
| BUFMRCE | 0 | 0| 0| 10 | 0.00 |

| BUFHCE | 0| 0| 0| 72 | 0.00 |

| BUFR | 0| 0| 0| 20 | 0.00 |

+------------+------+-------+------------+-----------+-------+

6. Specific Feature

-------------------

+-------------+------+-------+------------+-----------+-------+

| Site Type | Used | Fixed | Prohibited | Available | Util% |

+-------------+------+-------+------------+-----------+-------+

| BSCANE2 | 0| 0| 0| 4 | 0.00 |

| CAPTUREE2 | 0 | 0| 0| 1 | 0.00 |

| DNA_PORT | 0 | 0| 0| 1 | 0.00 |

| EFUSE_USR | 0 | 0| 0| 1 | 0.00 |

| FRAME_ECCE2 | 0 | 0| 0| 1 | 0.00 |

| ICAPE2 | 0| 0| 0| 2 | 0.00 |

| PCIE_2_1 | 0 | 0| 0| 1 | 0.00 |

| STARTUPE2 | 0 | 0| 0| 1 | 0.00 |

| XADC | 0| 0| 0| 1 | 0.00 |

+-------------+------+-------+------------+-----------+-------+

7. Primitives

-------------

+----------+------+---------------------+

| Ref Name | Used | Functional Category |

+----------+------+---------------------+

| IBUF | 7| IO |

| OBUF | 4| IO |

| FDCE | 4| Flop & Latch |

| BUFG | 1| Clock |

+----------+------+---------------------+
8. Black Boxes

-------+----------+------+

| Ref Name | Used |

+----------+------

9. Instantiated Netlists

------------------------+----------+------+

| Ref Name | Used |

+----------+------+

TIMING SUMMARY :

POWER REPORT :