TH E ANALOG M IN D

Behzad Razavi

Fifty Applications of the CMOS Inverter—Part 2

A
As explained in the first part of
this article [1], this series deals
with interesting and useful appli-
cations of the CMOS inverter, a
included. Unless otherwise stated,
L = 30 nm for all transistors.

The Ring Oscillator

the additional loading presented by
the buffer.) The oscillator core power
consumption, P, is given by 3f0 C 0 V 2DD,
where C0 is the total capacitance
versatile building block in today’s Inverter-based ring oscillators can seen from each node to ground. For
designs. In addition to studying serve as a compact solution with a small transistors, the PN is domi-
the operation of such circuits, we wide tuning range. While suffering nated by flicker noise and can be
also quantify their performance by from high phase noise (PN), rings have expressed as [3]
simulations in 28-nm CMOS tech- become common in die-to-die serial
nology. Simulations are performed links (“chiplets”) because a significant f 20
S z (f ) = [S N (f ) + S P (f )] .(1)
in the slow-slow corner at T = 75° C fraction of their PN is removed by 2MI 2D f 2
with VDD = 0.95 V. An estimate of the “clock forwarding” [2].
layout parasitic capacitances is also Consider the ring shown in Fig- Here, M is the number of stages, ID
ure 1(a). The oscillation frequency, is the transistor current under the
Digital Object Identifier 10.1109/MSSC.2024.3473737 f0, is equal to 1/ (6TD), where TD conditions shown in Figure 1(b),
Date of current version: 15 November 2024 denotes the gate delay. (We neglect and S N (f ) and S P (f ), respectively,

Buffer VDD
VDD
2
X ID

0.5 µm 1 µm
(W (N = (W ( P =
L 30 nm L 30 nm

(a) (b)

0
0.8
Phase Noise(dBc/Hz)

–20
Voltage (V)

0.6 –40

–60
0.4
–80
0.2 –100

0.86 0.88 0.9 0.92 0.94 105 106 107 108

Time (ns) Offset Frequency (Hz)
(c) (d)

FIGURE 1: (a) A simple ring oscillator, (b) condition under which ID and SN (f ) are measured, (c) oscillation waveform at X, and (d) PN profile.

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denote the flicker noise drain cur- capacitances at the three nodes by to drain junction capacitances, W
rent spectrum of NMOS and PMOS a factor of n, f0 drops by the same and L are scaled somewhat differ-
devices under the same condition. factor, P remains constant, and S z ently, with the goal of scaling f0 by
This equation offers a wealth of falls by n 2. On the other hand, if we a desired factor (three in this case)
insight into the ring’s PN behavior. raise the number of stages to nM, and keeping P constant. We now
Let us first simulate the circuit we still obtain f 20 /n 2 in the numera- have f0 = 15.7 GHz and the PN pro-
with (W/L) N = 0.5 nm/30 nm and tor of (1) but also another factor of file plotted in Figure 3(b). The PN
(W/L) P = 1 nm/30 nm. Depicted in n in its denominator. The power is at 1-MHz offset has decreased to
Figure 1(c), the waveform at X sug- unchanged. This method is thus –62 dBc/Hz, i.e., by 14 dB. We could
gests that f0 . 46 GHz. We also have advantageous. obtain the same reduction by tri-
P = 340 nA # 0.95V . 320 nW, both The larger number of stages does pling the number of stages but at
attractive results. The profile in lead to substantial complexity if we the cost of greater complexity. We
Figure 1(d), however, reveals a PN target a practical voltage-controlled call this design the “reference oscil-
of –48 dBc/Hz at 1-MHz offset, an oscillator (VCO). Consider the stage lator.” For lower PN values, we can
exceedingly high value. The 30-dB/ shown in Figure 2, where the varac- trade power consumption; if all of
decade slope of the PN profile sig- tor, Cvar, provides continuous tuning, the oscillator’s transistor widths are
nifies flicker noise upconversion for and unit capacitors C 1 gC k imple- scaled up by m, f0 remains constant,
frequency offsets as high as several ment discrete tuning. This topology S z (f ) in (1) drops by m, and P rises
hundred megahertz. exemplifies the design complexity by the same factor.
In practice, we run ring oscil- if f0 is scaled by simply increasing When comparing the PN of differ-
lators at lower frequencies. This the number of stages. We now wish ent oscillators, we should normal-
point holds, for example, in a to see whether the 1/n 3 PN reduc- ize the values to f 20 and P because
chiplet environment due to the tion can be realized without raising S z (f ) ? f 20 /P. Suppose f0 changes
difficulties facing the distribution M. This is possible if both the width to af0 and P changes to bP. If the
of high-frequency clocks. We then and length of the transistors are change in S z (f ) in dB is equal to
ask: How can we lower f0 in Fig- increased by a factor of n . Con- 10 log a 2 + 10 log b -1, we say the
ure 1(a)? If we simply increase the sequently, ID in Figure 1(b) remains performance has not changed.
constant, and S N (f ) and S P (f ) fall
by n because they are inversely pro- The Differential Ring Oscillator
portional to the transistors’ channel It is possible to couple two single-
C1 Ck areas. Since the node capacitances ended rings so as to guarantee that
Cvar rise by approximately a factor of n, they oscillate with opposite phases.
Vcont f0 scales proportionally, causing S z Illustrated in Figure 4(a), the idea is
to fall by n3. We therefore prefer this to inject the output of each o
­ scillator
approach. into the other by an inverter. Since
k Units
Shown in Figure 3(a) is an exam- Inv1 and Inv2 prefer to sustain com-
FIGURE 2: A stage with continuous and ple using (W/L) N = 1 nm/100 nm plementary inputs and outputs,
discrete tuning. and (W/L) P = 2 nm/100 nm. Due the waveforms at X and Y develop

–20
Phase Noise(dBc/Hz)

–40

–60
Core Devices:
–80
1 µm 2 µm
( W (N = ( W (P =
L 100 nm L 100 nm –100

(a)
–120
104 105 106 107 108
Offset Frequency (Hz)
(b)

FIGURE 3: (a) A ring oscillator with larger transistors and (b) its PN profile.

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a phase difference of 180°. If exces- The Quadrature Ring Oscillator of our reference oscillator. With
sively strong, however, these two We can envision placing four P = 850 nA # 0.95 V = 810 nW, we
inverters can create latch-up by vir- inverters in a loop so as to gener- recognize that, ideally, the PN of
tue of positive feedback. For this rea- ate quadrature phases (see Fig- the reference oscillator should
son, we typically scale Inv1 and Inv2 ure 5(a)]. This circuit, however, drop by 10 log (810 nW/340 nW) +
down by a factor of four with respect prefers to latch up and settle into 10 log (15.7 GHz/9.8 GHz) 2 = 7.7 dB.
to the main inverters. “degenerate” conditions A = B = 0 That is, quadrature operation costs
Figure 4(b) plots the waveforms and X = Y = VDD (or the other way about 2.7 dB in performance.
at X and Y, revealing an oscillation around). We know from the pre-
frequency of 14.1 GHz, slightly less vious section that cross-coupled The Current-Controlled Oscillator
than that of the single-ended coun- inverters, e.g., Inv1 and Inv2 in Fig- The high supply sensitivity of the
terpart shown in Figure 3(a). This ure 4(a), pose complementary val- ring oscillators studied in the previ-
occurs due to the additional capaci- ues at their two terminals and can ous sections demands on-chip volt-
tances introduced by the cross- therefore avoid the degenerate con- age regulators having low output
coupled inverters. We also have ditions. As shown in Figure 5(b), we noise. An alternative that alleviates
P = 690 nA # 0.95 V . 660 nW. Pre- attach such pairs between A and this issue supplies the ring by a
sented in Figure 4(c), the PN profile sug- B and between X and Y [4]. Plotted current source [Figure 6(a)], assum-
gests a value of –66 dBc/Hz at a 1-MHz in Figure 5(c) are the quadrature ing that I1 has little dependence on
offset, about 4 dB lower than that in waveforms exhibiting a frequency VDD [5]. Capacitor C1 further sup-
Figure 3(b). This is to be expected of 9.8 GHz. From Figure 5(d), we presses the supply noise. Since the
because 10 log (660 nW/340 nW) + measure a PN of –67 dBc/Hz at a ­oscillation frequency depends on VX
10 log (15.7GHz/14.1 GHz) 2 = 3.7 dB. 1-MHz offset, 5 dB lower than that and since VX can be adjusted by I1,

0.8
Voltage (V)

0.6

X 0.4

0.2
Inv1 Inv2

0
0.5 0.55 0.6 0.65 0.7
Y Time (ns)
(b)
Main Inverters:
0
1 µm 2 µm
( W (N = ( W (P =
L 100 nm L 100 nm –20
Cross−Coupled Inverters:
Phase Noise(dBc/Hz)

0.25 µm 0.5 µm –40

( W (N = ( W (P =
L 30 nm L 30 nm –60
(a) –80

–100

–120

–140
104 105 106 107 108
Offset Frequency (Hz)
(c)

FIGURE 4: (a) A differential ring, (b) the X and Y waveforms, and (c) the PN profile.

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 Inv1 Inv2 Inv1 Inv2
X X

A B A B

Y Y
Inv4 Inv3 Inv4 Inv3
1 µm 2 µm
( W (N = W
( (P =
L 100 nm L 100 nm
(a) (b)

0.8 –20

Phase Noise(dBc/Hz)
–40
Voltage (V)

0.6
–60
0.4 –80

0.2 –100

–120
0
0.8 0.85 0.9 104 105 106 107 108
Time (ns) Offset Frequency (Hz)
(c) (d)

FIGURE 5: (a) A four-stage ring, (b) the addition of cross-coupled inverters, (c) the ring’s waveforms, and (d) the PN profile.

the circuit is called a “current-con-

trolled oscillator” (CCO). VDD 1
It is helpful to estimate the small- I1 C1 RX f 0CL
signal resistance seen at node X X
[Figure 6(b)]. Each inverter can be A
modeled as depicted in Figure 6(c), CL
which represents a capacitance, CL ,
switching between two nodes peri- (a) (b) (c)
odically. Such a structure displays an
average resistance equal to 1/ (f0 C L), FIGURE 6: (a) A CCO, (b) the circuit’s core for resistance calculation, and (c) the equivalent
yielding R X . 1/ (3f0 C L) . Thus, the circuit of one inverter.
pole at X in Figure 6(a) is located at
~ X . 3f0 C L /C 1, demanding a large CL shown in Figure 7(b), for example, 11.1 GHz) 2 = 3.4 dB. But the actual
if low-frequency supply noise must both Ma and Mb introduce flicker PN is 2 dB lower than that of our ref-
be suppressed. noise in the “control” path, thereby erence oscillator.
One advantage of the CCO is its modulating the oscillation fre-
very wide frequency tuning range; quency and phase. To avoid ampli- The Digitally Controlled Oscillator
even if I1 is very small, VX falls to fying the noise of Ma , we select Digital phase-locked loops incorpo-
a level barely necessary for the (W/L) a = (W/L) b = 10 nm/100 nm, rate digitally controlled oscillators
inverters to operate properly, still burning as much power in the ref- (DCOs) rather than VCOs. For this
sustaining oscillation. The princi- erence current path as in the oscil- purpose, we can simply rely on the
pal drawback of the CCO is that it lator. We obtain f0 = 11.1 GHz. discrete tuning scheme depicted in
is highly sensitive to I1, convert- From Figure 7(b), we observe a Figure 2. Alternatively, we can turn
ing the noise of this current source PN of –64 dBc/Hz at a 1-MHz offset. to the topology shown in Figure 8(a)
to PN. This effect is particularly Given P = 400 nA # 0.95 V = 380 nW, [6], where the main ring consisting
acute if I1 carries a great deal of we expect a PN drop of 10 log of Inv1-Inv3 is accompanied by addi-
flicker noise. In the arrangement (380 nW/340 nW) +10 log (15.7GHz/ tional inverters that can be enabled

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or disabled by a thermometer code. varies from three to nine. Of course, The Crystal Oscillator
With only the main ring enabled, for smaller steps, a large number of A single inverter along with two capac-
the circuit oscillates at its lowest inverters are necessary. itors can provide a negative resistance
frequency because of the parasitic Recall from our analysis of the and hence the possibility of oscillation
capacitances introduced by the basic ring oscillator that simply add- if it is connected to a resonator. Illus-
disabled inverters. If we now acti- ing capacitances to the internal nodes trated in Figure 9(a), such a structure
vate, e.g., Inv4, it provides a greater does not reduce the PN as much as displays the following impedance:
drive strength at node Y while neg- increasing the transistor dimensions
g mN + g mP
ligibly raising the total capacitance does. We therefore predict that the ZX = 1 + 1 + (2)
C1 s C2 s C1 C2 s2
at X. The oscillation frequency thus DCO of Figure 8(a) exhibits a less
increases. favorable PN-power tradeoff at its where channel-length modulation is
Employing our reference oscil- lowest oscillation frequency. On the neglected and gmN and gmP denote the
lator of Figure 3(a) in this environ- other hand, the circuit reduces to m transconductances of the inverter’s
ment with a total of nine inverters, rings in parallel at its maximum fre- NMOS and PMOS transistors, respec-
we arrive at the tuning characteris- quency, reducing the PN by a factor tively. For s = j~, the third term
tic presented in Figure 8(b). The fre- of m with respect to that of the ref- emerges as - (g mN + g mP ) / (C 1 C 2 ~ 2),
quency rises from 4.2 to 11.6 GHz erence oscillator while consuming m signifying a frequency-dependent neg-
as the number of active inverters times the power. ative resistance. We now construct the

–20
VDD
Phase Noise(dBc/Hz)

10 µm
( W ( a,b= Mb Ma –40
L 100 nm C1
200 µA –60
X
A
–80

–100
Core Devices:
1 µm 2 µm –120
( W (N = ( W (P = 104 105 106 107 108
L 100 nm L 100 nm Offset Frequency (Hz)
(a) (b)

FIGURE 7: (a) A CCO using a current mirror and (b) its PN.

Inv1 Inv2 Inv3

Y 11
X
10
Oscillation Freq. (GHz)

Inv4
9
m Rows
8

(a) 3 4 5 6 7 8 9
Number of Active Inverters
(b)

FIGURE 8: (a) A DCO and (b) its frequency characteristic.

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oscillator shown in Figure 9(b), where Figure 10(a) plots the voltages at clock. But if two such rings are driven
RF ensures that Inv1 begins in its high- nodes A and B in Figure 9(b), reveal- by Din and D in, and their outputs are
gain region. Inv2 sharpens the wave- ing an oscillation startup time of applied to a NAND gate [Figure 11(b)]
form’s edges. about 300 μs. Plotted in Figure 10(b) [8], we can produce a recovered clock.
The crystal model of Figure 9(c) are the PN profiles at node B and at The beauty of this technique is that it
reveals both series and parallel reso- the output of Inv2. We recognize that relies on ring oscillators for their abil-
nances occurring at ~ s = 1/ L 1 C s Inv2 raises the PN at low offset fre- ity to recover almost instantaneously
and ~ p =1/ L 1C sC p /(C s +C p), respec- quencies due to the slow edges at B. from a reset state.
tively. The topology of Figure 9(b) One can argue that the rings in Fig-
operates at the latter. The Burst-Mode Clock and Data ure 11(b) do not actually phase-lock
We select a 25-MHz crystal model Recovery Circuit to Din because, when enabled, they
from [7] with the following param- “Burst-mode” optical communication operate at their natural frequency,
eter values: L 1 = 12.6 mH, Cs = systems require that their clock and f0. This perspective reveals that any
3.4 fF, Cp = 1.2 pF, and R s = 20 X. data recovery (CDR) circuits phase- difference between f0 and the input
Note that C p & C s, yielding ~ s . ~ p . lock to the incoming data, data rate translates to
To minimize the flicker noise of the Din, in a very short time. Let The beauty of phase error accumu-
inverters, we resort to large transis- us consider a ring oscilla- this technique is lation between the out-
tors: (W/L) N = 20 nm/100 nm and tor under injection by that it relies on put clock and the input
(W/L) P = 40 nm/100 nm. We also Din [Figure 11(a)]. When ring oscillators data. This effect proves
select R F = 1MX to minimize its noise Din is low, the circuit for their ability serious if D in contains
contribution. With C 1 = C 2 = 10 pF and oscillates at its natural to recover almost long sequences of con-
g mN + g mP = 1/ (100 X), the negative frequency, and when Din instantaneously secutive ones or zeros.
resistance at 25 MHz amounts to about is high, node X is pulled from a reset state. The burst-mode CDR
–4 kΩ, more than adequate to cancel to near zero and Vout entails an issue that deter-
the parallel equivalent resistance of remains high. This output is not a peri- mines how the strength of Ma and Mb
the crystal (= L 21 ~ 2 /R s . 2 # 10 11 X) . odic waveform and cannot serve as a in Figure 11(b) must be chosen. Sup-
pose Ma is strong enough to cause
VX . 0. When Ma turns off, E resides
RF at a low level, causing X to charge
ZX L1 Cs R by a PMOS device whose gate-source
s
Inv2 voltage is equal to VDD [Figure 11(c)].
B
A B A Vout This yields a certain rise time, t r1
C1 C2 C1 Inv1 C2 C1 . In the oscillation mode, however,
nodes E and X bear a phase differ-
(a) (b) (c) ence of 120°, producing a different
rise time at X, t r2 . This difference
FIGURE 9: (a) A circuit exhibiting a negative resistance, (b) the basic crystal oscillator, and (c) ­translates to output jitter when the
a crystal model. input makes transitions. For this

VB –156 Vout
1
VA –158 VB
Phase Noise(dBc/Hz)

0.8
–160
Voltage (V)

0.6 –162

0.4 –164

0.2 –166
–168
0
–170
0 100 200 300 400 500 104 105 106 107
Time (us) Offset Frequency (Hz)
(a) (b)

FIGURE 10: The crystal oscillator’s (a) waveforms and (b) PN profile.

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r­eason, we select the strength of Ma at X and Y, and Figure 12(b) shows the idea is to add Inv4 so that the
and Mb only to bring VX or VY down to the recovered clock. The peak-to- waveform at X finds a faster path to
a few hundred millivolts. peak jitter is about 200 fs. Y. The divider can thus run at higher
Another jitter mechanism occurs frequencies. However, it now faces
if the two inputs of the NAND gate The Feedforward Frequency Divider a lower bound because Inv4 over-
in Figure 11(b) experience differ- Recall from the first part of this arti- whelms the main path from X to Y
ent delays. To resolve this issue, we cle series [1] that a dynamic latch can at low clock rates. These bounds are
employ two such gates with their be realized as a transmission gate studied in [9].
inputs swapped in Figure 11(d). followed by an inverter. We have Figure 13(b) plots the waveform at
Beginning with our reference seen in [1] that a ' 2 circuit using Y for an input frequency of 52 GHz,
oscillator of Figure 3(a), we imple- this latch operates up to an input indicating correct operation. As
ment the CDR for operation at 15 GHz. frequency of 45 GHz. This bound depicted in Figure 13(c), the circuit
We have (W/L) a, b = 1.5 nm/30 nm. can be raised by means of “feedfor- operates properly from 23 to 54 GHz.
Figure 12(a) presents the waveforms ward.” Illustrated in Figure 13(a) [9],
The Frequency Divider With
Quadrature Outputs
Wireless and wireline applications
E X often require in-phase (I) and quadra-
X ture (Q) components of periodic wave-
Vout Din Ma forms. To generate these phases by a
Din Ma Vout
frequency divider, we return to the
Din Y quadrature oscillator of Figure 5(b)
and surmise that it can act as a ' 2 cir-
Vout Din Mb cuit if Inv1-Inv4 are controlled by the
input clock. Shown in Figure 14(a), the
Din
t result can be viewed as an injection-
(a)
Vout locked oscillator or as a loop employ-
ing “clocked CMOS” (C2MOS) latches.
VDD t The device dimensions in this
(b)
E divider must be chosen carefully.
X A
B The clocked transistors are twice as
Vout wide as the devices that they enable
Din Ma A
B so as to maintain reasonable pull-
(c) (d) down and pull-up strengths for the
latches. Moreover, the cross-coupled
FIGURE 11: (a) A ring enabled and disabled by random data, (b) a burst-mode CDR circuit, inverters are twice as weak as the
(c) an illustration of oscillator activation, and (d) two crisscrossed NAND gates for improving main inverters to avoid latch-up.
propagation symmetry. With these dimensions, the ­ circuit

1 1
VY
VX
0.8 0.8

0.6
Voltage (V)

Voltage (V)

0.6

0.4
0.4

0.2
0.2

0.8 1 1.2 1.9 2 2.1 2.2 2.3

Time (ns) Time (ns)
(a) (b)

FIGURE 12: The CDR circuit’s (a) internal waveforms and (b) output clock.

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 CK CK
Inv1 Inv2 Inv3
X Y

CK CK

( W ( N = 0.5 µm
L 30 nm Inv4
1 µm Feedforward
( W (P =
L 30 nm
(a)

0.8 25

Output Frequency (GHz)

Voltage (V)

0.6
20
0.4

15
0.2

0.9 1 1.1 1.2 1.3 20 30 40 50 60 70

Time (ns) Input Frequency (GHz)
(b) (c)

FIGURE 13: (a) A divide-by-two circuit with feedforward, (b) the waveform at Y, and (c) its frequency characteristic.

0.8
Voltage (V)

CK CK Main Inverters: 0.6

0.5 µm
( W (N =
L 30 nm 0.4
1 µm
CK CK ( W (P =
L 30 nm 0.2
Clocked Devices:
1 µm 0.78 0.79 0.8 0.81 0.82 0.83
( W (N = Time (ns)
L 30 nm
(b)
2 µm
CK CK ( W (P =
L 30 nm
30
Cross−Coupled
Output Frequency (GHz)

Inverters:
25
0.25 µm
CK CK ( W (N =
L 30 nm
20
0.5 µm
( W (P =
L 30 nm 15
(a)

10

0 20 40 60
Input Frequency (GHz)
(c)

FIGURE 14: (a) A divide-by-two circuit providing quadrature outputs, (b) its output waveforms, and (c) its frequency characteristic.

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generates the I and Q outputs plot- NMOS device in Inv1 and the PMOS interpolation network. Shown in
ted in Figure 14(b) for an input device in Inv2 are heavily on, fight- Figure 16(a) is an example for inter-
frequency of 60 GHz. The character- ing each other. With equal strengths, polation by a factor of 16 at 28 GHz
istic of Figure 14(c) suggests correct therefore, these two transistors pro- [10]. We use a virtual ground, node
operation up to 62 GHz. duce Vout = (VI + VQ ) /2. Of course, X, for the summation of the currents
the NMOS/PMOS strength ratio var- produced by the inverters and the
The Phase Interpolator ies with process corners. resistors. The multiplexers receive a
In some applications, we generate Phase interpolation requires suffi- thermometer code that determines
the I and Q phases of a clock and ciently slow transitions for VI and VQ how many inverters sense VI and how
then interpolate between them so so that they avoid any “nonoverlap” many sense VQ. For example, a code
as to create finer phase spacings. time. As illustrated in Figure 15(b), if with 15 ones and one zero trans-
Inverters can serve this purpose at VI and VQ respectively reside at high lates to Vout ? 15VI + VQ and hence
fairly high speeds. and low levels at the same time, a a rotation of tan -1 (1/15) = 3.8° [Fig-
Consider the arrangement shown “kink” appears in the output, caus- ure 16(b)]. Plotted in Figure 16(c) are
in Figure 15(a), where quadra- ing considerable jitter. the interpolated waveforms, display-
ture inputs, VI and VQ , ideally yield To lessen the effect of process ing some nonlinearity; the phase
Vout = (VI + VQ ) /2. At t = t 12, the corners, we can add resistors to the spacing varies from 385 to 690 fs.
This issue can be alleviated through
the use of predistortion [10].
Inv1 Vout Vout
VI VI VI References
VDD VQ VDD VQ [1] B. Razavi, “Fifty applications of the CMOS
Vout 2 2 inverter—Part 1,” IEEE Solid-State Circuits
VQ Mag., vol. 16, no. 3, pp. 7–14, Summer
t1 t2 t1 t2 t 2024, doi: 10.1109/MSSC.2024.3419528.
t
t 12 [2] B. Casper et al., “A 20Gb/s forwarded
Inv2 clock transceiver in 90nm CMOS B.,” in
(a) (b) Proc. IEEE Int. Solid State Circuits Conf.
– Dig. Tech. Papers, San Francisco, CA,
USA, Feb. 2006, pp. 87–88. doi: 10.1109/
FIGURE 15: (a) Two inverters interpolating between quadrature inputs and (b) the kink ISSCC.2006.1696056.
problem. [3] A. Homayoun and B. Razavi, “Relation
between delay line phase noise and ring
oscillator phase noise,” IEEE J. Solid-State
Circuits, vol. 49, no. 2, pp. 384–391, Feb.
2014, doi: 10.1109/JSSC.2013.2289893.
VI R1 [4] L. Sun and A. Kwasniewski, “A 1.25-GHz
MUX

0.35-um monolithic CMOS PLL based on a

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