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JK Master

The document discusses the JK Master Slave Flip-Flop, highlighting the racing problem in level-sensitive sequential circuits and proposing edge sensitivity as a solution. It outlines the design flow for sequential circuits, which includes drawing a state diagram, state table, K-map, and circuit. An example of designing a 2-bit up counter using T flip-flops is provided, detailing the state table and K-map for the design.

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19 views5 pages

JK Master

The document discusses the JK Master Slave Flip-Flop, highlighting the racing problem in level-sensitive sequential circuits and proposing edge sensitivity as a solution. It outlines the design flow for sequential circuits, which includes drawing a state diagram, state table, K-map, and circuit. An example of designing a 2-bit up counter using T flip-flops is provided, detailing the state table and K-map for the design.

Uploaded by

Frank
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Sequential Circuits

Part-V

JK Master Slave Flip-Flop

All sequential circuits that we have seen in the last few pages have a problem
(All level sensitive sequential circuits have this problem). Before the enable
input changes state from HIGH to LOW (assuming HIGH is ON and LOW is
OFF state), if inputs changes, then another state transition occurs for the
same enable pulse. This sort of multiple transition problem is called racing.

If we make the sequential element sensitive to edges, instead of levels, we


can overcome this problem, as input is evaluated only during enable/clock
edges.

In the figure above there are two latches, the first latch on the left is called
master latch and the one on the right is called slave latch. Master latch is
positively clocked and slave latch is negatively clocked.
Sequential Circuits Design

We saw in the combinational circuits section how to design a combinational


circuit from the given problem. We convert the problem into a truth table, then
draw K-map for the truth table, and then finally draw the gate level circuit for
the problem. Similarly we have a flow for the sequential circuit design. The
steps are given below.

 Draw state diagram.


 Draw the state table (excitation table) for each output.
 Draw the K-map for each output.

 Draw the circuit.

Looks like sequential circuit design flow is very much the same as for
combinational circuit.

State Diagram

The state diagram is constructed using all the states of the sequential circuit in
question. It builds up the relationship between various states and also shows
how inputs affect the states.

To ease the following of the tutorial, let's consider designing the 2 bit up
counter (Binary counter is one which counts a binary sequence) using the T
flip-flop.

Below is the state diagram of the 2-bit binary counter.

State Table

The state table is the same as the excitation table of a flip-flop, i.e. what inputs
need to be applied to get the required output. In other words this table gives
the inputs required to produce the specific outputs.

Q1 Q0 Q1+ Q0+ T1 T0

0 0 0 1 0 1

0 1 1 0 1 1

1 0 1 1 0 1

1 1 0 0 1 1
K-map

The K-map is the same as the combinational circuits K-map. Only difference:
we draw K-map for the inputs i.e. T1 and T0 in the above table. From the table
we deduct that we don't need to draw K-map for T0, as it is high for all the
state combinations. But for T1 we need to draw the K-map as shown below,
using SOP.

Circuit

There is nothing special in drawing the circuit, it is the same as any circuit
drawing from K-map output. Below is the circuit of 2-bit up counter using the T
flip-flop.

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