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General Description Features

The AL3201 (SCR, or Single Chip Reverb)
16 internal ROM programs consisting
is a one chip reverb solution that is of halls, rooms, plates, delays, chorus,
compact, easy to use, and yet quite flange, vocal cancel, and rotary
powerful. Built-in DRAM eliminates the speaker emulation.
need for wide bus connections to external
Serially programmable SRAM (Writable
RAM, and the choice of built-in programs Control Store – WCS) for program
and a user programmable RAM allows development or dynamically changing
instant usability or custom program programs
design.
Programs run at 128 instructions per
word clock. (6 MIPS @ 48kHz sam-
pling frequency.)

32k location DRAM provides over 0.68s
of delay at 48kHz sampling frequency.

Internal crystal oscillator circuit
eliminates need for discrete external
passive components.

Internal voltage regulators allow opera-
tion at both 5V and 3.3V VDD.

Internal 1000pF bypass capacitor to
reduce voltage swings at the rails.

Applications

Personal stereos with reverb functions.

Extremely portable guitar effects boxes.

Karaoke machines utilizing the vocal cancel program.

Hardware reverb effects for computer sound cards.

Ambience settings for car stereos.

DigOut DigIn
16
1

AL3201

Int/Ext VDD
Bypass
SCR

XtalIn
XtalOut Gnd
Prog0/SData Reset
Prog1/SClk SysClk
Prog2 BitClk
Prog3 WordClk
9
8

16 pin SOIC
300 mils wide

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Electrical Characteristics and Operating Conditions
Parameter Description Condition Min Typ Max Units
Electrical Characteristics and Operating Conditions
VDD Supply Voltage 3.0/4.5 3.3/5.0 3.6/5.5 V
IDD Supply Current : SCR 6/9 7/10 8/11 mA
Gnd Ground Note 3 - 0.0 - V
FS Sample rate 24 1 48 50 1 kHz
Temp Temperature 0 25 70 °C
Outputs (DigOut, SysClk, BitClk, WordClk)
VOH Logical “1” output voltage Unloaded 0.9 VDD VDD - V
VOL Logical “0” output voltage Unloaded - 0 0.05 VDD V
IOH Logical “1” output current VDD=5V VO=4.5V - - -8.0 mA
IOL Logical “0” output current VDD=5V VO=0.4V - - 8.0 mA
_______________ __________________________

Inputs (DigIn, Int/Ext, Prog0/Sdata, Prog1/SClk, Prog2, Prog3, Reset) Notes 2,4
VIH Logical “1” input voltage 2.5 - VDD V
VIL Logical “0” input voltage 0 - 0.5 V
IIH Logical “1” input current VDD=VIH=5V - - 2 µA
IIL Logical “0” input current No pullup pin - - 2 µA
IILP Logical “0” input current Pullup pin, Vin=0 83 167 333 µA
CIN Input Capacitance - 2.0 - pF
Note:
1. Changing the sample rate (by changing the crystal frequency) will change the maximum delay
available through the DRAM proportionally. Low sample rates require more refresh instructions.
2. XtalIn, XtalOut are special pins designed to be connected to a crystal. XtalOut is a relatively weak pin
(about 0.2 mA) and should not be used to drive external circuits. Instead of using a crystal, XtalIn
may be driven by a standard VDD to Gnd logic signal, but the logic levels are not specified.
3. All other voltages are relative to Gnd.
4. Bypass (pin 14) must never exceed 3.6V

Pin Descriptions: AL3201 SCR (*: Pullup to VDD via nominal internal 30kΩ resistor)
Pin # Name Pin Type Description
1 DigOut Output Digital serial output for stereo DAC.
______________

2 Int/Ext Input* Internal/external program selection. 1:Internal, 0:External.

3 XtalIn Input 12.288MHz crystal input.
4 XtalOut Output 12.288MHz crystal output.
5 Prog0/SData Bidirectional* Internal program select 0 / serial interface data line.
6 Prog1/SClk Input* Internal program select 1 / serial interface clock line.
7 Prog2 Input* Internal program select 2.
8 Prog3 Input* Internal program select 3.
9 WordClk Output Word clock output.
10 BitClk Output Bit clock output.
11 SysClk Output System clock output.
_____________________

12 Reset Input Active low reset.

13 Gnd Ground Ground connection.
14 Bypass Bidirectional Connect 0.1µF bypass capacitor to Gnd for internal +3.3V regulator.
15 VDD Power +5V/+3.3V VDD power pin. Connect 0.1µF capacitor to Gnd.
16 DigIn Input Digital serial input from stereo ADC.

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Block Diagram

Mechanical Specification
Dimensions (Typical)
Inches Millimeters
A .406” 10.31
B .295” 7.49
C .407” 10.34
16 9
D .100” 2.50
E .008” 0.20
C B F .025” 0.64
G .050” 1.27
1 8
H .017” 0.42
J .011” 0.27
K .340” 8.66
L .033” 0.83
A Notes:
1) Dimension “A” does not include mold
flash, protrusions or gate burrs.
7° nom
K

D 4° nom

E H J L
G
F

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Internal Programs
The SCR comes with 16 internal ROM
programs ready to go, utilizing the skills
and techniques of the Alesis Studio
Electronics effects processor programmers.
By setting the chip to internal mode, the
four program pins may be used to select
between the different algorithms.

Program List
Prg Name Description
125ms slapback delay for
0* Delay 1
vocals and guitars.
Auto-wah guitar effect with
1 Chorus/Room 2
reverb for lead instruments.
Warm hall for acoustic
2 Hall 2
guitars, pianos, and vocals.
Removes lead vocals from
3 Vocal Cancel
many stereo recordings.
190ms delay for percussive
4* Delay 2
arpeggios.
Chorus with reverb for
5 Chorus/Room 1
guitars, synths, and pianos.
Bright hall reverb for
6 Hall 1
drums, guitars, and vocals.
Rotary speaker emulation
7 Rotary Speaker
for organs and guitars.
Stereo flanger for jet wash
8 Flange
effects.
Sizzling bright plate reverb
9 Plate 2
for vocals and drums.
Hardwood studio for
10 Room 1
acoustic instruments.
Classic plate reverb for lead
11 Plate 1
vocals and instruments.
Stereo chorus for guitars
12* Chorus
and pianos.
Short vintage plate reverb
13 Plate 3
for snares and guitars.
Ambience for acoustic
14 Room 2
mixes and synth sounds.
Warm room for guitars and
15 Room 3
rhythm instruments.
Note: The unusual ordering of the programs allows a
16-position rotary switch’s Gray code output to be
connected to the program pins. The sequence of
programs is then Halls 1-2, Rooms 1-3, Plates 1-3,
Chorus, Flange, Delays 1-2, Chorus/Rooms 1-2,
Vocal Cancel, and Rotary Speaker.
* WARNING
Programs 0, 4, and 12 do not meet refresh
requirements. Do not depend upon these programs
working in any application.

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Programming the RAM The first four instructions in the WCS RAM
set the parameters for the four LFOs. The
Alongside the 16 internal programs is an sinusoid generated by the LFOs is of the
externally programmable SRAM that is formula Asin(nF/M) or Acos(nF/M), where
easily accessible through the serial clock n is the time index, F/M = 2πf/FS, M is the
and data pins. By setting the chip to maximum internal value, f is the selected
external mode, the SClk and SData pins frequency, and FS is the sampling
become available for serial frequency. Thus the frequency extrema
communication. Except for its external are:
programmability, there is no functional f = (F/M) FS/(2π)
difference between the SRAM and the
fmin = (0x1/0x3ffff) (48kHz)/(2π)
internal ROMs.
= 0.029Hz
Memory Map fmax = (0x1fff/0x3ffff) (48kHz)/(2π)
Addr Name = 239Hz
Addr Name Triangle waves are generated by incremen-
0:127 WCS RAM 0:3 LFO Coefficients tally adding or subtracting 0x400000*F/M
4:127 MAC Instructions (= 222*F/M) from the maximum internal
128 Control/Status 0
negative or positive value respectively. Its
129 Control/Status 1 frequency extrema are then:
f = # Samples / # Steps
A simple assembly language is available
= FS / (4 Max/Increment)
for writing programs. With the assembler
= FS / (4 0x7fffff/(222*F/M))
and loader software available from the
Alesis Semiconductor website, programs fmin = 48kHz / (8/(0x1/0x3ffff))
may be developed on the PC and = 0.023Hz
downloaded into the chip. Please refer to fmax = 48kHz / (8/(0x1fff/0x3ffff))
the assembly language guide for a full = 187Hz
description. When chorus instructions are used,
addresses are offset by the output an LFO.
LFO Coefficient Word The range of this offset is plus and minus
Bit # Description A/8 samples, or A/4 samples total.
31 P: Pitch shift mode select (S must be set). 1
Following the 4 LFO coefficient words are
30 S: Sine/triangle select. 1:Triangle; 0: Sine.
124 MAC instruction words. These
X[1:0]: Crossfade X[1:0] Xfade
instructions allow the manipulation of the
coefficient select. Value 11 1/16
29:28 indicates the fraction of a 10 1/8 DRAM and the waveforms generated by
half sawtooth period 01 1/2 the LFOs.
used in crossfading. 00 1 A good NOP instruction is 0x00030000.
27:15 F[12:0]: Frequency coefficient, unsigned. This instruction preserves the value in all
14:0 A[14:0]: Amplitude coefficient, unsigned. registers, and is the NOP executed in the
Note: MAC during the first four ticks of every
If set, the output waveform is a sawtooth with double
the triangle wave’s frequency.
sample period while the LFO coefficients
are loaded.
By judiciously choosing the LFO frequency
Sawtooth SIN
and waveform with which to sweep
Sawtooth COS through the DRAM, it is possible to
generate pitch shifts, flanges, choruses,
Crossfade 1 reverbs, and other effects. Please see
Crossfade 1/2 application notes for descriptions and
examples.
Crossfade 1/8

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MAC Instruction Word 5. Register B, if clocked at the end of the tick, will
Bit # Description store the value of the current tick’s multiplicand.
When a read is executed, B latches LeftIn,
31 S: Sign bit for multiplier coefficient. RightIn, or DRAM. When a write is executed, B
C[7:1]: Multiplier coefficient, 2’s complement. latches the accumulator from the last tick.
C[7:0]: Chorus instruction. Only the 7 MSBs 6. The accumulator contains the result from the
are used as multiplier coefficients. The LSB is last instruction tick, and is updated at the end of
used in chorus mode. If I[5] is set, C[7:0] is: the current instruction tick.
C Description 7. The internal DRAM address offset automatically
Chorus/Xfade select: decrements by 1 every word clock period.
1: Pass LFO address to address 8. Because addresses 0x0000 and 0x0001 are
7 generator & select chorus coefficient. being used to access the left and right channels,
0: Mask LFO address to address those DRAM memory locations may not be
30:23 generator & select crossfade coefficient. directly written to or read from.
1’s complement the LFO address sign
6
bit. 1
5 1’s complement the LFO coefficient.
4 1’s complement the LFO address.
LFO latch. 1: Latch in new LFO data;
3
0: Hold last LFO data. 2
2:1 LFO select.
0 LFO sine/cosine select. 1: Cos; 0: Sin.
22 W: Write select. 3, 4
I[5:0]: Instruction field.
I Description
Chorus select (When set, MAC
coefficient is LFO block output, LFO
5
address offset added to DRAM
address).
4 Clock register C. 3
21:16
3 Clock register B. 4
2 Reserved – set to zero.
I[1:0] Instruction
MAC
11 Acc = Prod + Acc 6
product
1:0 10 Acc = Prod + C 3
instruc-
tion. 01 Acc = Prod + B 5
00 Acc = Prod + 0
A[15:0]: Multiplicand address. 7, 8 (Currently
only lower 15 bits used; reserve MSB for
15:0 future expansion.)
Address 0x0000 = LeftIn/Out;
Address 0x0001 = RightIn/Out.
Notes:
1. This complement is only for the MSB, and sign-
extension bits are not affected.
2. Upon latching new data, the LFO registers will
store the lower or upper LFO pairs’
sinusoid/triangle waves, and the lower or upper
LFO pairs’ crossfade coefficient. I.e. there are
two pairs of registers; LFO 0/1’s sinusoid
/triangle/crossfade will be latched together, and
LFO 2/3’s sinusoid/triangle/crossfade will be
latched together.
3. The LeftOut, RightOut, and C registers are in
parallel with the accumulator, and will contain
the same value as the accumulator if clocked at
the end of the tick.
4. A write to DRAM stores the last tick’s results into
address A. Writes to LeftOut or RightOut should
use the Acc = Product + Acc instruction with the
multiplier coefficient set to 0 to pass all bits
unaltered.

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Control/Status Word 0 its execution. Otherwise reads and writes to the
Instruction RAM will usurp the address bus to
Bit # Description the RAM and cause address jumps in the
31:30 Reserved. Set to zero. instruction sequence. With I deasserted, reads
29:16 B[13:0]: DRAM read data. 1 and writes to each address may take up to one
15:11 Reserved. Set to zero. word clock period to complete. Thus during
continuous writes, the start of each instruction
O: MAC overflow. Self-clears after read. Read word should be at least one word clock period
10
only. apart, and during reads the serial clock should
9 P: Self test pass. Read only. wait 1 word clock after the address before
R: Ready indication. Read/write/test/clear continuing.
8
complete. 8. The DRAM self test cycle will run to completion
M: DigOut mute in external mode. Resets even if S[0] is deasserted. It may not be
7 cancelled.
to 1.
Z: DRAM zero. Initiates zeroing cycles until 9. A DRAM self test cycle takes approximately
6 10.66ms to complete with a 12MHz crystal.
deasserted. Resets to 0. 2, 3, 4, 5, 6
X: DRAM zero cancel. Prevents zeroing
5 circuitry from running until deasserted. Control/Status Word 1
Overrides Z. Resets to 0. 3
Bit # Description
L: LFO reset pulse. Resets LFO internal
4 status registers and clears overflow flag. Self R: Read select. Read data from DRAM
address A[15:0] and put data in B of
clearing. Resets to 0. 31
control/status word 0. Self-clears after
I: Instruction RAM direct mode. Resets to 1.
completion.
1: Instructions are written/read as soon as
W: Write select. Write data D[13:0] to DRAM
3 received; 0: Instructions are written/read 30
address A[15:0]. Self-clears after completion.
when the address counter rolls around to
matching address. 7 29:16 D[13:0]: DRAM write data.
2 Reserved. Set to zero. A[15:0]: DRAM address. The MSB is unused
15:0
and reserved for future expansion.
S[1]: DRAM self test pattern select.
1 1: Load DRAM with 2AAA/1555 checkerboard; Note: Reading and writing DRAM will usurp DRAM
0: Load DRAM with 1555/2AAA checkerboard. access for one cycle, possibly disrupting proper code
S[0]: DRAM self test initiate. Self-clears after execution.
0
test completion. Resets to 0. 2, 3, 6, 8, 9
Notes: Other notes:
1. The floating point format used in the DRAM is: 1. When in internal mode, program
E[2:0].S.F[9:0], where E is the exponent, S is the changes will start a DRAM zero cycle.
sign bit, and F is the fractional portion. The
expansion of the floating point into fixed point is 2. Resets always start a DRAM zero cycle.
as follows: 3. To meet refresh requirements below 70
If E<7, S E*S !S FFFFFFFFFF (8-E)*0 °C, access each address (modulo 1024)
(where E*S means E number of S bits).
every 1.34 ms. If program code doesn't
If E=7, S SSSSSSS FFFFFFFFFF 00.
This method encodes one extra bit for sign do this, then (at 48 kHz) read 16
extensions less than 7 bits. locations each cycle spaced 1024/16 =
2. The DRAM zeroing circuitry and DRAM self test 64 addresses apart, to meet refresh
circuitry share gates; do not turn more than one
requirements. (For instance, addresses
on at a time.
3. The DRAM zeroing cycle will run to completion 0x0002, 0x0042, ..., 0x03C2.)
even if Z deasserted. Only the X bit may cancel 4. ROMs may not be read due to the
it mid-cycle. Until the cycle ends, self test serial interface becoming the program
results will be inaccurate. Thus do not deassert
select interface when in internal mode.
Z and assert S[0] at the same time. Rather,
assert X and S[0] at the same time. 5. Use of Reset is mandatory to obtain
Note that Z does not self-clear, and will affect proper operation of the AL3201.
both internal and external mode.
4. After a DRAM zeroing cycle has completed, do
The 4 word formats: LFO, MAC, CS0, CS1
not start another for one word clock period.
5. A DRAM zeroing cycle takes approximately LFO: PSXXFFFF FFFFFFFF FAAAAAAA AAAAAAAA
5.33ms to complete with a 12MHz crystal. MAC: SCCCCCCC CWIIIIII AAAAAAAA AAAAAAAA
6. During DRAM zeroing and test cycles, reads and CS0: --BBBBBB BBBBBBBB -----OPR MZXLI-SS
writes to the DRAM are ignored.
7. For dynamically changing programs, deassert I CS1: RWDDDDDD DDDDDDDD AAAAAAAA AAAAAAAA
so that changing the program does not interrupt

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Serial Interface Format
The basic format for the micro serial interface is:
Attn Sel R/W A7 A6 A5 A4 A3 A2 A1 A0 DN DN-1 DN-2 … D2 D1 D0 Attn Desel
⇓ ⇓
Attn: A 0-1-0 is used to signal attention/start. Write mode only
Sel/Desel: 0:Select; 1:Deselect. A7 - A0: Address
R/W: 0:Read; 1:Write DN - D0: Data

Notes: 2. As long as data is being sent during a write, the

1. There is a short period of High-Z during a read address will be automatically incremented.
between A0 and the first data bit shifted out. Therefore only a start address need be sent.
This period must be at least 5 system clocks 3. The phase of the clock is unimportant.
long, 1 word clock long if not in direct mode
(CS0[3]).

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-8-
DigIn/DigOut Interface Format

Suggested Connections

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 NOTICE
Alesis Semiconductor reserves the right to make changes to their products or to discontinue
any product or service without notice. All products are sold subject to terms and conditions
of sale supplied at the time of order acknowledgement. Alesis Semiconductor assumes no
responsibility for the use of any circuits described herein, conveys no license under any
patent or other right, and makes no representation that the circuits are free of patent
infringement. Information contained herein are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has
been carefully checked, no responsibility is assumed for inaccuracies.

Alesis Semiconductor products are not designed for use in applications which involve
potential risks of death, personal injury, or severe property or environmental damage or life
support applications where the failure or malfunction of the product can reasonably be
expected to cause failure of the life support system or to significantly affect its safety or
effectiveness.

All trademarks and registered trademarks are property of their respective owners.

Contact Information:

Alesis Semiconductor
12555 Jefferson Blvd., Suite 285
Los Angeles, CA 90066
Phone: (310) 301-0780
Fax: (310) 306-1551

Email: sales@alesis-semi.com

Copyright 2002 Alesis Semiconductor

Datasheet August 2002
Reproduction, in part or in whole, without the prior written consent of Alesis
Semiconductor is prohibited.

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Phone (310) 301-0780 Fax (310) 306-1551 www.alesis-semi.com
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