Tutorial : Opamps

1. The circuit shown below uses an op amp that is ideal except for having a finite gain A. Measurements indicate
vO = 4.0 V when vI = 1.0 V. What is the op-amp gain A?
2. A particular inverting circuit uses an ideal op amp and two 10-kΩ resistors. What closed-loop gain would you
expect? If a dc voltage of +1.00 V is applied at the input, what outputs result? If the 10-kΩ resistors are said
to be “1% resistors,” having values somewhere in the range (1 ± 0.01) times the nominal value, what range of
outputs
120 Chapter wouldAmplifiers
2 Operational you expect to actually measure for an input of precisely 1.00 V?
3. Design an inverting amplifier with a gain of 46 dB having the largest possible input resistance under the
the finite A, a resistor Rc is shunted across R1 . Show D 2.29 An inverting op-amp circuit using an ideal op amp
that perfect compensation
constraintisof achieved
havingwhentoRcuse
is selected mustno
resistors be designed
largertothan
have a1gain
MΩ.of −500 V/V using
What is theresistors
input resistance of your design?
according to no larger than 100 k!.
4. Show that
R for
A − Gthe inverting amplifier
c (a) For if
the the op-amp
simple two-resistorgain
circuit,iswhat
A,input input resistance is given by 𝑅𝑖𝑛 = 𝑅1 +
theresistance
=
R1 1+G would result?
D *2.26
𝑅2/(𝐴 + 1).
(a) Use Eq. (2.5) to obtain the amplifier open-loop
(b) If the circuit in Fig. 2.8 is used with three resistors of
maximum value, what input resistance results? What is
gain A required to realize a specified closed-loop gain
5. The inverting circuit with the T network
(Gnominal = −R2 /R1 ) within a specified gain error e,
the value ofinthethe feedback
smallest resistor needed?is redrawn below in a way that emphasizes the
! ! 2.30 The inverting circuit with the T network in the feedback
observation
e ≡ !!
! G − Gthat
nominal !R2 and R3 in effect are in parallel (because the ideal op amp forces a virtual ground at
! the
! is redrawn in Fig. P2.30 in a way that emphasizes the
Gnominal
observation that R2 and R3 in effect are in parallel (because 124 Chapter 2 Operational Amplifiers
(b) Design aninverting inputforterminal).
inverting amplifer Use thisthe
a nominal closed-loop observation to derive an expression for the gain (vO/vI ) by first finding
ideal op amp forces a virtual ground at the inverting input
(vX
gain of −100, an input resistance of 1 k!, and a gain error of terminal). Use this observation to derive an expression for the
rule applied to R4 and (R2 ∥R3). I

PROBLEMS
≤10%. Specify/vIR)1 , and
R2 , and(v O/v
the X ). For
minimum the latter usegain
A required. the(vvoltage-divider
O /v I ) by first finding (v X /v I ) and (v O /v X ). For the latter 10R b
*2.27 (a) Use Eq. (2.5) to show that a reduction "A in the use the voltage-divider rule applied to R4 and (R2 & R3 ).
c
op-amp gain A gives rise to a reduction "|G| in the magnitude
R2 vX R4 2
of the closed-loop gain G with "|G| and "A related by
o
"|G|/|G| 1 + R2 /R1 R3 a
$
CHAPTER 2

"A/A A A
" # i
R "A iI
Assume that 1 + 2 % A and % 1. 10R
R1 A vI ! 2
(b) If in a closed-loop amplifier with a nominal gain (i.e., R1 0V vO c
R2 /R1 ) of 100, A decreases by 10%, what is the minimum " r
nominal A required to limit the percentage change in | G | to l
0.1%? Figure P2.50

2.28 Consider the circuit in Fig. 2.8 with R1 = R2 = R4 = Figure P2.30

1 M!, and assume the op amp to be ideal. Find values for R3
D 2.51 The circuit shown in Fig. P2.51 utilizes a 10-k!
6.the The
to obtain circuit
following gains: shown below utilizes*2.31 a 10-kΩ potentiometer
The circuit toconsidered
in Fig. P2.31 can be realizetoan adjustable-gain
be an amplifier.
potentiometer to realize Derive
an adjustable-gain an Derive
amplifier.
extension of the circuit in Fig. 2.8. an expression for the gain as a function of the potentiometer
(a) −100 V/V
(b) −10 V/V
expression for the gain as a function of the potentiometer setting x. Assumesetting
(a) Find the resistances looking into node 1, R1 ; node 2, R2 ;
thex.op amptheto
Assume op be
amp ideal. What
to be ideal. What isisthe range
(c) −2 V/V node 3, R3 ; and node 4, R4 . of gains obtained? Show how to add a fixed resistor so that
the range of gains obtained? Show how to add a fixed resistor so that the gain therange can
gain range can be
be 11to to 11 V/V.
11 V/V. What
What should the resistor
value be?
should
R
the
1
resistor
R/2
value
2
be?
R/2 3 R/2 4

D
I R1 R R2 R R3 R R4 1
I4 a
I1 I2 I3
g
2 r
0V
m
1
u
u
Ideal
Figure P2.51 2
Figure P2.31 c
7. Given the availability of resistors of value 1 k Ω and 10 k Ω only, design a circuit based on the noninverting t
D 2.52 Given the availability of resistors of value 1 k!
= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem o
configuration to realize a gain of +10 V/V. What is the input resistance of your
and 10amplifier?
k! only, design a circuit based on the noninverting
1
configuration to realize a gain of +10 V/V. What is the input
t
resistance of your amplifier?
o
2.53 It is required to connect a 10-V source with a source a
resistance of 1 M! to a 1-k! load. Find the voltage that will
2
 (c) 100 V/V

PTER 2
b +1 10 (d) 0.5 V/V
c −1 100
d +10 10 2.62 For the circuit shown in Fig. P2.62, express v O as a
8. e For the −10
circuit shown100below, express vO asofav 1function
function and v 2 . What
ofisvthe1 and
input vresistance seen by v 1
2. What is the input resistance seen by v 1
f −10 1000 alone? By v 2 alone? By a source connected between the two

PROBLEMS
g alone? By
+1 v2 alone? By input terminals?
2 a source connected By a source
between the connected
two input to both input terminals
terminals? By a source connected to both
simultaneously?
.59 Figure P2.59input terminals
shows simultaneously?
a circuit that provides an output
oltage v O whose value can be varied by turning the wiper of
he 100-k! potentiometer. Find the range over which v O can
e varied. If the potentiometer is a “20-turn” device, find the
hange in v O corresponding to each turn of the pot.

25
Figure P2.62

9. For the difference amplifier shown above, let all the resistors be 10 kΩ ± x%. Find an expression for the worst-
Consider the
2.63Evaluate
case common-mode gain that results. thisdifference
for x = amplifier of Fig.
0.1. Also, 2.16 with
evaluate the resulting CMRR. Neglect
the two input terminals connected together to an input
the effect of resistor tolerances on Acommon-mode
d. signal source. For R2 /R1 = R4 /R3 , show that
25 the input common-mode resistance is (R3 + R4 )" (R1 + R2 ).
10. Consider the instrumentation amplifier taught in the class with a common-mode input voltage of +3 V (dc)
2.64 Consider the circuit of Fig. 2.16, and let each of the
and a differential input signal of 100
v I1 -mV
and v I2peak
signalsine wave.
sources have aLet 2Rresistance
series 1 = 2 kΩ, Rs . R2 = 50 kΩ, R3 =R4 =10 kΩ. Find
What
condition must apply in addition to the condition in Eq. (2.15)
the voltage at every node in the circuit.
in order for the amplifier to function as an ideal difference
Figure P2.59
amplifier?
Section 2.4: Difference Amplifiers *2.65 For the difference amplifier shown in Fig. P2.62, let
all the resistors be 10 k! ± x%. Find an expression for the
.60 Find the voltage gain v O /v Id for the difference amplifier
worst-case common-mode gain that results. Evaluate this for
f Fig. 2.16 for the case R1 = R3 = 5 k! and R2 = R4 =
x = 0.1, 1, and 5. Also, evaluate the resulting CMRR in each
00 k!. What is the differential input resistance Rid ? If the
case. Neglect the effect of resistor tolerances on Ad .
wo key resistance ratios (R2 /R1 ) and (R4 /R3 ) are different
rom each other by 1%, what do you expect the common-mode 2.66 For the difference amplifier of Fig. 2.16, show that if
ain Acm to be? Also, find the CMRR in this case. Neglect the each resistor has a tolerance of ±100 e% (i.e., for, say, a
ffect of the ratio mismatch on the value of Ad . 5% resistor, e = 0.05) then the worst-case CMRR is given
D 2.61 Using the difference amplifier configuration of approximately by
ig. 2.16 and assuming an ideal op amp, design the circuit ! "
o provide the following differential gains. In each case, the K +1
CMRR # 20 log
ifferential input resistance should be 20 k!. 4e

= Multisim/PSpice; * = difficult problem; ** = more difficult; *** = very challenging; D = design problem