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Low-Power Digital Signal Processor Design for a Hearing Aid

Conference Paper · December 2013

DOI: 10.1109/ICEAC.2013.6737634

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 2013 4th Annual International Conference on Energy Aware Computing Systems and Applications (ICEAC)

Low-Power Digital Signal Processor Design for a

Hearing Aid
Lama Shaer Ihab Nahlus Jawad Merhi Ayman Kayssi Ali Chehab
Department of Electrical and Computer Engineering
American University of Beirut
Beirut 1107 2020, Lebanon
{las24,inn02,jrm02,ayman,chehab}@aub.edu.lb

Abstract — A new low-power digital signal processor (DSP) battery life and thus further satisfy hearing aid users. We
design for a hearing aid system is proposed. A stochastic utilize a method that has been used in our previous work for
method was applied to the DSP in order to fulfill the needs of a low-power adder [19]. We investigate the design of each
the hearing aid system, considered to be an error-tolerant
of the different building blocks of this processor and then
system. The different blocks that form the DSP are presented
apply our low-power technique to the DSP, and verify its
in this paper. The implementation and layout were performed
and simulated using a 90 nm CMOS process. Simulation
correctness using HSPICE and VHDL. The overall DSP
results showed excellent energy consumption savings in the design was then implemented using Cadence. The results
range of 4.5x to 10x of the proposed DSP design when show the practicality of this DSP for error-tolerant
compared to similar DSPs. applications.

Keywords: digital signal processor, low power, stochastic, The rest of the paper is organized as follows: Section II
error-tolerant, energy consumption, hearing aid system. discusses related work. The design of our system is
presented in section III. Section IV discusses the
I. INTRODUCTION implementation of the system, and section V presents the
Despite the continuous aggressive scaling of CMOS testing results. We conclude with a summary and potential
technology and integrated circuits, the progression of future work in section VI.
battery technology at the hardware level is relatively very
slow. The shortness of battery lifetime has been raised as a II. RELATED WORK
critical issue as batteries are used in almost all portable and There are many different architectures and design
wearable electronic devices. As a result, the low energy structures for a digital signal processor. Some methods are
aspect has become an essential design factor for almost all based on generic core architectures for a DSP processor.
such devices. The authors of [2] presented a DSP circuit that was built
This paper focuses on reducing energy consumption for according to a generic architecture and included analog-to-
hearing aid systems through the use of stochastic low power digital and digital-to-analog converters for hearing
digital signal processors (DSP). DSPs are considered instruments. Also, P. Mosch et al. [3] described a generic
essential blocks in hearing aid systems and reducing power technique to build a low-power DSP.
dissipation in them reduces the total energy consumed by Other methods rely on building Fast Fourier Transform
the device. Although a stochastic DSP produces inaccurate (FFT) and Interpolated Finite Impulse Response (IFIR)
results, this does not create problems when the target processors. K. Chone et al. [4] described an FFT processor
application is error-tolerant. Any application where results and an inverse FFT processor for low-voltage and energy-
are perceived by human hearing and vision systems is error critical hearing aid systems. L. S. Nielsen and J. Sparsoe [5]
resilient and can be based on a stochastic processor [1]. The presented an IFIR processor that relies on a filter bank
errors associated with voice do not cause problems to users structure for the use in low power devices.
as witnessed by multimedia applications such as Skype.
Most designs however rely on Application Specific
In this paper, we present a DSP processor that operates Integrated Circuit (ASIC) designs for the DSP processor.
at low power while introducing some inaccuracies in the
The authors of [6-8] present designs that include the use
computations. The purpose of this processor is to reduce the
of a filter bank structure where the frequency band is split
energy consumption of hearing aid systems to prolong the

978-1-4799-2543-8/13/$31.00 ©2013 IEEE 40

 2013 4th Annual International Conference on Energy Aware Computing Systems and Applications (ICEAC)

into multiple bands, and then each band is processed power and requires a large area [17]. We still need
individually. R. Brennan and T. Schneider [6] describe a multipliers for the volume control and the gains, however.
flexible filter bank structure for hearing aid applications
taking into consideration the following requirements:
limited memory, low power, and low delay. K. Chong et al.
[7] present an FIR filter bank core with micro energy
consumption and small area, with the advantages of a higher
stop band attenuation and linear phase frequency response
as compared to other designs. The authors of [8] present a
low power design of a filter bank for digital hearing aids
whereby a multi-rate FIR filter bank algorithm was
developed and it showed that in comparison with a
straightforward FIR filter bank, 96% of the multiplications
and additions are saved.
Although the use of a filter bank structure as presented in Figure 1: Digital Filter [11]
[6-8] grants a higher control over the different bands, two
The transfer function of this filter is expressed in[11] as
bands are usually enough: a high band and a low band. The
follows:
most common designs consist of a band split filter that splits
the frequency band into a high band and a low band as ‫ܪ‬ሺ‫ݖ‬ሻ ൌ ܸ‫ܥ‬ൣͲǤͷሺͳ ൅ ‫ܩ‬଴ ሻሺͳ ൅ ‫ି ݖ‬ସ ሻ
presented in [9-12]. Each band is then processed by itself; it െ ൫‫ܩܭ‬ଵ ൅ ‫ܩ‬ଶ ሺ‫ ܰܫ‬െ ‫ܭ‬ሻ൯ሺͲǤͷ െ ͲǤͷ‫ି ݖ‬ସ ሻ௣ ൧
is multiplied by a gain whose value can be manipulated
through a serial interface or imported from memory, hence B. Adder
making the hearing aid tunable. Some designs use an In order to make the DSP stochastic, we apply a method
automatic gain control (AGC) to ensure that the gain does that we previously used for the design of a ripple carry
not overshoot as in [10]. Other designs have a serial adder and whereby we achieved 167% savings in energy
interface combined with the RAM instead of having them consumption [19]. The method consists of applying multiple
separated as in [11]. In addition, some designs have a supply voltage levels to different parts of the circuit and
volume control to digitally control the gain of the aid as in making sure that the voltage level is adequate on the critical
[9-11]. path in order not to affect performance. The parts that are
affected might generate some errors but are associated with
III. SYSTEM DESIGN the least significant bits. Hence, we achieve substantial
A. Digital Filter energy savings while allowing for small errors only (in the
low-order bits) to be introduced.
In our design, we are targeting a simple hearing aid that
provides a basic functionality with minimal energy C. Multiplier
consumption. The multiplier is the most critical component of the DSP
The digital filter used is shown in Figure 1. This filter since it is the slowest and therefore, it will define the
uses a band-pass filter and a notch filter [17]. In contrast to frequency of operation. Sequential multipliers were used in
the traditional band-splitting scheme with a low-pass and a the DSP design whereby we are either multiplying 16 bits
high-pass infinite impulse response (IIR) filters, this by 4 bits or 20 bits by 4 bits. Therefore, we used 16×4 and
structure uses an FIR filter and reduces both power 20×4 sequential multipliers that consist of a maximum of 3
consumption and physical size while obtaining comparable additions. These multipliers perform much less
results. This is because the IIR filter suffers from finite computations than other commonly used multipliers and
word-length problems and consumes more power than the hence consume much less energy.
FIR filter [18]. Moreover, the IIR filter has inevitable error In our sequential 16×4 multiplier, we multiply the 16 bits
accumulation and phase non-linearity. Another reason why by 2, 4, and 8 and we obtain 4 modified versions of the
this transfer function is widely used is because the input (including itself), which are then fed to multiplexers.
coefficients of the filter are powers of 2; consequently, we The other 4 bits serve as control signals to these
can do hardwired shifting for most parts instead of using multiplexers. Finally, The 4 outputs of the multiplexers are
many multipliers whereby each multiplier consumes a high

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 2013 4th Annual International Conference on Energy Aware Computing Systems and Applications (ICEAC)

added using three 20-bit ripple-carry adders. The same is

done for the 20×4 multiplier.
D. Delay Unit
We have used several delay units in the DSP design that
were implemented using D flip-flops.
The DSP was implemented using static CMOS since it
leads to relatively lower energy consumption and most
importantly it leads to a more robust design. Robustness is a
very important characteristic because while applying the
stochastic technique, the noise margins will shrink due to
reduced supply voltage levels.
E. Multi VDD Design
We already know that reducing the voltage supply will
Figure 3: DSP Schematic
reduce power consumption but will increase delay. Some
components in the DSP processor might need to be fast We also extracted the design to HSPICE after setting the
while others are more elastic when it comes to speed. This is minimum parasitic resistance value to 250 ȍ and the
why we chose to have multiple voltage supplies in our minimum parasitic capacitance value to 10-15 F. This
circuit so we can satisfy both the speed and energy extraction had around 450 resistors and 10,000 capacitors.
requirements. The area occupied by the DSP layout (shown in Figure 4) is
roughly 39000 nm2.
Typically, the availability of different supplies on one
chip is not a problem due to voltage islands and DC-to-DC
converters already present on the chip. As stated in [20],
two to four supplies are more than enough. We chose to use
two voltage supplies, referred to as VDDHIGH and VDDLOW

IV. SYSTEM IMPLEMENTATION

The DSP consists of several blocks and sub-blocks as
shown in Figure 3 (as extracted from Cadence):

(A) twelve 16-bit flip-flops

(B) five 16-bit ripple carry adders (RCAs)

(C) three 20-bit RCAs

(D) three 16x4 multipliers

(E) one 20x4 multiplier

(F) two 16-bit multiplexers

(G) one 16-bit multiplexer.

Figure 4: DSP Layout

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 2013 4th Annual International Conference on Energy Aware Computing Systems and Applications (ICEAC)

V. TESTING RESULTS TABLE I. Case I Results

We generated a vector file for the inputs of the DSP
Supply Voltage (V) Power Consumption (ȝW)
using JAVA’s pseudo random number generator. Our target
was to vary VDDHIGH and VDDLOW to reach maximum savings 0.8 120
in power consumption, even if this incurs some errors in the 0.7 86.22
system. The clock frequency used was set to 10 MHz. 0.6 57.36
0.5 37.08
There are two major steps in checking for the validity of 0.4 21.93
the DSP design. We need to check the correctness of the 0.3 9.841
design itself and the post simulation results. To establish the
first step, we designed the filter using VHDL and simulated
it while inputting a raw audio file and outputting the When the two supplies were further reduced to 0.3 V, the
modified raw audio file. Then, the modified raw audio file digital signal processor started producing some errors. If we
was converted into a usable format (MP3) and compared to
are to use this supply level, we can save an additional 10%
the original MP3 file. This is summarized in Figure 5.
in power consumption, summing up to a total 92%. The
percentages of errors in each bit in the output O are
presented in Table II, where O23 is the most significant bit
(MSB) and O0 is the least significant bit (LSB) of the
output.

Figure 5: Verifying Correctness (step1)

TABLE II. Percentage Errors in Bits

After validating the design, we proceeded to the second O0 O1 O2 O3 O4 O5 O6 O7

step, which is verifying the correctness at the bit level by 25% 15% 25% 60% 60% 10% 25% 35%
comparing the output of the HSPICE simulator to the output
of the VHDL simulator. We simulated the random vectors O8 O9 O10 O11 O12 O13 O14 O15
coming out of JAVA’s pseudo random number generator. 25% 15% 25% 35% 20% 10% 40% 15%
This is illustrated in Figure 6.
O16 O17 O18 O19 O20 O21 O22 O23
20% 25% 15% 15% 10% 10% 10% 10%

B. Case II: Scaling VDDLOW

In this case, several combinations for VDDHIGH and
VDDLOW were tested in order to achieve a good reduction in
energy consumption yet with reasonable errors that do not
affect the most significant bits, as was the case in the
Figure 6: Verification (step 2) previous test scenario. The results are summarized in Table
III.
Here, two cases were tested. The first is the case in
which both supply voltages were scaled down, and the TABLE III. Case II Results
second is the case where only VDDLOW was scaled down.
Power Consumption
Test VDDHIGH VDDLOW
A. Case I: Scaling Both Supply Voltages (uW)
In this case, both voltage supply voltages were gradually
1 0.8 0.7 118.5
scaled down from 1 V to 0.3 V. The results are summarized
in Table I. 2 0.8 0.6 98.6

We can see that there is a 90% reduction in power 3 0.8 0.3 92.1
consumption from the case of normal VDD (1 V) to the case 4 0.7 0.5 87.32
where both supply voltages were set to 0.4 V. In this
specific case, the system was fully functional without errors.

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 2013 4th Annual International Conference on Energy Aware Computing Systems and Applications (ICEAC)

As seen from Table III, the power consumption was [6] Brennan, R.; Schneider, T.; "A flexible filterbank structure
reduced in tests 2, 3 and 4. For test 1, the reduction in power for extensive signal manipulations in digital hearing aids,",
IEEE International Symposium on Circuits and Systems,
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expected, the power consumption was still higher than what for Digital Hearing Aids," IEEE Transactions on Circuits and
Systems II: Express Briefs, , vol.53, no.9, pp.853-857, Sept.
we got in Case I.
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Comparing our design to other designs in literature, the [8] Yu-Ting Kuo; Tay-Jyi Lin; Yueh-Tai Li; Chih-Wei Liu;,
results show a major improvement. It was previously "Design and Implementation of Low-Power ANSI S1.11
Filter Bank for Digital Hearing Aids," IEEE Transactions on
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[11]. Comparing this value with the values of Case I 2010.
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respectively. Controller," the 32nd European Solid-State Circuits
Conference (ESSCIRC’06), pp.231-234, 19-21 Sept. 2006.
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