Features of PIC18FXXX Series Microcontrollers

• Important Features of PIC18FXXX Series Microcontrollers are:

1. Harvard architecture: PIC uses Harvard architecture. Harvard architecture has the program memory
and data memory as separate memories and are accessed from separate buses. This improves bandwidth
over traditional Von Neumann architecture in which program and data are fetched from the same memory
using the same bus.
2. High performance RISC processors
■ C-Language friendly architecture
■ PIC16 source code compatible
■ Linear program memory addressing to 2 Mbyte
■ Linear data memory addressing up to 4 Kbytes
■ Up to 10 MIPS operation
■ 16-bit wide instructions, 8-bit wide data path
■ Priority levels for interrupts
■ 8 × 8 Single cycle hardware multiplier
3. Register file architecture: The register files/data memory can be directly or indirectly addressed. All
special function registers, including the program counter, are mapped in the data memory.
4. Instruction set simplicity
■ Reduced instruction set: The instruction set of PIC consists of only 77 instructions.
■ Orthogonal (symmetric) instructions: The instructions are orthogonal. It is possible to carry out any
operation on any register using any addressing mode when the instructions are orthogonal.
■ Single word instructions.
5. FLASH program memory: In sizes from 8 to 128 Kbytes
6. Data RAM: From 256 to 4 Kbytes
7. Built-in power-on-reset: PIC has a built-in power-on-reset.
8. Brown-out reset: PIC has a brown-out-reset. A brown-out-reset feature causes a reset of the PIC when
the power supply voltage drops below 4 V or so.
9. Watchdog Timer (WDT): Watchdog timer is a special timer with specific function. It is used to prevent
software crashes, i.e. endless loop.
10. Power saving SLEEP mode: The PIC can put itself to sleep to save power during intervals when it has
nothing to do. Thus, PIC supports a power saving SLEEP mode.
11. Flexible 8 and 16-bit timers
12. Interrupt Control: The PIC can control up to 12 independent interrupt sources.
13. 10-bit ADC (Analog to digital converter)
14. Capture/Compare/PWM (CCP) modules: Up to five (CCP) modules.
15. Powerful output pin control
16. Built-in serial peripheral interface
17. EPROM/OTP/ROM Options
18. Low power consumption
Functional Block Diagram of PIC18FXXX Series Microcontrollers
● Fig. 18.2.1 shows the simplified block diagram of PIC18 series microcontrollers.

Harvard architecture
• PIC18 uses Harvard architecture in which program and data are accessed from separate memories using
separate buses.
ALU
• The PIC18 contains 8-bit ALU. It is capable of performing arithmetic operations such as add, subtract,
multiply, shift and logical operations.
Multiplier 8 × 8:
• An 8 × 8 hardware multiplier is included in the ALU of the PIC18 devices.
• By making the multiply a hardware operation, it completes in a single instruction cycle. This is an
unsigned multiply that gives a 16-bit result. The result is stored in the 16-bit product register pair (PRODH:
PRODL).
Program ROM
• ROM is used to store programs and hence the name. It is also known as code ROM. For PIC18
microcontroller family the size of program RAM vary from 4 K are to 128 K depending on the family. In
PIC18 family microcontrollers, program ROM is available in different memory types:
• Flash memory
• OTP (One Time Programmable) memory
• Masked memory
• Flash memory uses letter F in the part number and it is used for product development.
• OTP (One Time Programmable) memory uses letter C in the part number and it is used for mass product
because it is cheaper than flash version.
• When the program is burnt into the PIC chip during the fabrication process of the chip, the chip is known
as masked PIC. It is the cheapest version of PIC.
Data RAM and EEPROM
• RAM space is used for data storage. For PIC18 microcontroller family the size of data RAM vary from
256 to 4096 bytes depending on the family.
• The data RAM space has two components:
■ General Purpose RAM (GPR) and
■ Special Function Registers (SFRs)
• The RAM GPR space is used for read/write scratch pad and data manipulation and is divided into
memory banks of 256 bytes of each. Thus the size of GPR for PIC18 family is always in multiples of 256
bytes.
• The SFRS are used by the CPU and peripheral modules for controlling the desired operation of the
device.
• The size of EEPROM on the chip vary with the family and it is used to store critical data that does not
frequent access.
Interrupt Sources
• PIC18 devices support multiple interrupt sources.
• Each interrupt can be assigned with low/high priority.
I/O Pins
• In PIC18 microcontroller family I/O pins vary from 16 to 72 depending on the family.
Capture/Compare/PWM (CCP) Module
• The CCP (Capture/Compare/PWM) module contains a 16-bit register that can operate as a 16-bit capture
register, as a 16-bit compare register or as a PWM duty cycle register.
Enhanced Capture/Compare/PWM (CCP) Module
• The operation of the ECCP module is identical to that of the CCP module. The ECCP module, on the
other hand, has Enhanced PWM functionality and auto-shutdown capability.
CAN Module
• The Controller Area Network (CAN) module is a serial interface, useful for communicating with other
peripherals or microcontroller devices.
• This interface/protocol was designed to allow communications within noisy environments.
ADC
ADC is 10-bit and the number of ADC channels in each chip varies from 5 to 16.
Timers
• PIC18 has 4/5 timers along with watch dog timer.
Master Synchronous Serial Port (MSSP) module
• The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with
other peripheral or microcontroller devices. It has two modes of operation :
• 3-wire SPI (Supports all 4 SPI modes)
• I2 C Master and Slave mode
Universal Synchronous Asynchronous Receiver Transmitter (USART) module
• The USART is a serial interface that can be configured in the following modes:
■ Asynchronous (full-duplex)
■ Synchronous - Master (half-duplex)
■ Synchronous - Slave (half-duplex)
PIC18F458/452 Pin Out Connection
● Fig. 18.4.1 shows the pin diagram of PIC18F458

● As shown in the Fig. 18.4.1, PIC18F458 has total 40 pins. These pins can be classified as :
■ Port pins : Out of 40 pins, 34 pins are dedicated to five ports A (RA0-RA6), B (RB0-RB7), C(RC0-
RC7), D (RD0-RD7) and E (RE0-RE2), with alternate functions.
■ Oscillator pins: OSC1 and OSC2. OSC2 and RA6 share the same pin.
■ Reset pin: MCLR (Master clear)
■ Programming voltage input: VPP
■ Power supply pins: Two VDD and Two VSS (GND).
● Table 18.4.1 shows PIC18F458 pins with description.
Registers of PIC18F
• The memory of the PIC is divided into a series of registers. Each of the registers has its own address and
memory locations.
• According to the type of working and usage, the registers in PIC are classified as :
■ Special Function Registers (SFRS): Used for control and status of the controller and peripheral
functions
■ General Purpose Registers (GPRS): Used for data storage and scratchpad operations in the user's
application.
■ WREG working register (acts as an Accumulator) - Used to perform arithmetic or logical functions.
■ Status register that stores flags - Indicates the status of the operation done by ALU.
■ Registers - hold memory address
• Bank Select Register (BSR): 4-bit register used in direct addressing the data memory.
• File Select Registers (FSRs).: 16-bit registers used as memory pointers in indirect addressing data
memory.
• Program Counter (PC): 21-bit register that holds the program memory address while executing
programs. This means that the PIC18 family can access program addresses 000000 to 1FFFFFH, a total of
2M bytes of code.
• Stack Pointer (SP): PIC18 has a 5-bit stack pointer. It is used to access the stack.

1. Working Register (WREG)

• It is 8-bits wide.
• It is used for ALU operations.
• The WREG register is the same as the accumulator in other microprocessors.
• The contents of WREG register are used for all arithmetic and logic one / two- operand instructions.
• It is not an addressable register.

2. PIC18 Status Register

• The status register is an 8-bit register. It is also referred to as flag register.
• The status register contains the arithmetic status of the ALU. It contains five flag bits Z, DC, C, OV and.
These bits are set or cleared according to the result of arithmetic or logical instructions.
• Remaining three bits: 5, 6, and 7 are unimplemented and read as 0.
• CLRF STATUS instruction clears the upper three bits and set the Z bit. This leaves the Status register as
000u uluu (where u = Unchanged).
• Only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the status register, because
these instructions do not affect the Z, C, DC, OV or N bits from the status register.

• Carry (C) flag: This flag is set if there is an overflow out of bit 7. The carry flag also serves as a borrow
flag for subtraction.
• Digital Carry (DC) flag: This flag is set if there is an overflow out of bit 3 i.e. carry from lower nibble to
higher nibble (bit 3 to bit 4). This flag is used for BCD operations and it is not, available for the
programmer. It is also known as Auxiliary Carry flag.
• Zero (Z) flag: The zero flag sets if the result of operation in ALU is zero and flag resets if result is non
zero. The zero flag is also set if a certain register content becomes zero following an increment or
decrement operation of that register.
• Over (OV) flag: This flag is set whenever the result of a signed number operation is too large, causing
the high-order bit to overflow into the sign bit.
• Negative (N) flag: After the execution of arithmetic or logical operations, if bit7 of the result is 1, the N
flag is set indicating result is negative. If bit7 is 0, the number will be considered as positive number.

3. Special Function Registers

• The Special Function Registers (SFRs) are registers used by the CPU and peripheral modules for
controlling the desired operation of the device. These registers are implemented as static RAM.
• Table 18.5.1 shows the list of SFRS. The SFRS are classified into two sets:
■ Registers associated with the core function and
■ Registers associated with peripheral functions.
• Here, we will discuss the registers related to the core functions, while those related to the peripheral
functions are discussed in the respective sections.
1. This is not a physical register.
2. These registers are not implemented on the PIC18F248 and PIC18F258. Table 18.5.1 Special Function
Register map for PIC18FXX8 family
Program and Data Memory Organization
1. The Program Counter in the PIC18
• A program counter is a register in a CPU that contains the address (location) of the instruction being
executed at the current time. After each instruction is fetched, the program counter is incremented to point
to the next instruction in the sequence.
• The PC can be accessed/modified by jump and branch instructions. Therefore, the destination address can
be loaded to the program counter via branch instructions.
• The width of the program counter decides how many memory locations CPU can access. More the width,
more the memory locations CPU can access.
• Table 18.6.1 shows the width of program counter in various PIC families and code memory access by
them.

• Fig. 18.6.1 shows the 21 bit program counter in PIC18 Family. The first location of. program memory in
PIC has the address of 00000H; however the last location can be different depending on the size of the
ROM on the chip.

• Program Counter (PC) - 21-bit register that holds the program memory address while executing
programs. This means that the PIC18 family can access program addresses 000000 to 1FFFFFH, a total of
2M bytes of code.

2. Programmable ROM Space in the PIC18 Family

Table 18.6.2 shows the code memory (ROM) size for various PIC18 family members.
• Fig. 18.6.2 shows program ROM space for PIC18F458 and PIC18F8722. As shown in Fig. 18.6.2, the
Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h.

• The PIC18F458 has 32 kbytes of flash program memory. This translates into 32768 single-word
instructions, which can be stored in the program memory.
• On the other hand, the PIC18F8722 has 128 kbytes of Flash program memory. This translates into
131072 single-word instructions, which can be stored in the program memory.
• Accessing a location between the physically implemented memory and the 2-Mbyte address will cause a
read of all '0's (a NOP instruction).
• For the PIC18, the internal data bus between the code ROM and CPU is 16 bit. Therefore, for
PIC18F458, 32 kbyte code memory is presented as 16K x 16 memory. As PIC18 family microcontrollers
access 16 bits from a memory at given time, all instructions of PIC18 are either 2 bytes or 4 bytes.

Addressing Modes
• Part of the programming flexibility is the different kind of ways the programmer can refer to data stored
in the memory. The different ways that can access data are referred to as addressing modes.
• The PIC 18 microcontroller supports following addressing modes :
1. Immediate addressing mode
2. Direct addressing mode
3. Register indirect addressing mode
4. Register Indirect/Indexed ROM addressing mode
1. Immediate addressing mode
• In immediate addressing mode, the immediate data is specified in the instruction. Immediate data is also
called literal in PIC18.
• The immediate addressing mode is used to load the data into PIC registers and WREG register. However,
we cannot use immediate addressing mode to load data into any of the file register.
• Examples:
1. MOVLW 0x50 ; Load 50 H into WREG
2. ANDLW D '18' ; Logically AND WREG with 18 decimal
3. ADDLW B' 01100000' ; Add 60 H in WREG
• The letter 'L' in the instruction means literal (immediate).
• To load immediate data in file register data RAM, we have to load immediate data in WREG register and
then it can be copied to file register data RAM location.
• We can use the EQU directive to access immediate data as shown below. NUM EQU 0x50
…
MOVLW NUM ; Load 50H in WREG
2. Direct addressing mode
In direct addressing mode, the operand data is in the file register (RAM) data memory. The address of this
memory location is specified in the instruction.
• Examples:
1. MOVWF 0X10 ; Copy contents of WREG into File Register RAM location 10 H
2. MOVFF 0X10, 0X20 ; Copy contents of location 10 H to 20 H dip elde
3. MOVFF 0X30, PORTC ; Copy contents of location 30 H to PORTC
• The letter 'F' in the instruction means the address of the file register location.
• The letter 'FF" in the instruction means the both source and destination addresses are file register
locations.
3. Register indirect addressing mode
• Register indirect addressing mode is used for accessing data stored in the file register (RAM) data
memory.
• In this addressing mode, three file select registers - FSRO, FSR1, and FSR2 are used as pointers to the
memory locations of the file register (RAM) data memory.
• Each of the FSRO, FSR1, and FSR2 registers has an INDF register associated with it, and these are called
INDFO, INDF1, and INDF2. When we move data into INDFX we are moving data into a RAM location
pointed to by the FSRX.
Examples:
1. LFSR 1, 0x55 ; Load FSR1 with 55H
MOVWF INDF1 ; copy contents of WREG into RAM location
; whose address is held by FSR1 register, i.e. 55H
2. LFSR 0, 0x40 ; Load FSR0 with 40H
MOVF INDFO,W ; Copy the contents of RAM location pointed by FSRO to WREG
4. Register Indirect/Indexed ROM addressing mode
• We use code space to store fixed data along with the code. This addressing mode is used for accessing the
fixed data from look up tables that reside in the PIC18 program ROM. This process is often called table
processing.
• Directive DB is used to define an 8-bit fixed data in data ROM. Here, we have to use special function
register to point the data to be fetched from the code space.
• Two registers are used in the table processing: TBLPTR (TaBLe PoinTR) and TABLAT (TABle
LATch). eisibemmi bol ol
• The 21 bit register TBLPTR is used to access byte from PIC18 program ROM. With 21 bit register
TBLPTR we can cover the entire 2M program (code) space for PIC18.
• TBLPTR register in divided into three parts: TBLPTRL (Low), TBLPTRH (High), and TBLPTRU
(Upper). These parts are of the SFRS.
• TABLAT register is used for keeping the byte read from code space pointed by TBLPTR.
• Example :
MOVLW 0x0 ; WREG = 10 Look-up Table low -byte address
MOVWF TBLPTRL ; Load Look-up Table low -byte address in TBLPTRL register
MOVLW 0x10 ; WREG = 10 Look-up Table high -byte address
MOVWF TBLPTRH ; Load Look-up Table high-byte address in TBLPTRH register
MOVLW 0x0 ; WREG = 0 Look-up Table upper-byte address
MOVWF TBLPTRU ; Load Look-up Table upper-byte address in TBLPTRH
; register
TBLRD* ; Read byte pointed by TBLPTR
MOVFF TABLAT, PORTB ; Send the read byte to PORTB
I/O Port Structure with Programming
• In the PIC18 family, the number of I/O ports supported by a particular microcontroller varies depending
on the family member and the number of I/O pins the device has.
• Table 18.13.1 shows Ports in PIC18 family members.

• The PIC18F458 has five I/O ports:

■ Port A (7 Bit): RAO - RA6
■ Port B (8 Bit): RBO - RB7
■ Port C (8-Bit): RC0 - RC7
■ Port D (8 Bit): RD0 - RD7
■ Port E (3 Bit): REO - RE2
• Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the
device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.
• Each port has three Special function registers (SFRs) associated with it:
■ TRIS register (Data Direction register)
■ PORT register (reads the levels on the pins of the device)
■ LAT register (output latch)
• The data latch (LAT register) is useful for read-modify write operations on the value that the I/O pins are
driving.
• Each of the Ports A-E in the PIC18F458 can be used for input or output. These ports are bi-directional.
The data direction register is TRISx (x stands for A - E) is used to set the direction either input or output.
• It is important to note that Data direction needs to be set before the I/O operation.
• Setting a TRISX bit (= 1) will make the corresponding PORTx pin an input (i.e., put the corresponding
output driver in a high-impedance mode).
• Clearing a TRISX bit (= 0) will make the corresponding PORTX pin an output (i.e., put the contents of
the output latch on the selected pin).
• Reading the PORTX register reads the status of the pins, whereas writing to it will write to the port latch.
• The Data Latch register (LATX) is also memory mapped. Read-modify-write operations on the LATX
register, read and write the latched output value for PORTX.

Example 18.13.1 Write an instruction sequence to output the hex value 0x35 to port B.
Solution: The Port B should be configured for output before data is written to it.
CLRF TRISB ; Configure Port B for output
MOVLW 0X35 ; WREG 35h
MOVWF PORTB ; Send 35h to Port B

Example 18.13.2 Write an instruction sequence to read the current value of port D into WREG.
Solution:
SETF TRISD ; Configure port D for input
MOVF PORTD, W ; Read data form port D and put it into WREG

Example 18.13.3 Configure the upper four pins of Port B for input and the lower four pins for output.
Solution :
MOVLW 0XF0 ; WREG = F0h
MOVWF TRISB ; Configure Port B upper as input and Port B lower as output

Example 18.13.4 Write a code to toggle all 8-bits of Port C forever with some time delay between ON and
OFF states.
Solution :
CLRF TRISC ; Configure Port C for output
BACK: MOVLW 0X55 ; WREG = 55h
MOVWF PORTC ; Send 55h to Port C
CALL DELAY ; Wait for some time
MOVLW 0XAA ; WREG = AAh
MOVWF PORTC. ; Send AAh to Port C
CALL DELAY ; Wait for some time
GOTO BACK ; Do forever

Example 18.13.5 Write a code to toggle all 8-bits of Port B forever with some time delay between ON and
OFF states using read-modify-write.
Solution:
CLRF TRISB ; Configure Port B for output
MOVLW 0X55 ; WREG = 55h
MOVWF PORTB ; Send 55h to Port B
BACK: COMF PORTB, F ; Complement bits of Port B
CALL DELAY ; Wait for some time
GOTO BACK ; Do forever
Note Upon reset, TRIS registers of all ports are loaded with value FFH, i.e. 11111111 2. As a result all
ports act as input ports upon reset.

1. Port A
• PORTA is a 7-bit wide (RAO-RA6), bidirectional port. The corresponding Data Direction register is
TRISA and Latch register is LATA.
Table 18.13.2 shows Port A alternate functions.
• The pins RA0, RA1, RA2, RA3, RA5 are multiplexed with analog inputs.
• The pins RA0, RA2 and RA3 are also multiplexed with the analog CVREF, VREF+ and VREF- inputs,
respectively.
• The RA4 pin is multiplexed with the Timero module clock input to become the RA4/TOCKI pin. The
RA4/TOCKI pin is a Schmitt Trigger input and an open-drain output.
• The RA5 pin is also multiplexed slave select input (SS) and low-voltage detect input (LVDIN)
• The RA6 pin is only enabled as a general I/O pin in ECIO and RCIO Oscillator modes.
• The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D
Control Register 1).
• All other RA port pins have TTL input levels and full CMOS output drivers.
• On a Power-on Reset, RA5 and RA3: RAO are configured as analog inputs and read as '0'. RA6 and RA4
are configured as digital inputs.

2. Port B
• PORTB is a 8-bit wide (RBO0-RB7), bidirectional port. The corresponding Data Direction register is
TRISB and Latch register is LATB.
• Read-modify-write operations on the LATB register, read and write the output value for PORTB.
Initializing Port B
CLRF PORTB ; Initialize PORTB by clearing output data latches
CLRF LATB ; Alternate method to clear output data latches

Example 18.13.6 Write an instruction sequence to set RB3:RB0 as outputs, RB5:RB4 as inputs and
RB7:RB6 as outputs.
Solution :
MOVLW 30h ; Value (00110000 in binary) used to initialize data direction
MOVWF TRISC ; Set RB3:RB0 as outputs, RB5:RB4 as inputs and RB7:RB6 as outputs.
• Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups.
This is performed by clearing bit (INTCON2 register). The weak pull-up is automatically turned
off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
• Table 18.13.3 shows Port B alternate functions.

• The pins RB0, RB1 and RB2 are multiplexed with the external interrupt pins INTO, INT1 and INT2,
respectively.
• The pin RB2 is also multiplexed with Transmit signal for CAN bus.
• The pin RB3 is multiplexed with Receive signal for CAN bus.
• Four of the PORTB pins (RB7: RB4) have an interrupt on-change feature. This "interrupt on change" is
triggered when any of the RB7: RB4 pins, configured as an input, changes level.
• The input pins (of RB7: RB4) are compared with the old value latched on the last read of PORTB. The
"mismatch" outputs of RB7 : RB4 are ORed together to generate the RB Port Change Interrupt with Flag
bit RBIF (INTCON register). This interrupt can wake the device from Sleep.

3. Port C
• PORTC is an 8-bit wide, bidirectional port.
• The corresponding Data Direction register is TRISC and Latch register is LATC.
• Read-modify-write operations on the LATC register, read and write the latched output value for PORTC.
• Table 18.13.4 shows Port C alternate functions.
• PORTC uses Schmitt Trigger input buffers
Initializing Port C
CLRF PORTC ; Initialize PORTC by clearing output data latches
CLRF LATC ; Alternate method to clear output data latches

Example 18.13.7 Write an instruction sequence to set RC3: RCO as inputs RC5: RC4 as outputs RC7:
RC6 as inputs.
Solution:
MOVLW 0CFh ; Value (11001111 in binary) used to initialize data direction
MOVWF TRISC ; Set RC3:RCO as inputs, RC5:RC4 as outputs and RC7:RC6 as inputs

4. Port D
• PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD and
Latch register is LATD.
• Read-modify-write operations on the LATD register, read and write the latched output value for PORTD.
• Table 18.13.5 shows Port D alternate functions.
PORTD uses Schmitt Trigger input buffers.
Initializing Port D
CLRF PORTD ; Initialize PORTD by clearing output data latches
CLRF LATD ; Alternate method to clear output data latches
MOVLW 07h ; Comparator off
MOVWF CMCON ; Comparator Control Register bits (CM2:CM0) 111 to make them off.

Example 18.13.8 Write an instruction sequence to set RD3: RD0 as inputs and RD7 : RD4 as outputs.
Solution:
MOVLW 0Fh ; Value (00001111 in binary) used to initialize data direction
MOVWF TRISD ; Set RD3: RDO as inputs and RD7: RD4 as outputs.

5. Port E
• PORTD is an 3-bit wide, bidirectional port. The corresponding Data Direction register is TRISE and
Latch register is LATE.
• Read-modify-write operations on the LATE register, read and write the latched output value for PORTE.
• Table 18.13.6 shows Port E alternate functions.
• PORTE uses Schmitt Trigger input buffers.
Initialize PORT D
CLRF PORTE ; Initialize PORTE by clearing output data latches
CLRF LATE ; Alternate method to clear output data latches

Example 18.13.9 Write an instruction sequence to set RE1: REO as inputs and RE2 as output.
Solution :
MOVLW 03h ; Value (00000011 in binary) used to initialize data direction
MOVWF TRISE ; Set RE1 : RE0 as inputs and RE2 as output.
• The TRISE register also controls the operation of the Parallel Slave Port through the control bits in the
upper half of the register, as shown in the Fig. 18.13.2.

bit 7 IBF : Input Buffer Full status bit

1 = A word has been received and waiting to be read by the CPU
0 = No word has been received
TECHNICAL PUBLICATIONS an up-thrust for knowledge
TRISEO
bit 0
bit 6 OBF : Input Buffer Full status bit
1 = The output buffer still holds a previously written word
0 = The output buffer has been read
bit 5 IBOV : Input Buffer Overflow Detect bit (in Microprocessor mode)
1 = A write occurred when a previously input word has not been read
(must be cleared in software)
0 = No overflow occurred
bit 4 PSPMODE : Parallel Slave Port Mode Select bit
1 = Parallel Slave Port mode
0 = General Purpose I/O mode
bit 3 Uniplemented : Read as '0'
bit 2 TRISE2 : RE2 Direction Control bit
1 = Input
0 = Output
bit 1 TRISE1: RE1 Direction Control bit
1 = Input
0 = Output
bit 0 TRISE0 : RE0 Direction Control bit
1 = Input
0 = Output
Fig. 18.13.2 Bit pattern of TRISE register
• When the Parallel Slave Port is active, the PORTE pins function as its control inputs.

6. I/O Bit Manipulation Programming

• Many times it is necessary to access only 1 or 2 bits of the port instead of all 8-bits.
• The PIC18 I/O ports allow to access individual bits of the ports without altering the rest of the bits in that
port.
• Table 18.13.7 gives the single bit instructions for the PIC18.

• Bit operations allow us to move, set and clear single bits in registers or numbers that we specify.
BCF
• This instruction will clear a bit that we specify in a given File register. The syntax is:
BCF <register>, <bit_num>
• Example :
BCF TRISC, 0 ; Clear bit 0 of TRISC register
BSF
• This instruction will set a bit that we specify in a given File register. The syntax is : BSF <register>,
<bit_num>
• Example:
BSF PORTA, 4 ; Set bit 4 of Port A
BTFSC
• This instruction will test the bit that we specify in a given File register. If the bit is a 0, the instruction will
tell the PIC to skip the next instruction. The syntax is : <register>, <bit_num>
• Example 1 :
BTFSC PORTB, 2; Check bit 2 of Port B, if it is zero code skips next instruction
• Example 2:
LOOP : BTFSC PORTA, 3 ; Monitor PA3 ; repeats instructions in the LOOP until PA3 is 0.
BRA LOOP
BTFSS
• This instruction will test the bit that we specify in a given File register. If the bit is a 1, the instruction will
tell the PIC to skip the next instruction. The syntax is : BTFSS <register>, <bit_num>
• Example 1 :
BTFSS PORTC, 5; Check bit 5 of Port C, if it is 1 code skips next instruction
• Example 2:
LOOP : BTFSS PORTB, 3 ; Monitor PB3; repeat instructions in the LOOP until PB3 is 1.
BRA LOOP
BTG
• This instruction will toggles a bit that we specify in a given File register. The syntax is:
BTG <register>, <bit_num>
• Example: Code segment to generate square wave on pin PC2
BCF TRISC, 2 ; Clear bit 2 of TRISC register to make RC2 an output pin
BACK: BTG PORTC, 2 ; Toggle PC2
CALL DELAY ; Wait for some time
BRA BACK ; Repeat forever

7. Programming Examples
Example 18.13.10 Write the following programs. Create a square wave of 50% duty cycle on bit 0 of
PORTA.
Solution: The 50% duty cycle means that T ON = TOFF. Therefore, we toggle RA0 with a time delay in
between each state.
Program 1 : Using BCF and BSF instructions
BCF TRISA, 0 ; Clear bit 0 of TRISA register to make RA0 an output pin
AGAIN : BSF PORTA, 0 ; Set bit 0 of Port A
CALL DELAY ; Wait for Some time
BCF PORTA, 0 ; Clear bit 0 of Port A
CALL DELAY ; Wait for Some time
BRA AGAIN ; Repeat forever
Program 2 : Using BTG instruction
BCF TRISA, 0 ; Clear bit 0 of TRISA register to make RAO an output pin
AGAIN: BTG PORTA, 0 ; Toggle bit 0 of Port A
CALL DELAY ; Wait for Some time
BRA AGAIN ; Repeat forever

Example 18.13.11 Write the following programs. Create a square wave of 66% duty cycle on bit 2 of
PORTC.
Solution: The 66% duty cycle means that 2TON = TOFF
BCF TRISC, 2 ; Clear bit 2 of TRISC register to make RC2 an output pin
AGAIN : BSF PORTC, 2 ; Set bit 2 of Port C
CALL DELAY ; Wait for some time twice for 66%
CALL DELAY
BCF PORTC, 2 ; Clear bit 2 of Port C
CALL DELAY ; Wait for Some time
BRA AGAIN ; Repeat forever

Example 18.13.12 Write a program to perform the following :

(a) Keep monitoring the RC3 bit until it becomes high
(b) When RC3 becomes high, write value-34H to Port B
(c) Send a high-to-low (H-to-L) 'pulse to RD2
Solution :
BSF TRISC, 3 ; Set bit 3 of TRISC register to make RC3 an input pin
CLRF TRISB ; Make Port B an output port
BCF TRISD, 2 ; Clear bit 2 of TRISD register to make RD2 an output pin ;
MOVLW 0x34 ; WREG = 34H
AGAIN: BTFSS PORTC, 3 ; Test RC3, if RC3 = 1, skip next instruction
BRA AGAIN ; Repeat if RC3 = 0
MOVWF PORTB ; Send contents of WREG (34H) to Port B
BSF PORTD, 2 ; Set bit 2 of Port D
BCF PORTD, ; Clear bit 2 of Port D
Example 18.13.13 Assume that bit RC3 is an input and represents the condition of an oven. If it goes low,
it means that the food is ready. Monitor the bit RC3 continuously. Whenever it goes low, send a high-to-
low pulse to port PB5 turn on a buzzer.
Solution :
BSF TRISC, 3 ; Set bit 3 of TRISC register to make RC3 an input pin
BCF TRISB, 5 ; Clear bit 5 of TRISB register to make RB5 an output pin
AGAIN: BTFSC PORTC, 3 ; Test RC3, if RC3 = 0, skip next instruction
BRA AGAIN ; Repeat if RC3 = 1
BSF PORTB, 2 ; Set bit 2 of Port B
BCF PORTB, 2 ; Clear bit 2 of Port B
BRA AGAIN ; Repeat forever

Example 18.13.14 Assume that switch (SW) is connected to pin RB1. Write a program to check the status
of SW and perform the following :
(a) If SW-0, send character 'N' to PORTC
(b) If SW=1, send character 'Y' to PORTC
Solution :
BSF TRISB, 1 ; Set bit 1 of TRISB register to make RB1 an input pin
CLRF TRISC ; Make Port C an output port
AGAIN: BTFSC PORTB, 1 ; Test RB1, if RB1 = 0, skip next instruction
BRA NEXT ; if RB1 = 1, go to NEXT
MOVLW A 'N' ; Load ASCII of character N in WREG
MOVWF PORTC ; Send it to Port C
BRA AGAIN ; Repeat forever
NEXT : MOVLW A 'Y' ; Load ASCII of character Y in WREG
MOVWF PORTC ; Send it to Port C
BRA AGAIN ; Repeat forever

Example 18.13.15 Assume that a switch (SW) is connected to pin RA3 and an LED to pin RB6. Write a
program to get the status of the SW and send it to the LED.
Solution:
BSF TRISA, 3 ; Set bit 3 of TRISA register to make RA3 an input pin
BCF TRISB, 6 ; Clear bit 6 of TRISB register to make RB6 an output pin
AGAIN: BTFSS PORTA, 3 ; Test RA3, if RA3 = 1, skip next instruction
BRA NEXT ; if RA3 = 0, go to NEXT
BSF PORTB, 6 ; Set RB6 to make LED ON
BRA AGAIN ; Repeat forever
NEXT: BCF PORTB, 6 ; Clear RB6 to make LED OFF
BRA AGAIN ; Repeat forever

8. Input Pin Vs. LATx Port

• Writing to PORTX or LATx has the same effect, but reading PORTX register read the corresponding
input pin. Reading LATx, reads the status of the corresponding internal port latch and not the status of the
pin.
• Some instructions read the contents of an internal port latch instead of reading the status of an extern pin.
• When such instructions are executed following sequence of actions take place –
1. The instruction read the internal latch of the LATX and brings that data into the CPU.
2. The data is processed as per instruction.
3. The result of the operation is rewritten back to the LATx latch.
4. The data on the pins are changed only if the port bits are configured as an output pins i.e. TRISx bits are
cleared to 0.
• For example, COMF PORTC instruction will read PORTC, complement all the data bits, then write the
result back to PORTC.

1. Registers used for Timer/Counter Operation

• PIC18 has two to five timers depending on the PIC family it belongs to. They are Timer 0, 1, 3, 4 and 5.
PIC18F458 has four timers: Timer 0, Timer 1, Timer 2, and Timer 3.
• They can be used either as timers to generate time delays or as counters to count events.
• In PIC18F458, timers 0, 1 and 3 are 16-bit timers while timer 2 is 8-bit timer. These timers can be used as
timer, counters or for PWM generation.

• Selecting clock source clock source can be internal or external and is controlled by bit TxCS:
■ D TxCS = 0: Clock source is internal and is taken from Fosc/4.
■ TxCS = 1: Clock source is external and is taken from TxCKI pin; in this case TXSE controls the edge of
the signal which triggers increment.
■ Note: x can be 0, 1, 2 or 4.
2. Prescaling of PIC18 Timers
• In some cases, the clock coming from the oscillator could be too fast for an application. We can lower it
by using the frequency prescaler.
• Timer 0 : The prescaler circuit divides the signal frequency by prescale values of 1:2, 1: 4, ..., 1: 256
according to the status of TOPS2: TOPSO: Timero Prescaler Select bits. The prescaler is activated by bit
PSA:
■ PSA = 0 Prescaler is selected.
■ PSA 1 = Prescaler is not selected.
• Timer 1: The prescaler circuit divides the signal frequency by prescale values of 1:1, 1:2, 1: 4, 1:8
according to the status of T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits.
• Timer 2: The prescaler circuit divides the signal frequency by prescale values of 11, 14, 1: 16 according
to the status of T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits.
• Timer 3: The prescaler circuit divides the signal frequency by prescale values of 1:1, 1:2, 1:4, 1: 8
according to the status of T3CKPS1:T3CKPS0: Timer3 Input. Clock Prescale Select bits.

3. Timer 0
a. Features
• The features of Timer 0 are:
1. Software selectable as an 8-bit or 16-bit timer/counter.
2. Readable and writable
3. Dedicated 8-bit software programmable prescaler
4. Clock source selectable to be external or internal
5. Interrupt-on-overflow from FFh to 00h in 8-bit mode and FFFFh to 0000h in 16-bit mode MCALAT
6. Edge select for external clock
b. T0CON: Timer0 Control Register
• Fig. 18.14.1 shows the Timer0 Control register (T0CON). It is an 8-bit, read/write register used to that
controls all the aspects of Timer0 including: enable/disable timer0, select the operating mode, select the
clock source and its transition (HIGH to LOW or LOW to HIGH), enable/disable prescaler and to select the
prescaler value if enabled.
c. Block Diagram
• Fig. 18.14.2 shows the simplified block diagram of Timer 0 in 8-bit mode.
• Upon Reset, Timer0 is enabled in 8-bit mode with clock input from TOCKI maximum prescale.
• Timer0 can operate as a timer or as a counter. Timer mode is selected by clearing the T0CS bit.

• In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler).
• Counter mode is selected by setting the T0CS bit. In Counter mode, Timer0 will increment either on
every rising or falling edge of pin RA4/T0CKI.
• The incrementing edge is determined by the Timer0 Source Edge Select bit (T0SE). Clearing the TOSE
bit selects the rising edge.
• The prescaler circuit divides the signal frequency by prescale values of 1:2, 1:4, ..., 1:256 according to the
status of TOPS2:TOPSO: Timer0 Prescaler Select bits. The prescaler is activated by bit PSA :
• PSA = 0: Prescaler is selected.
• PSA 1 Prescaler is not selected.
• An overflow occurs when a timer register (TMROL) has already counted the maximum value it can count
(255). At overflow the counter value become 0 again. An overflow triggers an interrupt and set TMR0IF
flag bit.
• Fig. 18.14.3 shows the simplified block diagram of Timer 0 in 16-bit mode.
• Timer0 can be set in 16-bit mode by clearing the T08BIT in T0CON.
• In this mode, registers TMR0H and TMR0L are used to access the 16-bit timer value.
• In this mode, TMR0IF flag bit is set when 16-bit timer value overflows from FFFFh to 0000.
• Here, TMROH is not the high byte of the timer/counter in 16-bit mode, but is actually a buffered version
of the high byte of Timer0. This is illustrated in Fig. 18.14.2.
d. Applications
• Applications of Timer0 are:
■ Generate wide range of accurate time delays by selecting the appropriate prescaler options.
■ Measure frequency of an unknown signal. det bra sal

4. Timer 1
a. Features
• The features of Timer 1 are :
1. 16-bit timer/counter
2. Two 8-bit registers: TMR1H and TMR1
3. Readable and writable (both registers)
4. Internal or external clock select
5. Interrupt-on-overflow from FFFFh to 0000h
6. Reset from CCP module special event trigger
7. Can not be disabled by SLEEP instruction
b. T1CON: Timer1 Control Register
• Fig. 18.14.4 shows the Timer1 Control register (T1CON). It is an 8-bit, read/write register used to that
controls all the aspects of Timer1.
c. Block Diagram
Fig. 18.14.5 shows the simplified block diagram of Timer 1.

• Timer1 can be enabled/disabled by setting/clearing control bit, TMR1ON (T1CON register).

• The operating mode for the Timer1 is determined by the clock select bit, TMRICS (T1CON register).
Timer1 can operate in one of these modes :
■ As a timer
■ As a synchronous counter
■ As an asynchronous counter
• When TMR1CS=0: Timer1 increments every instruction cycle.
• When TMR1CS = 1: Timer1 increments on every rising edge of the external clock input or the Timer1
oscillator, if enabled.
• When the Timer1 oscillator is enabled (T1OSCEN is set), the T1OSI and T1OSO/T1CKI pins become
inputs. This oscillator is a low power oscillator and it is utilized in the sleep mode. In the sleep mode, the
Timer1 is not disabled and hence it can be used to implement the-chip real time clock (RTC).
• Timer1 also has an internal "Reset input". This Reset can be generated by the CCP module.
• The prescaler circuit divides the signal frequency by prescale values of 1:1, 1:2, 1:4, 1:8 according to the
status of T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits.
• Here, TMR1IF flag bit is set when 16-bit timer value in TMR1 register pair (TMR1H:TMR1L)
increments from 0000h to FFFFh and rolls over to 0000h.
d. Applications
• Applications of Timer1 are :
■ Generate accurate time delays by selecting the appropriate prescaler options.
■ Measure frequency of an unknown signal.
■ Implement Real Time Clock (RTC)
■ Generate special event trigger in compare mode of CCP module.

5. Timer 2
a. Features
• The features of Timer 2 are:
1. 8-bit timer (TMR2 register)
2. 8-bit period register (PR2)
3. Readable and writable (both registers)
4. Software programmable prescaler (1: 1, 1:4, 1:16)
5. Software programmable postscaler (1 : 1 to 1 : 16)
6. Interrupt on TMR2 match of PR2
7. SSP module optional use of TMR2 output to generate clock shift
b. T2CON: Timer2 Control Register
• Fig. 18.14.6 shows the Timer1 Control register (T2CON). It is an 8-bit, read/write register used to that
controls all the aspects of Timer2.
• Timer2 can be shut-off by clearing control bit TMR2ON (T2CON register) to minimize power
consumption.
c. Block Diagram
• Fig. 18.14.7 shows the simplified block diagram of Timer 2.

• Timer2 is disabled on power-on-reset.

• It consists of two 8-bit, readable/writable registers: TMR2 and PR2, comparator, and prescaler and
postscaler circuits.
• The clock source for TMR2 is Fosc/4 for both prescaler and Postscaler options. There is no external clock
source for Timer2 and hence can't be used as a counter.
• The prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON register).
• The 4-bit postscaler gives a 1:1 to 1:16 scaling options to generate a TMR2 interrupt.
• TMR2 register increments from 00 to the value equal to PR2. Comparator compares values from TMR2
and PR2 registers. When these values are equal, TMR2IF flag is set in PIR1 register and TMR2 reset to 00.
• Timer2 can be used as the PWM time base for the PWM mode of the CCP module.
• The prescaler and postscaler counters are cleared when any of the following Occurs:
1. A write to the TMR2 register
2. A write to the T2CON register
3. Any device Reset (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset)
• TMR2 is not cleared when T2CON is written.
d. Applications
• Applications of Timer 2 are:
1. Generate accurate time delays by selecting the appropriate prescaler options.
2. Acts as an input for SSP module to generate clock shift.
3. Used as PWM time base for the PWM mode of the CCP module.
4. Generate periodic interrupts.

6. Timer 3
a. Features
The features of Timer 3 are:
1. 16-bit timer/counter TUOT
2. Two 8-bit registers: TMR3H and TMR3L)
3. Readable and writable (both registers)
4. Internal or external clock select
5. Interrupt-on-overflow from FFFFh to 0000h
6. Reset from CCP1/ECCP1 module trigger
b. T3CON: Timer3 Control Register
• Fig. 18.14.8 shows the Timer3 Control register (T3CON). It is an 8-bit, read/write register used to that
controls all the aspects of Timer3.

bit 7 RD16 : 16-bit Read/Write Mode Enable bit

1 = Enables register read/write of Timer3 in one 16-bit operation
0 = Enables register read/write of Timer3 in two 8-bit operation
bit 6,3 T3ECCP1: T3CCP1 : Timer3 and Timer1 to CCP1/ECCP1 Enable bits
1x = Timer3 is the clock source for compare/capture CCP1 and ECCP1 modules
01 = Timer3 is the clock source for compare/capture of ECCP1
Timer1 is the clock source for compare/capture of CCP1
00= Timer1 is the clock source for compare/capture of CCP1 and ECCP1 modules
bit 5-4 T3CKPS1 : T3CKPS0: Timer3 Input Clock Prescale Select bits
11= 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1: 2 Prescale value
00 = 1:1 Prescale value
c. Block Diagram
• Fig. 18.14.9 shows the simplified block diagram of Timer3.

• Timer3 can be enabled/ disabled by setting/clearing control bit, TMR3ON (T3CON register).
• The operating mode for the Timer3 is determined by the clock select bit, TMR3CS (T3CON register).
Timer3 can operate in one of these modes:
■ As a timer
■ As a synchronous counter
■ As an asynchronous counter
• When TMR3CS = 0, Timer3 increments every instruction cycle.
• When TMR3CS = 1, Timer3 increments on every rising edge of the Timer1 external clock input or the
Timer1 oscillator, if enabled.
• The Timer1 oscillator may be used as the clock source for Timer3. When the Timer1 oscillator is enabled
(T1OSCEN is set), the T1OSI and T1OSO/T1CKI pins become inputs.
• Timer3 also has an internal "Reset input". This Reset can be generated by the CCP module.
• The prescaler circuit divides the signal frequency by prescale values of 1:1, 1: 2, 1: 4, 18 according to the
status of T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits.
• Here, TMR3IF flag bit is set when 16-bit timer value in TMR3 register pair (TMR3H:TMR3L)
increments from 0000h to FFFFh and rolls over to 0000h.
d. Applications
• Applications of Timer 3 are:
■ Generate accurate time delays by selecting the appropriate prescaler options.
■ Measure frequency of an unknown signal.
■ Implement Real Time Clock (RTC)
■ Generate special event trigger in compare mode of CCP module.

7. Delay Calculations
• Let's take an example. Suppose we have to generate a delay of 1 ms having 10 MHZ oscillator frequency
of PIC18F458.
Calculate timer input frequency
Given: FOSC = 10 MHz. Let us take prescaler = 1 : 4
FTIMER = FOSC / 4 × Prescaler ratio
= 10 / 4 × 1 / 4 = 625 kHz
Find the period which will be taken by the timer to increment the count
Period = 1 / FTIMER = 1/ 625 kHz = 1.6 μs
• Therefore, after each 1.6 μs, the timer value will be incremented by 1.
Find the count needed for a delay of 1 ms
Count = 1 ms / 1.6μs = 625
• Since this count is greater than 256 we need use 16 bit timer.
Calculate value to be loaded in Timer register for a delay of 1 ms
• The value to be loaded in 16-bit Timer register is calculated as: 65536- Count = 65536 625 = 64911 =
FD8FH
• Load this hex value in the 16-bit timer register to produce desired delay.
Using 8-bit Timer
• By selecting larger prescaler ratio we can generate same delay with 8-bit counter. Let us select prescaler 1
: 64.
FTIMER = FOSC / 4 × Prescaler ratio
= 10 / 4 × 1 / 64 = 39.0625 kHz
Find the period which will be taken by the timer to increment the count
Period = FTIMER = 1 / 39.0625 kHz = 25.6 µs
• Therefore, after each 25.6, us the timer value will be incremented by 1.
Find the count needed for a delay of 1 ms
Count = Desired Delay / Timer Period = 1 ms / 25.6μs
= 39.0625≈ 39
• Since this count is less than 256 we need use 8- bit timer.
• The value to be loaded in 8-bit Timer register is calculated as: 256 - Count 256 - 39 = 217 D9H
• Load this hex value in the 8-bit timer register to produce desired delay.
PIC Programming Techniques
Program Using W Register and Literal Values
MOVLW 15H ; Load 15H into W register
ADDLW 20H ; Add 20H to W register (W = W + 20H = 35H)
ADDLW 36H ; Add 35H to W register (W = W + 35H = 70H)
ADDLW 05H ; Add 05H to W register (W = W + 05H = 75H = 15H + 20H + 35H + 05H)
Accessing locations in the file register (General Purpose Register or SFR)
MOVLW 95H ; Load 95H into W register
MOVWF 10H ; Copy W register contents to location 10H
MOVWF PORTA ; Copy W register contents to Port A
MOVF PORTB, W; Copy data from Port C to W register
MOVF 20H, W ; Copy data from location 20H to W register
Copy data from one location in file register to another location in file register
MOVFF 20H, PORTB ; Copy data from location 20H to Port B
Arithmetic Operation on data from file register location and Saving Result in W register
MOVLW 15H ; Load 15H into W register
ADDWF 5H ; Add contents of location 5H and W register, store result in W register.
; If contents of location 5H = 34H, After execution: W = 15H + 34H = 49H
Arithmetic Operation on data from file register location and Saving Result in W register
MOVLW 15H ; Load 15H into W register
ADDWF 5H, 0 ; Add contents of location 5H and W register, store result in W register.
; If contents of location 5H = 34H, After execution: W = 15H + 34H 49H
Arithmetic Operation on data from file register location and Saving Result in file register location
MOVLW 15H ; Load 15H into W register
ADDWF 5H, 1 ; Add contents of location 5H and W register, store result in location 5H.
; If contents of location 5H = 34H,
; After execution : Location 05 = 15H + 34H = 49H
Sample PIC Assembly Language Program

Arithmetic Operation with Conditional Branch Instruction

Let us add two 8-bit numbers and save 16-bit result in two file register locations
L_Byte EQU 10H ; Assign RAM location 10H to store L_Byte of Sum
H_Byte EQU 11H ; Assign RAM location 11H to store H_Byte of Sum
ORG 0 ; Start at address 0
MOVLW 0 ; W register = 0
MOVWF H_Byte ; H_Byte = 0
MOVLW 85H ; Load first number in W register
ADDLW A5F ; Add second number, W = 85H + A5H 2AH, C = 1
BNC SKIP ; If C = 0, skip the next instruction
INCF H_Byte, F ; If C = 1, increment H_Byte, i.e., H_Byte
SKIP MOVWF L_Byte ; L_Byte = 2AH
END
Looping in PIC
Let us see PIC18 program to add value 5 to W register ten times.
COUNT EQU 20H ; Reserve location 20H for counter
SUM EQU 10H ;Reserve location 10H for sum
MOVLW D ‘10' ; Load value decimal 10 in W register for counter
MOVWF COUNT ; Initialize the Counter with value 10
MOVLW 0 ; Sum = 0
BACK ADDLW 5 ; W = W +5
DECF COUNT, F; Decrement counter and skip next instruction if count = 0
GOTO BACK ; if count ≠ 0, repeat previous two instructions
MOVWF SUM ; Save the sum at location 10H
Using conditional branch instruction
Let us see the same program using conditional branch instruction
COUNT EQU 20H ; Reserve location 20H for counter
SUM EQU 10H ; Reserve location 10H for sum
MOVLW D '10' ; Load value decimal 10 in W register for counter
MOVWF COUNT ; Initialize the Counter with value 10
MOVLW 0 ; Sum = 0
BACK ADDLW 5 ; W = W + 5
DECF COUNT, F; Decrement counter
BNZ BACK ; if count ≠ 0, repeat previous two instructions
MOVWF SUM ; Save the sum at location 10H
Using Look-up Tables
The following program will send the ASCII value based on the value in W register to Port C. For example,
if W = 0000 0010, program will send ASCII for 2, i.e., '2' to Port C. It is assumed that W register contents
value between 0 - 9 (decimal).
ORG 0 ; Start at address 0
MOVLW D `5' ; W register = decimal 5
CALL ASCII_TABLE ; Get ASCII value from Look-up Table
MOVWF PORTC ; Send ASCII value to Port C
ASCII_TABLE
MULLW 0x2 ; Multiply contents of W by 2 to align offset for even address
MOVF PRODL, W ; Put the offset in W register for indexing
ADDWF PCL ; PCL = PCL + W (offset) so that PC will access
; corresponding RETLW instruction
RETLW `0' ; Return ASCII for 0
RETLW 1' ; Return ASCII for 1
RETLW 2' ; Return ASCII for 2
RETLW 3' ; Return ASCII for 3
RETLW '4' ; Return ASCII for 4
RETLW '5' ; Return ASCII for 5
RETLW `6' ; Return ASCII for 6
RETLW '7' ; Return ASCII for 7
RETLW `8' ; Return ASCII for 8
RETLW '9' END ; Return ASCII for 9
END
Note: In the program memory, Look-up Table contains the opcode for RETLW instruction, followed by
ASCII code consuming 2 bytes for each RETLW instruction. Thus to obtain the right offset, we must
multiply the contents of the W register by 2. ADDWF PCL instruction allows PC to access the correct
RETLW instruction and once executed it returns the corresponding ASCII code.