Ajay Kashyap Mobile: +91 98868 06294

ajay.kashyap@gmail.com

Profile
Physical design implementation and signoff expert. Lead multiple projects as physical design lead and
delivered from RTL to Fab.

Hands on PDN convergence and signoff expert, work across multiple companies and projects. None of
the project had any silicon finding for PDN issues.

Managed teams of 10-20 engineers as a people manager. Responsible for team deliverables planning
and execution, individual mentoring, communication and alignment and team growth. Also sponsored
multiple contingent workers.

Education
Indian Institute of Technology (IIT Delhi), Delhi, 2002 – 2004

Degree: M.Tech., Computer Technology

CGPA: 8.57 / 10.0 (3rd Rank/22)

M B M Engineering College, Jodhpur, 1998 - 2002

Degree: B.E, Computer Science and Engineering

Aggregate: 67.7% (5th Rank/35)

Professional Experience
Senior Manager/Soc Design Lead, Intel Technologies Bangalore (Aug 2018 – present)

• Lead physical design for multiple subsystems for TSMC N5 and Intel 5nm technology node.
Significantly improved the execution efficiency, reduced power, and delivered the subsystems
much earlier than committed timelines
• PDN domain signoff and convergence owner. Lead multiple project PDN convergence across
client, server, graphics and IOTG groups on different TSMC and intel technology nodes
• Developed methodology for multi gated design PDN convergence using modular block header
switches.
• Worked on IR aware placement and PG augmentation for IR/RV fixing methodologies.
• Worked on IR fixing using Dynamic clock scheduling.
• Developed multiple topological checks within ICC to prevent the IR EM related issues later in
signoff convergence cycle.

Senior Staff Engineer/Manager, Qualcomm Inc Bangalore (Oct 2016 – Aug2018)

• Design Project TFM manager for PnR and Signoff for 7FF designs
 • Supported multiple project technology readiness across implementation and signoff vectors as
CAD owner.
• IREM methodology owner for BDC design projects, Supporting multiple nodes 7FF, 8LPE, 10LPE,
11LPE, 14LPP, 14CVRF and 28nm
• Responsible for defining signoff criteria for different technology nodes
• Tool/flow readiness and enablement for different nodes
• Driving different methodology project especially DVD prevention and fixing.

Member Technical Staff, Infineon Technologies Bangalore (Dec 2012 – Oct 2016)

• IREM methodology owner and IREM design signoff champion for Asia pacific design projects.
• Responsible for defining IREM signoff criteria for different technology nodes
• Responsible for design signoff for different design projects (ATM microcontrollers, ASIC designs)
• Chip package co-analysis and roll-out

Member Technical Staff, Advanced Micro Devices, Bangalore, (Aug 2007 - Nov 2012)

• Technical lead for CPU/GPU analysis flows (Signal EM, LocalHeating, IR, timing, noise) in India
design center
• Developed gate level clock domain crossing tool for 32nm, 40nm and 28nm fusion SoC projects.
This effort was well recognized by design and the EDA/CAD team.
• Developed and deployed sub-chip Level IR flow using Apache Redhawk and bench marked it
with fullchip SOC runs.
• CAD methodology owner for standard cell library qualification flow. Developed infrastructure
and library checklist management system for validating standard cell library releases.
• Co-architect subchip/IP packaging and release mechanism. Implemented the whole system and
owning the entire flow. Support for processor design flow on different processor design.

Senior Design Engineer, Texas Instruments (India) Pvt, Ltd, Bangalore, June 2004 - August 2007.

• Worked on designing, developing, and maintaining the software infrastructure needs of ASIC
Group
• Worked with team having Characterization and Modelling ownership of all IP’s including IO and
CORE cells (90nm, 65nm and 45nm)
• Automation of cell cerate flow (more than 4000 cells needs to be characterized on different
parameters (CIN, Timing, Power, Constraints, DC, Reliability-parameter))
• Developed IBIS Model generation flow
• Developed IO Compiler (IO selection Tool for CO14 (45nm) PPPAS Goals)

Paper Presentation
• Title: New Method of implementing Nth level of Power Gating with Modular Power Gates
Forum: DTDC 2021 and Design Automation Conference 2021, San Francisco
• Title: Novel approach for Static and Dynamic IR aware Implementation
Forum: DTDC 2021 and Design Automation Conference 2021, San Francisco
• Title: Developing Safe and Reliable Automotive Electronics System
Forum: Design Automation Conference 2015, San Francisco
 • Title: Analyze and study the impacts of different packages on static and dynamic IR Drop analysis
on different Infineon designs
Forum: “International Journal on Recent and Innovation Trends in Computing and
Communication (IJRITCC)", 2015
• Title: Inrush Current Analysis for Voltage drop simulation across GDHS/BHS
Forum: Qualcomm Qbuzz, 2017
• Title: Power Reduction Methodologies for Energy Efficient Soc’s
Forum: Infineon iTech Days 2015,
• Title: A contention free 802.11 protocol for multi WLAN configurations
Forum: IEEE International Conference on Personal Wireless Communication (ICPWC 2005)
• Title: The development of Macro-modelling tool to develop IBIS Models
Forum: Pyramid, Libraries ASIC and You (PLAY-2006), TI Bangalore
• Title: 10X Library Characterization
Forum: Texas Instruments India Technical Conference 2005

Award and Recognition

1. Received best physical design lead/manager award for delivering 5nm project with high quality and
better than expected timelines.
2. Received Intel department recognition (from VP) for owning and executing PDN convergence for a
graphics server project. Taken up the project in broken stage and completed flawless convergence.
3. Received multiple recognition in Intel for PDN convergence across different projects for quality PDN
signoff
4. Qualcomm CAD Super Achiever Award 2017
5. Ten different Qualcomm QUALSTAR awards, for ten different topics.
6. Infineon VP Spotlight award with a 10000 Euro cash award, one of the highest-level recognitions in
Infineon.
7. AMD Spirit of success award by US team. (Highest recognition in AMD)
8. AMD Spotlight award by US team for enabling and supporting analysis flows for Trinity project
9. AMD Spotlight award by US team for implementing the EGADS recommendation on AMD first fusion
product
10. AMD Lonestar award by US team for executing voltage domain checks and clock domain checks at
gate level netlist for 40nm fusion project.
11. AMD Hoysala award by India team for developing a stdcell library quality checks and
tool release infrastructure
12. Merit award for 25X cycle time reduction for IBIS model generation in TI India.
13. Winner of Hardware Design contest in inter college tournament.
14. Inter college science quiz competition winner.
15. First prize in inter school science exhibition in class 12th.

References Upon Request