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Entity Décodeur

The document describes various digital circuit components including decoders, adders, and flip-flops, detailing their entity and architecture definitions in VHDL. It includes a 1-to-4 decoder, a 3-to-8 decoder, an adder with carry, a D flip-flop, and an RS latch. Each component is defined with its ports and the logic behavior is specified in the respective architectures.

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mokhtarseba36
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12 views7 pages

Entity Décodeur

The document describes various digital circuit components including decoders, adders, and flip-flops, detailing their entity and architecture definitions in VHDL. It includes a 1-to-4 decoder, a 3-to-8 decoder, an adder with carry, a D flip-flop, and an RS latch. Each component is defined with its ports and the logic behavior is specified in the respective architectures.

Uploaded by

mokhtarseba36
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Entity Décodeur_1-4 is

Port (A, B in std_logic;

Y0,Y1,Y2, Y3: out std_logic);

end Décodeur-1-4;

Architecture arch of Decodeur is

begin

Y0 <= (not A) nand (not B)

Y1 <= A nand (not B)

Y2 <= (not A) nand B

Y3 <= A nand B

end arch;
--Décodeur 3 vers 8

entity DECODEUR is

Port (E: in std_logic_vector (2 downto 0);

S : out std_logic_vector (7 downto 0));

end DECODEUR;

architecture behavioral of DECODEUR is

begin

process (E)

begin

case E is

when “000” =>S<=“00000001”;

when “001” =>S<=“00000010”;

when “010” =>S<=“00000100”;

when “011” =>S<=“00001000”;

when “100” =>S<=“00010000”;

when “101” =>S<=“00100000”;

when “110” =>S<=“01000000”;

when “111” =>S<=“10000000”;

end case;

end process;

end behavioral;
entity ADDI is

port( A, B, Ri :in std_logic ;

S, R : out std_logic) ;

end ADDI;

architecture FLOT of ADDI is

begin

S<=(A xor B) xor Ri;

R<=(A and B) or ((A xor B) and Ri);

end FLOT;
entity BASCULE_D is

port ( D,CLK : in std_logic;

S : out std_logic);

end BASCULE_D;

architecture DESCRIPTION of BASCULE_D is

begin

process (CLK)

begin

if (CLK'event and CLK ='1') then

S <= D;

end if;

end process;

end DESCRIPTION;
entityADDi is

port( A, B, Ri : in std_logic; S, R : out std_logic);

end ADDI;

architecture STRUCTURE of ADDI is

component DEMI_ADDI

port (A, B : in std_logic; S, R : out std_logic);

end component;

component PORTE_OU

port (E1, E2 : in std_logic; Z : out std_logic);

end component;

signal S1, S2, S3 : std_logic;

begin

C1 : DEMI_ADDI port map( A, B, S1, S2);

C2 : DEMI_ADDI port map( S1, Ri, S, S3);

C3 : PORTE_OU port map( S3, S2, R);

end STRUCTURE;
entity RS_NAND is

Port ( S , R : in STD_LOGIC;

Q , Q_b : buffer STD_LOGIC );

end RS_NAND;

architecture Behavioral of RS_NAND is

begin

process(R, S)

begin

if (R = '0' and S = '0') then

Q <= '1';

Q_b <= '1';

elsif (R = '0' and S = '1') then

Q <= '1';

Q_b <= '0';

elsif (R = '1' and S = '0') then

Q <= '0';

Q_b <= '1';

else

Q <= Q;

Q_b <= Q_b;

end if;

end process;

end Behavioral;
entity D_Flip_Flop is

Port (D, Clk, Clear, Preset : in STD_LOGIC;

Q, Q_b : out STD_LOGIC );

end D_Flip_Flop;

architecture arch of D_Flip_Flop is

begin

process (Clk, Preset, Clear)

begin

if (Clear = '0' and Preset = '0') then

Q <= '_';

Q_b <= '_';

elsif (Clear = '0' and Preset = '1') then

Q <= '0';

Q_b <= '1';

elsif (Clear = '1' and Preset = '0') then

Q <= '1';

Q_b <= '0';

elsif (Clear = '1' and Preset = '1') then

if (Clk'event and Clk = '1') then

Q <= D;

Q_b <= not D;

end if;

end if;

end process;

end arch;

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