1)Verilog code for AND gate
module and1(a, b, y);
input a, b;
output y;
assign y = (a & b);
endmodule
*Waveform for AND gate
2)Verilog code for OR gate
module or1(a, b, y);
input a, b;
output y;
assign y = (a | b);
endmodule
*Waveform for OR gate
3)Verilog code for NOT gate
module not1 (a, y);
input a;
output y;
assign y = (! a);
endmodule
*Waveform for NOT gate
4)Verilog code for NAND gate
module nand1(a, b, y);
input a, b;
output y;
assign y =! (a & b);
endmodule
*Waveform for NAND gate
5)Verilog code for NOR gate
module nor1(a, b, y);
input a, b;
output y;
assign y =! (a | b);
endmodule
*Waveform for NOR gate
6)Verilog code for XOR gate
module xor1(a, b, y);
input a, b;
output y;
assign y=a ^ b;
endmodule
*Waveform for XOR gate
7)Verilog code for XNOR gate
module xnor1(a, b, y);
input a, b;
output y;
assign y =! (a ^ b);
endmodule
*Waveform for XNOR gate
Verilog code for Structural model
module structural (a, b, c, d, e, y);
input a, b, c, d, e;
output y;
wire y1, y2;
and g1(y1, a, b);
and g2(y2, c, d, e);
or g3(y, y1, y2);
endmodule
Verilog code for Dataflow model
module dataflow(a, b, c, d, e, y);
input a, b, c, d, e;
output y;
assign y = (a & b) | (c & d & e);
endmodule
Waveform for structural and dataflow model
Verilog code for behavioural model
module behavioural(a, b, y);
input a, b;
output y;
reg y;
always @ (a or b)
begin
if((a==0) && (b==0))
y=0;
else y=1;
end
endmodule
Waveform form for Behavioural model
Verilog code for structural model of Full Adder
module stradder(a, b, c, s, y1, y2, y3, y4, c0);
input a, b, c;
output s, c0, y1, y2, y3, y4;
xor g1(y4, a, b);
xor g2(s, y4, c);
and g3(y1, a, c);
and g4(y2, b, c);
and g5(y3, a, b);
or g6(c0, y1, y2, y3);
endmodule
Waveform of structural model of Full Adder
Verilog code for Dataflow model of Full Adder
module dataadder(a, b, c, s, c0);
input a, b, c;
output s, c0;
assign s= (a^ b^ c);
assign c0= (b & c) | (a & b) | (a & c);
endmodule
Waveform for Dataflow model of Full Adder
Verilog code for behavioural model of Full Adder
module behadder(a, b, c, s, c0);
input a, b, c;
output s, c0;
reg s, c0;
reg w, x, y, z;
always @ (a or b or c)
begin
w=a & b;
x=a & c;
y=b & c;
c0=w + x + y;
z=a ^ b;
s=z ^ c;
end
endmodule
Waveform for Behavioural model of Full Adder
Verilog code for structural model of Full Subtractor
module strsub (a, b, bi, y1, y2, y3, y4, d, b0);
input a, b, bi;
output b0, d, y1, y2, y3, y4;
xor g1(y4, a, b);
xor g2(d, y4, bi);
and g3(y1, (~a), bi);
and g4(y2, b, bi);
and g5(y3, (~a), b);
or g6(b0, y1, y2, y3);
endmodule
Waveform for Structural model of Full Subtractor
Verilog code for Dataflow model of Full Subtractor
module datasub (a, b, bi, d, b0);
input a, b, bi;
output d, b0;
assign d= (a ^b ^bi);
assign b0=((~a) & bi) |((~a) & b) | (b &bi);
endmodule
Waveform for Dataflow model of Full Subtractor
Verilog code for Behavioural model of Full Subtractor
module behsub(a, b, bi, d, b0);
input a, b, bi;
output d, b0;
reg d, b0;
reg w, x, y, z;
always @ (a or b or bi)
begin
w= (! a & bi);
x= (! a & b);
y=b & bi;
b0=w + x + y;
z=a^b;
d=z^bi;
end
endmodule
Waveform for Behavioural model of Full Subtractor
Verilog code for Incomplete Boolean Expression
module incompletedata(a, b, c, d, f);
input a,b,c,d;
output f;
assign f=((!c)&d)|((!a)&b)|(a&(!b)&c);
endmodule
Waveform for Incomplete Boolean Expression
Verilog code for BCD to Excess 3
module bcdtoexcess3(a, b, c, d, w, x, y, z);
input a, b, c, d;
output w, x, y, z;
assign w=a | (b & d) |(b&c);
assign x= (b& (! c) & (! d)) | ((! b) &d) | ((! b) &c);
assign y=! (c ^ d);
assign z= (! d);
endmodule
Waveform for BCD to Excess 3
Verilog code for 2:1 multiplexer
module mux2to1(I0, I1, S, Y);
input I0, I1, S;
output Y;
assign Y=(((!S)&I0)|(S&I1));
endmodule
Waveform for 2:1 Multiplexer
Verilog code for 4:1 multiplexer
module mux4to1(I0,I1,I2,I3,S0,S1,Y);
input I0,I1,I2,I3,S0,S1;
output Y;
assign Y=((!S1)&(&S0)&I0)|((!S1)&S0&I1)|(S1&(!S0)&I2)|(S1&S0&I3);
endmodule
Waveform for 4to1 Multiplexer
Verilog code for 8to1 Multiplexer
module mux8to1(I0, I1, I2, I3, I4, I5, I6, I7, S0, S1, S2, Y);
input I0, I1, I2, I3, I4, I5, I6, I7, S0, S1, S2;
output Y;
assign
Y=((!S2)&(!S1)&(!S0)&I0)|((!S2)&(!S1)&S0&I1)|((!S2)&S1&(!S0)&I2)|((!S2)&S1&S0&I3)|(S2&(!S1)&(!
S0)&I4)|(S2&(!S1)&S0&I5)|(S2&S1&(!S0)&I6)|(S2&S1&S0&I7);
endmodule
Waveform for 8to1 Multiplexer
Verilog code for 2:4 Decoder
module dec2to4(a, b, y1, y2, y3, y4);
input a, b;
output y1, y2, y3, y4;
assign y1=(!a)&(!b);
assign y2=(!a)&b;
assign y3=a&(!b);
assign y4=a&b;
endmodule
Waveform for 2:4 Decoder
Verilog code for 3:8 Decoder
module dec3to8(a, b, c, y0, y1, y2, y3, y4, y5, y6, y7);
input a, b, c;
output y0, y1, y2, y3, y4, y5, y6, y7;
assign y0=(!a)&(!b)&(!c);
assign y1=(!a)&(!b)&c;
assign y2=(!a)&b&(!c);
assign y3=(!a)&b&c;
assign y4=a&(!b)&(!c);
assign y5=a&(!b)&c;
assign y6=a&b&(!c);
assign y7=a&b&c;
endmodule
Waveform for 3:8 Decoder
Verilog code for SR Flipflop
module srff(s, r, clk, q);
input s, r, clk;
output q;
reg q;
always @ (posedge clk)
begin
if(s==0&&r==0)
q<=q;
else if(s==0&&r==1)
q<=0;
else if(s==1&&r==0)
q<=1;
else if(s==1&&r==1)
q<=0;
end
endmodule
Waveform for SR Flip-Flop
Verilog code for JK Flip-Flop
module jkff(j, k, clk, q);
input j, k, clk;
output q;
reg q;
always @ (posedge clk)
if(j==0&&k==0)
q<=q;
else if(j==0&&k==1)
q<=0;
else if(j==1&&k==0)
q<=1;
else if(j==1&&k==1)
q<=~q;
endmodule
Waveform for JK Flip-Flop
Verilog code for D Flip-Flop
module dff(d, clk, q);
input d, clk;
output q;
reg q;
always @ (posedge clk)
begin
if(d==0)
q<=0;
else
q<=1;
end
endmodule
Waveform for D Flip-Flop
Verilog code for T Flip-Flop
module tff(t, clk, q);
input t, clk;
output q;
reg q;
always @ (posedge clk)
begin
if(t==0)
q<=q;
else
q<=~q;
end
endmodule
Waveform for T Flip-Flop
