International Journal of Scientific Engineering and Applied Science (IJSEAS) - Volume-1, Issue-3, June 2015

ISSN: 2395-3470
www.ijseas.com

Design and Implementation of General Purpose Input Output

(GPIO) Protocol
Bhavnil Patel1 , Bhargav Tarpara2
P P P

1
P P M.Tech. VLSI, U.V.Patel college of Engineering and Technology, Kherva, Mehsana, India
2T 2T

2
Verification Technical Assistant
P P

Abstract— General purpose input/output

42T 42T
controllers in a system and necessary simple
(GPIO) is a generic pin on an integrated input and/or output software controlled signals
circuit (IC) whose behavior, including [1].
whether it is an i/o pin, that can be controlled The pins can be programmed as input,
by the user at run time. GPIO pins have no where data from several external source is being
special purpose defined, and by default fed into the system to be flexible at a desired
unused. The idea after that sometimes the time and location. Output can also be execute on
system integrator building a full system that GPIOs, where formatted date can be transmitted
accustom the chip might find it useful to have efficiently to outside devices, this provides a
a handful of immense digital control lines, simple implement to program and re transmit
and having these accessible from the chip can data depending on user desires through a single
save the hassle of having to arrange port interface. The pins are generally arranged
additional circuitry to give them. In this into groups of 8 pins where signals can be sent
paper i have tried to implement GPIO design or received to and from other sources [1].
using FPGA (Field Programmable Gate
Array).That design check throw Directed In many applications, the GPIOs can be
Test case and apply that RTL(Register configured as interrupt lines for a CPU to signal
Transfer Level) in Physical Design (Backend immediate processing of input lines. In many
side) so a complete ASIC (Application designs, they also have the ability to control and
Specific Integrated Circuit) cycle. utilize Direct Memory Access (DMA) to
transfer blocks of data in a more effectively.
Keywords—General
42T Purpose
42T Input/output Significantly all ports can be tailored to fit
(GPIO), Integrated Circuit (IC), Field specific design aims and serve reusability within
Programmable Gate Array (FPGA), Register applications [1].
Transfer Level (RTL),Application Specific
Integrated Circuit (ASIC), Advanced Peripheral Every GPIO port can be configured for
Bus (APB), Advanced Microcontroller Bus i/o or bypass mode. All output data can be set in
Architecture (AMBA), Universal Verification one access Single or multiples bits can be set or
Methodology (UVM) cleared independently. Each GPIO port can
provide an interrupt source and has its own
I. INTRODUCTION configuration options:
A General Purpose Input/output (GPIO)
is an interface available on latest 1.Level sensitive, single edge triggered or
microcontrollers (MCU) to provide an ease of level change.
access to the devices internal properties. 2.Active high or low respectively rising edge
Generally there are multiple GPIO pins on a or falling edge.
single MCU for the use of different interaction 3.Individual interrupt enable register and
so concurrent application. The GPIO IP core is status flags.[2]
user-programmable general-purpose I/O
controller. It is used to mechanism functions that The core provides several synthesis
are not implemented with the dedicated options to ease the system integration and
minimize the gate count:

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 International Journal of Scientific Engineering and Applied Science (IJSEAS) - Volume-1, Issue-3, June 2015
ISSN: 2395-3470
www.ijseas.com

1.Selectable CPU bus width: default options 2. GPIO pins can be enabled/disabled.
are 8/16/32-bit. 3. Input values are like high=1, low=0.
2.Selectable number of GPIO ports. 4. Output values are writable/readable
3.CPU read back enable.[2] 5. Input values can often be used as IRQs
(typically for wakeup events)
6. GPIO peripherals vary absolutely widely.
In some of the cases, they are much
simple, a group of pins which can be
switched as a group to either i/p or o/p. In
others case pins can be set up flexibly to
accept or source different logic voltages
like configurable drive strengths and pull
ups/downs. The input and output voltages
are not in all instances, that is limited to
Figure 1: GPIO module Diagram [2]
the supply voltage of the device with the
GPIOs on and may be damaged by greater
Objectives:
voltages.
7. A GPIO pin's state may be exposed to the
General Purpose I/O (GPIO) pins are
software developer through one of a
single necessary to give versatile to digital and
number of multiple interfaces, like a
analog signals for ADC conversions. To provide
memory mapped peripheral, or by
efficiency the signals should be nuclear
dedicated IO port instructions.
controllable on a particular chip board. All
8. A few GPIOs have 5 V tolerant inputs:
GPIO should be able to define either an input
even when the device has a low supply
mode or an output mode for individual pins on
voltage such as 2 V, the device can accept
the chip. At last the pins must be extendable for
up to 5 V without damage.
a wide array of applications and functional uses
that define its generality in use.
Ports:
A GPIO port is a group of GPIO pins
Usage:
(typically 8 GPIO pins) manage in a group and
controlled as a group.
1.Devices with pin scarcity integrated
circuits such as system-on-a-chip,
The reminder of the paper is organized
embedded and custom
as follows section II descried GPIO Architecture
hardware, and programmable logic devices
& Block Diagram.
(for example, FPGAs).
2.Multi-function chips power managers,
audio codecs, and video cards. II. GPIO Architecture & Block
3.Embedded applications (for example, Diagram
Arduino, BeagleBone, PSoC kits and
Raspberry Pi) make heavy use of GPIO for GPIO Architecture:
reading from various environmental
sensors (IR, video, temperature, 3-axis General architecture of GPIO IP core. It
orientation, and acceleration), and for consists of four main building blocks:
writing output to DC motors (via PWM),
audio, LCD displays, or LEDs for status. 1.APB(Master & Slave)
2.GPIO registers
Capability: 3.Auxiliary inputs
4.Interface to external I/O cells and pads [3]
1. GPIO pins can be configured to be input
1. APB:
or output.

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 International Journal of Scientific Engineering and Applied Science (IJSEAS) - Volume-1, Issue-3, June 2015
ISSN: 2395-3470
www.ijseas.com

The APB is part of the AMBA protocol be used. ECLK register is worked as a part of
logic family. It display a chipper interface that is external interface. Usually register inputs based
optimized for minimal power consumption and on External clock reference.[3]
reduced interface complexity.
The APB protocol is not pipe lined, APB
use it to connect to lower bandwidth peripherals Features:
which do not wants the high performance of the
AXI protocol. 1. Number of general-purpose I/O signals is
The APB protocol relates a signal user selectable and can be in range from 1
transition to the rising edge of the clock, to to 32. For more I/O multiple GPIO cores
simplify the integration of APB peripherals into can be used in parallel.
any design flow. Every transfer takes minimum 2. Each general-purpose I/O signals can be
2 cycles.[4] bi-directional external bi-directional I/O
Cells are required in this case.
2. GPIO Registers: 3. Each general-purpose I/O signals can be
The GPIO IP Core has multiple software three-stated or open-drain enabled
accessible registers. Some of them registers have (External 3 state or open-drain Input-
the same width as no. of general-purpose Input- Output cells need in this case).
Output signals and they are from 0– 31 bits. The 4. General-purpose I/O signals
Host through these registers programs type and programmed as inputs can cause an
operation of each general-purpose Input-Output interrupt request to the CPU.
Signal.[3] 5. General-purpose I/O signals
programmed as inputs can be registered at
raising edge of system clock or at user
programmed edge of external clock.
6. All general-purpose I/O signals are
programmed as inputs at hardware reset.
7. Auxiliary inputs to GPIO core to bypass
outputs from RGPIO_OUT register.
8. Alternative input reference clock signal
from external interface.
9. Especially configurable (implementation
of registers, external clock reverse versus
needle flip-flops etc.)
10. APB interface

Figure 2: GPIO Core Architecture GPIO Operation:

3. Auxiliary Inputs: This section explain the operation of the

The auxiliary inputs can bypass GPIO core. The GPIO core provides toggling of
RGPIO_OUT outputs based on programming of general-purpose outputs and sampling of
RPGIO_AUX register. It can be used to general-purpose inputs under software
multiplex other on chip peripheral devices on control.[3]
GPIO pins.[3]
General-purpose inputs can create
4. Interface to External I/O Cells and Pads: interrupts so that software does not have to be in
External interface connects GPIO core to poll mode all the time when sampling inputs.[3]
external Input-output ring cells and pads. To Switching output drivers into open-drain
assist open drain or 3 state outputs, suitable or 3 state mode will disable general-purpose o/p.
open-drain or three-state Input-output cells must To lower number of pins of the chip, other on-

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 International Journal of Scientific Engineering and Applied Science (IJSEAS) - Volume-1, Issue-3, June 2015
ISSN: 2395-3470
www.ijseas.com

chip peripherals devices can be multiplexed Table 1. List of All Software Accessible
each other with the GPIO pins. For this object, Registers [3]
auxiliary inputs can be multiplexed on general-
purpose outputs.

I/O Ports:
GPIO IP core has three interfaces.

1.APB interface
2.Auxiliary inputs interface
3.Interface to external I/O cells and pads [3]

1.APB interface:
• Master Description:
APB is a single bus master so there is no
need for an arbiter. The master carry the address
and write buses and also express a conjugative
decode of the address to decide which PSELx
signal to trigger and it is also important for
driving the PENABLE signal to time the
Figure 3: GPIO Block Diagram transfer. It carry APB data onto the system bus
during a read transfer.[4]
GPIO Operations:
• Hardware Reset • Slave Description:
• General-Purpose I/O as Polled Input APB slaves have a much simple and
• General-Purpose I/O as Input in Interrupt flexible interface. The perfect implementation
Mode the interface will be dependent on the design
• General-Purpose I/O as Output style employed and many non-identical options
• General-Purpose I/O as Bi-Directional I/O are possible. In this two signals are mainly
• General-Purpose I/O driven by Auxiliary
protect the loss data while transfer of data. They
Input.[3]
are PSLVERR and PREADY.[4]
GPIO Registers:
This section describes all control and 2.Auxiliary inputs:
status register inside the GPIO core.[3] Auxiliary inputs descried above.
Name Width Access Description
RGPIO_IN 0 – 31 R GPIO input data Port Width Direction Description
RGPIO_OUT 0 – 31 R/W GPIO output data aux_i 0-31 Inputs GPIO
auxiliary
RGPIO_OE 0 – 31 R/W GPIO output
inputs
driver enable
RGPIO_INTE 0 – 31 R/W Interrupt enable
Table 2. Auxiliary input signals [3]
RGPIO_PTRIG 0 – 31 R/W Type of event
that triggers an
interrupt 3.Interface to external I/O cells and pads
RGPIO_AUX 0 – 31 R/W Multiplex
Auxiliary inputs External interface connects GPIO core to
to GPIO outputs external I/O ring cells and pads. To assist open
RGPIO_CTRL 2 R/W Control register
RGPIO_INTS 0 – 31 R/W Interrupt status
drain or 3 state outputs, I/O cells with open
drain or 3 state used.

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ISSN: 2395-3470
www.ijseas.com

Part of external interface is also ECLK

signal. It can be used to register inputs based on When all APB signal trigger that time
external clock reference.[3] Data which contained in PWDATA has been
stored to ext_pad_o and PRDATA.

Port Width Direction Description

in_pad_i 0-31 Inputs GPIO inputs
out_pad_o 0-31 Outputs GPIO outputs
oen_padoen_o 0-31 Outputs GPIO output
drivers
enables (for
three-state or
open-drain
drivers)
ext_clk_pad_i 1 Input Alternative
GPIO inputs'
latch clock

Table 3. External interface [3]

III. GPIO Simulation Results

Figure 6. Simulation result of PSLVERR
(Failure)

Over here address of PADDR given

wrong then it shows transfer Failure so
PSLVERR high(1) and PRDATA & ext_pad_o
low(0).

Figure 4. Simulation result of Input Register

Whenever all APB signal and ext_pad_i

trigger at posedge of PCLK , Data which is
contained by ext_pad_i has been stored to
PRDATA .

Figure 7. Simulation result of Output Enable

Register

When output enable is trigger then

PWDATA contained has been stored in
ext_padoe_o & PRDATA.

Figure 5. Simulation result of Output Register

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 International Journal of Scientific Engineering and Applied Science (IJSEAS) - Volume-1, Issue-3, June 2015
ISSN: 2395-3470
www.ijseas.com

[2].INICORE,
http://inicore.com/pdf/act/mb_gpio_mod_act
.pdf
[3]. OpenCores: http://opencores.org
[4]. AMBA Specification: http://www-
micro.deis.unibo.it/~magagni/amba99.pdf
[5]. Chris Spear, ”System Verilog for
Verification”
[6]. Samir Palnitkar ” Verilog HDL A Guide to
Digital Design and Synthesis”

Figure 8. Simulation result of Interrupt status

Register

In this interrupt status shows by IRQ

high, data of PWDATA has been stored in
PRDATA but ext_pad_o low because is show
interrupt cause by input.

CONCLUTION:
This paper gives an outline of the GPIO
Protocol and explain the GPIO working in
detail. The GPIO is designed using the Verilog
HDL according to the specification and is
verified using Xilinx. The simulation results
show that the data write into register and read
form registers, that value stored in a output side.
Hence, the design is functionally correct. Xilinx
also ensures the functional correctness of the
design.

MOTIVATIONAL WORK:
In this paper, Design of GPIO is verified
though a Direct Test Case in Xilinx. But you can
also verified in UVM by applying a Random or
Direct Test Cases. After verified that design
dump in to Design Complier (DC) and ICC. So,
a full ASIC cycle complete and after that a
design will Tap out.

IV. REFERENCE

[1].Sasang Balachandran, “General Purpose

Input/Output(GPIO)”:
http://www.egr.msu.edu/classes/ece480/caps
tone/fall09/group03/AN_balachandran.pdf
GPIO

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