Dig1talFlectronnc 6-2

6.1 Introduction Synchronous Counter : When counter

AU Dec.-08, 17
such that each flip-flop in the
A
group of flip-flops
register. Aregister connected together forms a
the same time, the
COunter
is counter is
is used solely for storing and called
shifting
data
entered from anwhich
sequence of states external
is in the form of 1s and/or 0s,
except insource
certainI very
has no speific
counter.

Asynchronous Counter I Ripple Synhto

specialized
applications. Acounter is a register capable of binary asynchronous/ripple Counter
series Connection of
Countcoensr:ists N
counting the number of clock puulses arriving at its complementing
clock input. Count
pulses arrived. On represents
counter is
the number of clock
arrival of cach clock pulse, the
the output of each flip--flop
input of the next higher-order
holding the least significant bit
fl
connected to ip -opsh
flip-flop. The dheke,
counter, it is incremented by one. In case of down
receives the
decremented by one.
The Fig. 6.1.1 shows
the logic symbol of a binary
COunter. External clock is applied to the
clock pulses.
The Table 6.1.1 shows
synchronous and asynchronous
the
compari son inco
Counters. betweo
ming
clock
cOunter. The counter can be positive input
of the
Sr Asynchronous counters
triggered or negative edge triggered. The n-bit edge
COunter has n flip-flops and it has 2n
of outputs. For example,
binary
distinct states
No.

1 In this type of counter Syncthishrotypenous counters

In
2-bit
and it has 4(2) distinct statescounter has 2 flip-flops
flip-flops are connected
in such a way that connectio n thwereeenis no
bet
: 00, 01, 10 and 1I. output of first flip-flop output first
and of
Similarly, the 3-bit binary counter has 3
it has 8 (2) distinct flip-flops and drives the clock for the
next clock inputlip-lon
flip-flop. of the
states : 000, 001, 010, 011, 100, next flip-flop.
101 110 and 111. 2 Allthe flip-flops are All the
not clocked
simultaneously. clocked flsiimp-iullotapsneouslarey
CLK n-bit
cOunter
3 Logic circuit is very Design involves
simple even for more complex logic circuit
number of states. as number of states
increases.
4 Main drawback of As clock is
n-bit output these counters is their
(a) Positive edge triggered low speed as the clock simultaneously given
to all flip-flops there is
n-bit counter is propagated through no problem of
number of flip-flops propagation delay.
before it reaches last
Hence they are high
flip-flop. speed counters and are
CLK n-bit preferred when
cOunter
number of flip-flops
increases in the given
design.
Table 6.1.1 Synchronous Vs asynchronous counters
n-bit output
Modulus of Counter
(b) Negative edge triggered
n-bit counter The total number of counts or stable states a counter
Fig. 6.1.1 Logic symbol of counter can indicate is called 'Modulus. For instance, the
he maximum count that the binary counter can modulus of a four-stage counter would be 16,y Sne
Dunt is 2n-1. For example, in 2-bit binary counter, it is capable of indicating 0000, to 1111,. The term
e maximum count is 2 -1=3 (11 in binary). After 'modulo' is used to describe the count capablity ot
aching the maximum count the counter resets to 0 counters. For example, mod 6 counter goes through
states 0 to 5 and mod 4 counter goes through staes
arrival of the next clock pulse and it starts
0 - 3.
nting again.
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 Counters
6-3

diagram of MOD-10 counter. Fig. 6.2.l shows 2-bit asynchronous counter using JK
state
Draw
the
AU : Dec.-08, Marks 2 flip-flops. As shown in Fig. 6.2.1, the clock signal is
connected to the clock input of only first stage
flip-flop. The clock input of the second stage flip-flop
stage.
is triggered by the O, output of the first
Because of the inherent propagation delay time
clock
through a flip-flop, a transition of the input
first stage
pulse and atransition of the O, output of Therefore,
the same time.
Sp can never occur at exactly
simultaneously triggered,
the two flip-flops are never operation.
which results in asynchronous counter
diagram for two-bit
Fig. 6.2.1 (a) shows the timing changes in the
asynchronous counter. It illustrates the
in response to the clock.
state of the flip-flop outputs HIGH
Fig. 6.1.2 flip-flops are tied to logic
Jand K input of JK each negative edge of
ReviewQuestions hence output will toggle for
cOUnter2 the clock input.
What iS
1 counters.
State ypes of
Comparesynchronous and
asynchronous COunter. 3
4

3. AU : Dec.-17, Marks 2 CP 1L 2

1
counter.
Define modulus of a
1
LSB QA
1 1

62Ripple l Asynchronous Counters MSB Qg

10
11
01
May-03,17, Dec.-09 Count 00 3
1
stage
counter consists of a
Abinary ripple/asynchronous with
series connection of complementing flip-flops, clock diagram for the counter of
connected to the Fig. 6.2.1 (a) Timing
the output of each flip-flop Fig. 6.2.1
flip-flop
input of the next higher-order flip-flop. The Fig. 6.2.2 for
holding the least significant bit receives the
incoming
Ex. 6.2.1 Extend the counter shown in
can be
clock pulses. A complementing flip-flops inputs 3-stages, and draw output waveforms.
obtained from a JK flip-flop with the J and K
or from a T Sol. :
tied together as shown in the Fig. 6.1.2
flip-flop
flip-flop. A third alternative is to use a D
connected to the D
with the complement output
always the
input. In this way, the D input is HIGH
next clock
complement of the present state and the
pulse will cause the flip-flop to complement. Let us JA
see the ripple counter using JK flip-flop. CP

Ka Kg
HIGH
Jp

CPJ Fig. 6.2.2 (a) Logic diagram

Kp

Fig. 6.2.1 A two-bit asynchronous binary counter

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Digital Electronics 6-4

In Fig. 6.2.2 (b), timing diagram for 3-bit asynchronous counter we have not
propagation delays of flip-flops, for simplicity. If we consider the propagation delavs
get timing diagram as shown in Fig. 6.2.3. considered th

0
0 1

0 1 1
1

1 1 1
0

Count 000 00 010 011 100 101 110 111

stage 1 3 4 5 6 7

Fig. 6.2.2 (b) Output waveforms for 3-bit asynchronous COunter

CP 2

fPHL (CP to Qa)

-PHL (CP to Qa)
-fpH (Qa to Qg)
tpuH (Qg to Qc)
PLH
(CP to Qa)
Fig. 6.2.3 Propagation delays in a ripple clocked binary counter
The timing diagram shows propagation delays. We can see that
added in the propagation delay of second stage to decide the propagation delay of the first stage is
transition time for third stage. This
cumulative delay of an asynchronous counter is a major disadvantage in many
limits the rate at which the counter can be applications because it
clocked and creates decoding problems.
Ex. 6.2.2
Draw the logic diagram for 3-stage asynchronous counter with negative
Sol. :
edge triggered flip-flops.
HIGH
When flip-flops are negatively edge
triggered, the Q output of previous B Qg
stage is connected to the clock input CP.
of the next stage. Fig. 6.2.4 shows
3-stage asynchronous counter with KA Kg Qa Kc Qc
negative edge triggered flip-flops. Fig. 6.2.4 Logic diagram of 3-stage negative edge
triggered counter
Ex. 6.2.3 A COunter has 14 stable states 0000 through 1101. If
the input frequency is 50 kHz what will be its
output frequency?
50 kHz
Sol. : 3.57 kHz
14

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 6-5
Counters
The d foreach Alip-flop is 50 ns , determine the maximum operating frequency for MOD-32 ripple

hat MOD-32 uses ive iip-tlops. With tn

=50 ns, the fmax for ripple counter can be
1
given dy
= 4 MHz
nax(ripple) 5x50 ns

Asynchronous I Ripple Down Counter

In the last section we have seen that the
output of counter is incremented by one for each clock
transition. Therefore, we call such counters as up counters. In this
section We see the
asynchronous/ripple down counter. The down counter will coount downward from a maximum count to
zero.

The Fig. 6.2.5 shows the 4-bit HIGH

asynchronous down counter using
IK flip-flops. Here, the clock signal
CP
is connected to the clock input of
only first flip-flop. This connection Kg Qg Kc
is same as asynchronous/ripple up Fig. 6.2.5 4-bit asynchronous down counter
counter. However, the clock input of
the remaining flip-flops is triggered by the @, output of the previous stage instead of QA output of the
previous stage.
The Fig. 6.2.6 shows the timing diagram for 4-bit asynchronous down counter. It illustrates the changes
in the state of the flip-flop outputs in response to the clock. Again the J and K inputs of JK flip-tlops
are tied to logic HIGH hence output will toggle for each negative edge of the clock input.

:
10

0 0 00 0:0 1 0:0

0 0: 0

0
1 1:1

Count 11111101101 1100|1011|1010|1001|1000|0111|0110\0101|0100|0o11|0010 0001 0000

Fig. 6.2.6 Timing diagram of 4-bit asynchronous down counter

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 Digital Electronics
6-6

Down
known counters
mustCounteber
are not
when a desired as widelyof used aspulses
up counters. They are used in situations where it
has occurred. In these situations the
preset to the number input down
desired
counter reaches the zeronumber and then allowed to count down as the pulses are applie
number of pulses have state it is detected by alogic gate whose
output then indicates
that
count
Whener the
is

Ex. 6.2.5 occurred. the preset

For
the clock, Q and the ripple counter shown in Fig. 6.2.7, slhow the complete tining diagram for eight clock
Q,
wavcforms. pulses, showing
High

J Q

CLK C

KÍ

Fig. 6.2.7
Sol. :

3 5 7 8

CLK

LSB Qo 1 1 -

1 1
MSB Q4 1 0

Count 11 10 01 00 11 1 01 800

Fig. 6.2.8
6.2.2 Asynchronous Up / Down Counter
To form an asynchronous up/down counter one control input say M is necessary to control the
operation of the up/down counter. When M = 0, the counter will count up and when M = 1, the
counter will count down. To achieve this the M input should be used to control whether the normal
flip-flop output (Q) or the inverted flip-flop output (O) is fed to drive the clock signal of the sucessive
stage flip-flop, as shown in Fig. 6.2.9 (a). The truth table for such combinational circuit is shown in
Fig. 6.2.9 (b).

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 Counters
6-7

onics

Inputs Output
Mode control MQQ
(M) 000 0
001 1 Y=k
M=0< 0 10 0 for down
0 11 1 counting
Combinational To CLK
Qutputsof 100 0
previousflip-flop circuit of next flip-flop Y=Q
10 1 for up
M=1 1 10 1 counting
(a) The block diagram of 1 11 1
combinational circuit
(b) Truth table

Fig. 6.2.9

For Y MQ

00 01 11 10
M -MO
1 10

1 1 1 MQ

MQ
:.Y= MQ+MQ
b) Logic diagram
a) K-map simplification

Fig. 6.2.10 when the mode

count from 000 up to 111
up/down counter that will
The Fig. 6.2.11 shows the 3-bit input M is 0.
down to 000 when mode control
control input M is 1 and from 111

M
M

High

CLK
Kg Qg

up/down counter
Fig. 6.2.11 3-bit asynchronous
allows the QA and
1on M enables AND gates 1 and 2 and disables AND gates 3 and 4. This
A logic
respective next stages. So that counter will count up.
QE outputs to drive the clock inputs of their and AND gate 3 and 4 are enabled.. This
allows
When M is logic 0, AND gates 1 and 2 are disabled
respective next stages so that counter will
the QA and Q outputs to drive the clock inputs of their
counter. (See Fig. 6.2.12
count down. The Fig. 6.2.12 shows the timing diagramn for 3-bit up/down ripple
on next page).

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Digital Electronics 6-8

Countg
UP/DOWN
=1

4 5 6 8
2 3

0
1 1
L
0 1
1 1 0
Q

1 1
0 1

Count 101 110 111

000 001 010 011 100

UPIDOWN
=0

4 5 6 7
2 3
CLK

1 1
Q

Count 000 111 110 101 100 011 010 001 000

Fig. 6.2.12 Timing diagram for 3-bit UP/ DOWN ripple counter

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 Counters
6-9

/pecoding
Gates
of the
gatesare used to indicate whether counter has reached to particular state. The outputs for
Decoding goes high
are onnected to the AND gate as inputs and the output of the AND gaBe
counter
state. Let us see the Fig. 6.2.13 (a). Here, the output of decoding gate goes
high when
particular
outputs are C = 1, B = 1and A = 1. In Fig. 6.2.13 (b) the output of decoding
gate goes high
counter
counter outputs are C=1, B=0 and A- 0.
when

HIGH

JA
CLOCK
K

Fig. 6.2.13 (a) Decoding gate to indicate state 7 (111)

HIGH

CLOCK
KA Kg Kc

D
indicate state 4 (100)
Fig. 6.2.13 (b) Decoding gate to
desired state. The
connect corresponding outputs to decoding gate inputs to indicate
Similarly, we can
possible state detection for 3-bit counter.
Fig. 6.2.14 gives these connections for all

DD-: D
Fig. 6.2.14 Decoding gate connections
6.2.4 Problem Faced by Ripple Counters (Glitch Problem)
t. This illustrated
We know that, due to the propagation delay the output flip-flop is delayed by time 6. Here,
decodes state
in the waveform shown in Fig. 6.2.15 shows the waveform of the circuit which
the output of flip-flop A triggers the flip-flop B, hence the B waveform is delayed by one flip-flop
delay time (tp) from the negative transition of A. Similarly, the C waveform is delayed by tp from
each negative transition of B.

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 6- 10
Digital Electronics
5

CLOCK

Glitch
CB

CBÃ CLOCK
CLOCK D
glitch
Fig. 6.2.15 Elimination of
7 to state 0.
Let us output waveform when the counter progresses trom state
observe the At point X, A
goes low (A goes high); however, because of flip-flop delay time, B does not go low
Thus between points Xand Y we have the condition C=1, B=1 and A =1. As a res1ult until point Y
the
high between points Xand Y. This undesirable output is known as glitch. We can avoid
the gloutitcphutiOns
the output waveform by connecting clock as afourth input to the decoding gate along with inputs A, B
and C. This is illustrated in the Fig. 6.2.15.

Review Questions
1. Explain in detail the operation of a 4-bit binary ripple counter. AU: Dec.-09, Marks 16
2. Explain the working of asynchronous down counter.
3. Design and explain the working of an up-down riyple counter. AU : May-03, Marks 8
4. What do you mean by asynchronous counter?
5. State the problem faced by ripple counters.
6. What is the primary disadvantage of asynchronous counter ? AU : May-17; Marks 2

6.3 Design of Ripple (Asynchronous) Counters AU : Dec.-04, May-06, 09, 11

The steps involved in the design of asynchronous counter are :

1 Determine the number of flip-flops needed.
2. Choose the type of flip-flops to be used T or JK. If T flip-flops are used connect T input of all
flip-flops to logic 1. If JK flip-flops are used connect both J and K inputs of all flip flops to logic 1.
Such connection toggles the flip-flop output on each clock transition.
3 Write the truth table for the counter.
4 Derive the reset logic by K-map simplification.
5. Draw the logic diagram.
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 Counters
6-11

DesiguBCDriyple counter using JK flip-flop. 11, Marks 16

AU Dec,-04, May-06,

0-9, i.e.
1: Determine the number of flip-flops needed. The BCD counter goes through states
Step total 10 states. Thus, N= 10 and for 2">N, we need n =4, i.e. 4 flip-flops required.
Step2: Type of flip-flops to be used: JK
Write the
W truth table for the counter
Step3 :

Output of Note: The reset input

CLK B D
reset logic Y (CLR)of each Flip-Flop
is active-low input.
0 0 1 input
By making CLR logic0,
1 0 0 0 1 1 of all Flip-Flops counter.
we can reset the
2 1 1 Thus reset logic is
3 0 1 1 designed such a way
that for invalid
0 Valid states, Y= 0 and
4 states counter resets.
5 0 1 1
6 0 1

7 1
1 0 1
1 0 1
1 1 0 0

1 0 1 1
1 1 0 0 Invalid
states
1 1
1 1 0

1 1

counter
Table 6.3.1 Truth table for BCD

Step 4: Derive reset logic

CD CD CD CD
CD
AB 00 01 11 10

AB 00 1 1 1 1
AB 011 1 1
.Y=
AB 11 0 0 0 0

1 0 0
-BC
AB 10 1

Fig. 6.3.1

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 Digital Electronics
6-12
Step 5: Draw logic
diagram.
Logic 1

JA A (MSB)
B Jp D (LSB)
CLK A B D
KA B Kç Kp D
CLR CLR CLR CLR

D
Reset logic

Fig. 6.3.2 Logic diagram of BCD ripple counter

Ex. 6.3.2 Design a 3-bit
Sol. : asynchronous ripple counter using Tflip-flops and explain its operation. AU : May-09, Marks 16
The
Fig. 6.3.3
shows 3-bit a

asynchronous ripple counter using T Logic 1

flip-flops. As shown in Fig.
clock input of only first stage 6.3.3, the A
The clock input of the flip-flop.
second stage Qp
flip-flop is triggered by the QA output
of the first stage and
third stage flip-flop Fig. 6.3.3 3-bit asynchronous counter using T flip-flons
is triggered by the Q
output of second
stage. Because the inherent propagation delay time through aflip-flop, atransition of the
of
pulse and a transition of the O, output of previous stage input clock
can never occur at exactly the same time.
Therefore, flip-flops are never simultaneously triggered, which results in
operation. asynchronous counter
Since, T input is connected to logic 1 each flip-flop toggles at clock
input. The Fig. 6.3.4 shows the
timing diagram for 3-bit asynchronous counter.

CE 2
8

0 1 0

1 1 1

0 0 0 1 1 1 1
Count 000 001 010 011 100 10
stage 110 111
0 1 2 3 4 5 6 7

Fig. 6.3.4 Output waveforms for 3-bit asynchronous counter

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 Counters
6-13

Desumod
6 riyplc counter using Tflip-flops.

1; Determine the number of flip-flop required. Here, counter goes through 0 - 5 states, i.e.,
Step
atal 6 states. ThusN=6 and for 2" > Nwe needn=3, ie. 3 flip-flops.

Step2. Type of flip-flops to be used:T

Step3 :
Step 4 :

B Output of
CLK A
reset logicY
0 0 1 BC
B Bc BC BC
A 01 11 10
00
1 1 1
11
2 1
Valid
3 0 1 1 1 states A 1 11 0

1 0 1 B .Y=
5 1 1

1 1 0 Invalid
states
1
Fig. 6.3.6
Fig. 6.3.5
Step 5: Draw logic diagram

Logic 1
B C
TA A

CLK B
A B
CLR CLR
CLR

Reset logic

Fig. 6.3.7
Review Questions
AU : Dec.-04, Marks 16
1. Explain the working of BCD ripple counter with timing diagrams.
2. Design mod 5 ripple counter using TFlip-Flops.
AU :Dec.-06,14, 16, May-08
6.4 Synchronous Counters
When counter is clocked such that each flip-flop in the counter is triggered at the same time, the
counter is called as synchronous counter.

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 Digital Electronics
8-22 Asynchronous Sequential Citcits
00,01/0
8.6.3.1| Races and Cycles
10/0 When two or more binary state variables

inputchangvae riatbhlier
11/0
01/1 value in response to a change in an
race condition occurs in
inan asynchronous
00,10/1( 00,01/0
)01,11/1
00,10/1
circuit. In case of unequal delays, a race Condition
may cause the state variables to sequential
11/1
unpredictable manner. For example, if thersindhan
change in two state variables due to
change
10,11/0 change
variable such that both change from 00 to in
Fig. 8.6.4 11. Ininput
8.6.3 Race Free State
situation, the difference in delays may
cause the this
variable to change faster than the first
The state assignment step Assignment
in
second
state variables to change in sequence rom 00 resulting the
essentially the same as it is forasynchronous circuits is and then to 11. On the other hand.
except for one difference. In synchronous circuits, variable changes faster than the first, the second
state assignments are madesynchronous circuits, the variables change from 00 to 01 and then to the11. state
circuit reduction. In with the objective of final stable state that the circuit reaches dooeIf the
asynchronous
objective of state assignment is to avoid
circuits, the depend on the order in which the state
critical races. variable
changes,the race condition is not harmful
called a noncritical race. But, if the final and it is
stable state
W

A
PoA

Race condition -S,+

Note: Paa: Propagation delay for A
PaB:Propagation delay for B

Fig. 8.6.5 Timing diagram

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 JFilatroic;
8-23 Asynchronous SequentialCircuits
the
order in which the state variable
race condition is harmful and it is called
race.Such critical races must be avoided for 1

operation. Let us See the 00(00: 11

and critical races.

examples of
01 (01)
races

oncritical
kRaces
11 (11)
10 (10)
86.6
illustrates noncritical races.
It shows
ratsiton
tablesin which Xis a input variable and y, Possible transitions
the state variables Consider a circuit is in a 00 11
00 01
state y,y,X=000 and there is a change in input 00 10
With this charnge in the
0to
1. input there are Fig. 8.6.7 Example of critical race
possibilities
that the state variables may change.
thnee
hmret oither change simultaneously from 00 to 11. Cycles
may change in sequence from 00 to 01 and asynchronous circuit makes a
orthey A cycle occurs when an
thento
11, or they may change in sequence from 00 transition through aseries of unstable
states. When a
andthen to 11. In all cases, the final stable state it introduces cycles,
o10 State assignment is made so that
which results in a noncritical race condition. In care must be taken to ensure
that each cycle
is11, a Cycle does not
8.6.6 final stable state is y,y,x =101. terminates on a stable state. If
Fig. (b) circuit will go from one
Contain a stable state, the
inputs are
unstable state to another, until the
must always be
00E00: 11 00 00 11 changed. Obviously, such a situation
circuits.
11 01 11
avoided when designing asynchronous
0
for making a
11 11 10 Two techniques are commnonly used
critical race free state assignment.
10 11 10 10 1. Shared row state assignment.
Possible transitions: Possible transitions :
2. One hot state assignment.
00 > 11 00 11 10
00 01 11 00 > 10 8.6.3.2| Shared Row State Assignment
10 11 00 01>11’ 10
00
(b) Races can be avoided by making a proper binary
(a) the state
assignment to the state variables. Here,
Fig. 8.6.6 Examples of noncritical races variables are assigned with binary numbers in
such a
any
Critical Races
way that only one state variable can change at
a circuit is To
Fig. 8.6.7 illustrates critical race. Consider time when a state transition OcCurs.
one
a change in accomplish this, it is necessary that states between
in a stable state y,v,x = 000 and there is
variables change which transition occur be given adjacent assignments.
input from 0 to 1. If state
simultaneously, the final stable state is yy,x = 111. If Two binary values are said to be adjacent if they
unequal differ in only one variable. For example, 110 and 11
Y, changes to 1 before Y, because. of the stable
Propagation delay, then the crcuit goes to are adjacent because they differ only in the third bit.
other hand, if Y,
State 011 and remain there. On the Fig. 8.6.8 shows the transition diagram. The transition
circuit goes to the
Changes faster than Y. then the diagram shows that there is transition from state a to
Hence, the race is
Stable state 101 and remain there. state b and transition from state a to state c. The state
goes to different stable
Citical because the circuit a is assigned binary value 00 and state c is assigned
in which the state
States depending on the order binary value 11. This assignment will cause a critical
variables change. race during the transition from a to c because there
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 Digital Electronics 8-24 Asynchronouss
are two
changes in the binary state variables. A race variable for each row of the flow
Scquential Creit C

ee table.
assignment
addition
can be obtained by introducing
which is binary state say d with binary value 10,
the modified
adjacent to both a and c. Fig. 8.6.9 shows
rows are introduced to
changes between internal
provide single
state Ad ditonal
illustrated in the following example.transitions. Thvairsiableis
transition diagram. As shown in the
ig. 8.6.9, the transition from a to c will go Consider a flow table given in Fig..8.6.10 four
This causes the binary through a. variables are used to represent the four rows in state
10 ’ 11 which variables to change from 00
satisfy the condition that only one-’ table. Each row is represented by a case the
binary variable
thus avoiding thechanges during cach state transition,
one of the four state variables is a 1. A where ony
critical race.
This technique is called
from state Ato state B requires two
changes; E from 1 to 0 and , from 0
state
to
travarnsitiiaoblne
because in this techniqueshared row state assignment directing the transition Ato Bthrough a new 1. ByE
extra state, i.e. extra
introduced in a flow table. This extra state shared row is which contains 1s where both states A and B row
between two stable states. We require only one state variable have 1s.
transition A to E and then changeE from
from transition
8.6.3.3 One Hot State to
This permits the race free transition between A B.
The one hot state Assignment B.
for finding a race free assignment is an another method
method, only one variable state assignment. In this In general, we can say that, in row i of the
is active or 'hot for each
row in the original flow table,
state variable F; is 1 and all other state variables are table,
i.e. it requires one state 0. When a transition between row i and
row i ie
required, first state variable F; is set to 1(so that
a=00 both F; and F; are 1), and then F; is set to 0. Thus
b=01

State variables
State
Inputs XX,
F4 F3 F2 F 00 01 11 10
0 00 1 A (A) B C
0 01 0
A ) C D
01 0 0 A B) C
c=11
1 00 0 D D) B C D
Fig. 8.6.8 Transition diagram
Fig. 8.6.10 Flow table

a= 00 each transition between two rows in the flow

b= 01 table
goes through one intermediate row. This permits the
race free transition but requires two state
times.
transition
The Fig. 8.6.11 shows the complete one hot
state
assignment flow table. When X,X, =01 the transition
from A to B is passing through the
dummy state E.
Similarly, when X,Xy =00 the transition from C to A
d= 10 C= 11 is passing through the dummy state F and so on. The
original table thus gets modified and it is as shown
Fig. 8.6.9 Transition diagram with race free state in Fig. 8.6.11.
assignment

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 t alectronics

8-25 Asynchronous Sequential Circuits

State variables
Fa F3 F2 F State Inputs X4 X
00 01 11
0 0 10
A
Original 00 1
table ¤E B C
1 0 0
AF gG
1 0 0 0
D (D BH
0 0 1 1
E A
0 1 0 1 F C C
Added
1 1 0
rows G B
1 0 1 0
H D

1 1 0 0

Fig. 8.6.11 One hot state assignment flow table

86.4Realization of Flow Table
To understand the process of realization of fow table we see the following example. The exaipe
illustrates all the steps of designing of asynchronous sequential circuit.

Examples for Understanding

output Z. Whenever Y
Ex. 8.6.4 Design an asynchronous sequential circuit with two inputs X and Y and with one
X. AU : May-03, Marks 16
is 1, input X is transferred to Z. When Y is 0, the output does not change for any change in
Sol. : Step 1 : Draw state diagram and derive primitive flow table.
8.6.12.
The state diagramn for above problem statemernt can be given as shown in Fig.
shown in Fig. 8.6.13.
A primitive flow table is constructed from the state diagram
XY
00

Present Next state for X Y Inputs Output

state 00 01 41 10
00 00
A B
01 10
01 B B A B D 0
11
11 A D 0
01
01 D 1
00
10 F D 1

11
10 F F B E 1

10
Fig. 8.6.13 Primitive flow table for example problem
for example problem
Fig. 8.6.12 State diagram

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 Asynchronous SequentialCircuits
/Electronice

8-39
the steps involved in the design of OCCur in
the
Smchrononsseguential circuit. delays at different paths. Hazards cause a
AU : Dec.-16,17, Marks 13 combinational circuits, where they may
When
such

Whatisthe objective of state assignment in a temporary false output used in the asynchronous
value.

psynchronoUSciYCuit2
AU : May-17, Marks
combinational circuits are transition to a
13 sequential circuits, they may result in a
wrong stable state.
and
B/DataSynchronizers Static hazards
There are two types of hazards :
static hazard exists if a signal is
synchronizer is a circuit that synchronizes a dynamic hazards. A
value when an
Istemwhere several modules are using their own Supposed to remain at particular logicbut instead the
input variable changes its value,
in its required
cocksbut no Common system clock is available. It
momentary change
asynchronous inputs and synchronize them; Signal undergoes a static hazards are
kesallmake value. According to definition, the static-1
them consistent with the module clock. static-0 hazard and
is,
that further classified as
8.7,1 shows the circuit for simple data hazard.
The Fig. momentarily
synchronizer. It synchronizes single data input with
In a combinational circuit, if output goes
known as
module clock. In this circuit, eventhough the
when it should remain a1. the hazard is
the O goes
asynchronousinput Bappears any time, it is applied other hand, if output
static-1 hazard. On the
synchronous module in synchronization with remain a 0, the hazard
momentarily 1 when it shouldAnother type of hazard
module clock. The Fig. 8.7.2 shows the synchronizer hazard.
1s known as static-0 three or
which output changes
timings. X 1S dynamichazard in should change from to 0 or
1
Synchronized more times when it
data input 1. The Fig. 8.8.1 shows the three types of
from 0 to
D
(Asynchronous to module clock hazards.
datainput) Synchronous
module

T (b) Static-0 hazard (c)

Dynamic hazard
Module (a) Static-1 hazard
clock hazards
Fig. 8.7.1 Simple data synchronizer Fig. 8.8.1 Types of
Assumne
circuit with hazards.
The Fig, 8.8.2 shows = 1. This
Clock 0 and
that, initially, inputs x, and X, =
1 to be 0, that of gate 2 to
causes the output of gate
Xasy
be 1, and the output of the
circuit to be equal to 1.
0. The output
Now consider change in x, from 1to
gate 2 changes to
Xsyn of gate 1 changes to 1 and that of
Fig. 8.7.2 Data synchronizer timings
However, the output
0, leaving the output at 1.
delay
momentarily goes to 0 if the propagation
Review Question consideration.
through the inverter is taken into
1. Write anote on data synchronizer.
X.
Switching Circuits
8.8| Design of Hazard Free
May-03,04,08,09, 10, 12, 13,17,
X
AU : Dec.-02,07,08, 09, 11, 12, 14 Y

(glitches) that may

The unwanted switching transients called Hazards. X
circuit are
appear at the output of a malfunction. The
circuit to
The hazards cause the Fig. 8.8.2
main cause of hazards is the different propagation
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 Digital Electronics 8-40

The delay in the

inverter causes the output of gate 2to change
to 0 before the
to 1. In this situation, both inputs of gate 3 are momentar1ly equat to 0, causing Hho
AoutsypnutdhrOnous
for the short time equal to the propagation delay of the inverter. This is illustratodin gte 1
he iH
&1
X

Output of Propagation delay of inverter +OR gate 1

gate 1

Output of
gate 2 Propagation delay of gate 2 only

Circuit output
Static - 1 hazard

Fig. 8.8.3 Waveforms showing static-1 hazard

8.8.1 Eliminating a
Hazard
The hazard exists
input results in
because of the change of
a different
covering two minterms or
product terns 1 00 01 11 10
00 01
different sum terms 0 1 11 10
COvering two maxterms. Whenever the circuit
0
1
move from one product term 1 1
another or to 1| 1
move one sumn term to
another, there is a
possibility of a momentary (a) Y=xX +XX3
neither term is equal to 1, interval when Fig. 8.8.4
(b) Y=x442*
undesirable 0 output. Hazardsgiving rise to an
can be eliminated
Eliminating hazards
For example, the circuit has minterms x x, + XyX3enclosing
by
twO minterms or maxterms
introducing another minterm x,X,. This is then these two minterms must be in question.
Ex. 8.8.1
Give hazard-free realisation for the
illustrated in Fig. 8.8.4. enclosed by
f (A, B, C, D) = m (0, 2, 6,
7, 8, 10, 12)
following Boolean function.
Sol. : AU :
May-17, Marks 13

CD
AB \CD
00 01 11 10 AB
Group 2 00 01 11 10
00| 1 1
Group 3 00 1: 1
01| J1......1 -Group 1 0 1 |1)
11K1}
11 1

10|1
10|1 1

f=BD+ ABC +ACD f= BD+ ABC + AC D+ ACD

Fig. 8.8.5
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krnowledge
 8-41 Asynchronous Sequential Circuits

The given function can be

shown in the Fig. implemented using A
K-map as 8.8.5 and Fig. 88.6
shows
the additional product term, ACD
overlappingtwo groups (group 1 and group 2) for
hazard free realization. Group 1 and group 3 are
already overlapped hence they do not
additional minterm for require
grouping.
B82 Hazards in Sequential Circuits
D
We know that, in sequential circuits, the
aombinational circuits are associated with them to
drive the flip-flop inputs. In synchronous sequential
circuits, the hazards due to combinational circuits
associated with them are not of concern. This is
Fig. 8.8.6
because momentary errorneous signals are not
generally troublesome in synchronous circuits. sequential circuit, it may
However, if a momentary incorrect signal is fed back in an asynchronous
cause the circuit to go to the wrong stable state.
8.8.8. For the
consider the its transition table as shown in Fig. 8.8.7 and Fig.
Let us logic diagram and changes from
= 111 and input X,
circuit shown in Fig. 8.9.7, ifthe circuit is in total stable state YX;X2 because of hazard, the output Y
1to 0, the next total stable state should be YXX, = 110. However, inverter
before the output of the
may go 0 momentarily. If this false signal feeds back into AND2
to stable total
switch to the incorrect
goes to 1, the output of AND2 will remain at and the circuit will
state 010.

Following figure shows hazards in an asynchronous sequential circuit.

X4 AND 1
00 01 11 10

t-Y=XX,+,Y o0(0) 1 K0

AND 2

Fig. 8.8.7 Logic diagram Fig. 8.8.8 Transition table

shown in the
enclosing two minterms by another minterm as
Such a hazard can be eliminated by
Fig. 8.8.9.

00 01 11 10 00 01 11 10
Y
1
00 0 1 0

1 1 0 1||1 1 1|| 0

Y= XX, +X,Y Y=XX,+X,Y +X,Y

Fia. 8.8.9 The two minterms are enclosed by introducing another minterm XY

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 Digital Electronic: 8-42

Therefore, the hazard free asynchronous sequential circuit will be as shown in

Asynchronous Sequen
Fig. 8.8.10.

X,
AND

AND 2
Y= XX, +X,Y +X,Y

AND 3

Fig. 8.8.10 Hazard free circuit

8.8.3 Essential Hazards
In the previous section we have seen
static and dynamic hazards and remedies to
another type of hazard that may occur in remove
essential hazard is caused by unequal delaysasynchronous sequential circuits, called essential it. There js
input. Such hazards can be eliminated by along two or more paths that
adjusting the amount of delays in the originate from the An hazards.
affected path.
8.8.4 Eliminating Essential Hazards
We can also avoid essential hazards in asynchronous sequential
SR latches. A momentary 0
signal applied to the S or R inputs ofcircuits
a
by implementing them usine
the state of the circuit. Similarly, a NOR latch will have
will have no effect on the state of themnomentary 1signal applied to the S and R inputs of a no efect
latch. NAND Jatch
Let us consider a NAND SR latch
with the following Boolean
functions forS and R.
S = AB + CD

R= AC
Such circuit can be implemented using
two-level circuit of NAND
gates as shown in the Fig. 8.8.11. The first D
level
gates that implement each product term in theconsists NAND
of

expression of S and R. The second level forms theoriginal Boolean

connection of the SR latch with inputs that come fromcross-coupled
the outputs
A
D
of each NAND gate in the first level.
Fig. 8.8.11 Implementation of latch
Illustrative Examples
Ex. 8.8.2 Implement the switching
function F = (1, 3, 5, 7, 8, 9, 14, 15) by a static hazard free
AND-OR gate network. tv0 level
AU : Dec.-02, CSE, Marks 16

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 Asynchronous SequentialCircuits
t t aBectronics
l 8-43

CD
AB 00 01 11 10

00 1 1

01 1

11 1 1

10

F=ABC+BCD+ +BCD +ABC

Fig. 8.8.12
Network
Sol. : AND-OR
A B C D

Fig. 8.8.13
Marks 16
AU : Dec.-02, CSE,
following machine has essential hazard.
Ex. 8.8.3 Using Unger's theorem, show that the asynchronous
an
an essential hazard exists in PS NS
Sol. : We have seen that, next total states
total state, S has a different x =1
circuit when a present stable
X= 0
transitions of
variable X, and after three
after one transition of an input 00 00 01

an input variable X;. 01 11 01

essential hazard
1. 00(0)’ 01(1) ’ 11(0) ’ 10(1) 10 00 10

2 01(1) 11(0) -’ 10(1) ’ 00(0) essential hazard 11 11 10

hazard
3 10(1) - 00(0) ’ 01(1) ’ 11(0) essential
11(0) ’ 10(1) ’ 00(0) 01(1) essential hazard
4

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 Digital Electronics
The essential hazard are
8 - 44
Asynchronous SequertalCi
1.
00(0) ’ 01(1) 2 01(1) ’ 11(0)
3
10(1) ’ 00(0) 4. 11(0) ’ 10(1)
Ex. 8.8.4
Implement the switching function F- J 0, 1, 3, 4, 8, - 12) by a static hazard free tza
network.
\evel
Sol. :

F= CD + AB +BD
AB
CD
01
OR-AND
11
00 1
1
10
1
= F=CD+ AB+BD
01 1
0
- (C+ D)(A +B)(B+D)
11 1
0

1............ 1
10 1

Logic diagram ******* 1

Fig. 8.8.14
B D

Fig. 8.8.15
Ex. 8.8.5 Show that no static 0 (static 1) hazard can happen in a two
level AND-OR (OR-AND) realisation of a
switching function F. AU : May-03, CSE, Marks 16
Sol. : Dynamic hazards due to a change in an
input variable x, can only occur if there are three or more
paths between the x, (and/or x) input and the network
output. Such condition does not exists in two level
AND-OR gate networks hence dynamic hazards do not occur in two
level AND-OR gate networks.
Ex. 8.8.6 Find a static and dynamic hazard free realization for the
) NOR gates F (a, b, c, d) = ))m (1, 5, 7, 14, 15) following function using i) NAND gates
AU : May-04, CSE, Marks 16
ol. : i) Circuit realization using NAND gate
F = ac d+ab d +bcd + abc

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otthonis 8- 45 Asynchronous Sequential Circuits
realization
Circuit using NOR gate
i)

11 10
00 01

00 Enclosing minterm C

01
(11

Fig. 8.8.16 Fig. 8,8.17

Steps :
"Complement inputs. "Complement output and
. Replace NAND gates by NOR gates.

Fig. 8.8.18

functions.
Ex. 8.8.7 Give hazard-free realization for the following Boolean AU : Dec.-07,
CSE/IT, Marks 8

f(A, B, C, D) = ) m(0, 1, 5, 6, 7, 9, 11)

F=AB +ABD +BD +ÃCD+ÃB
D+ÃBC
Sol. :
Refer Fig. 8.8.19
Boolean function.
Ex. 8.8.8 Give hazard-free realization for the following AU : May-08, Marks 8
15)
F(LJ, K, L) = ), m(1, 3, 4, 5, 6, 7, 9, 11,
Sol. : F=JL + IJ + KL +0L
Refer Fig. 8.8.20 IJ 00 01 1 10
CD 00 01 11 10
AB 00 1
00 ..L.....
011 1 1 1
01 1 1 1
11 1
11
10
4
10 1
Fig. 8.8.20
Fig. 8.8.19
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