PROC.

30th INTERNATIONAL CONFERENCE ON MICROELECTRONICS (MIEL 2017), NIŠ, SERBIA, OCTOBER, 9th-11th, 2017

An HDL Model of a Digitally Controlled

Oscillator for Rapid Digital PLL Prototyping
V
Milovanoviʉ
and
B
Nikoliʉ

Abstract— Simulating digitally-controlled oscillators Notwithstanding, the endeavor towards digital PLLs
(DCOs) presents a challenging trade-off between the ac- requested from an oscillator to be a digitally-controlled
curacy and the speed. Simplistic DCO simulations have
been pursued, but had limitations with nonideal effects. device, instead. A couple of distinct design patterns
Here, an event-driven behavioral model of a DCO which in contemporary digitally-controlled oscillators (DCOs)
is able to capture arbitrary oscillating frequency tuning can be observed. Firstly, a hybrid approach, in which a
curves and to support multiple codeword inputs with
varying granularity is presented. The DCO description
conventional analog voltage-controlled oscillator is pre-
provides supply voltage and ambient temperature de- ceded by a digital-to-analog converter (DAC) [2], and
pendencies, as well as the corner tests and random fluc- secondly, direct digital-to-frequency conversion [5]. In
tuations for full PVT variability analysis. It is further either case, the oscillator still suffers from random noise
equipped with thermal and flicker noise models. This
fully-featured HDL implementation of a DCO is intended variations which define its open-loop characteristics.
for use in a discrete-event simulation environment along Noise sources in every DCO may be divided into truly
with the synthesizable logic for rapid digital PLL anal- random, such as thermal and flicker noise, and deter-
ysis. A usual design case of a clock generator demon-
strates the possibility of subtle random noise versus limit
ministic, coming from finite quantization error. And al-
cycle optimization in a quick and convenient manner. though the latter can be well-handled by discrete-event
simulators, continuous-time SPICE-like circuit models
I. Introduction are mandatory in analyzing the contribution of the for-
Deep nanometer CMOS processes favor digitally in- mer ones. It greatly limits digital PLL design efficiency
tensive realizations of traditional analog circuitry. As which is anyway considered cumbersome and slow.
CMOS technology advanced both in downscaling and The oversimplified DCO models, that do not include
complexity, the burden of performance maintenance colored noise sources, simply prove to be inadequate [4]
and adoption of necessary analog components into for the task of an overall digital PLL design. Depend-
newer process nodes quickly overweighted their advan- ing on the time constants that differ by several orders of
tages. Typical example are phased-lock loop architec- magnitude, transient simulations of the complete PLL,
tures which in the past decade exhibited an abrupt shift which contains imported digital netlists in an analog en-
towards fully digital implementations [1–4]. Nowadays, vironment, might take weeks to verify locking process.
digital PLLs are dominant not only in clock generation Fast bit-accurate analog and digital co-simulations [6]
but also in the domain of RF frequency synthesis [1]. sound appealing especially for system-level design and
More recently, partially [2] and even completely [3] optimization, but involve yet another tool, further com-
synthesizable DPLLs emerged as an alternative for ap- plicating already quite complex digital PLL design flow.
plications where strict loop bandwidth is not required. This paper presents a hardware-description language
These somewhat looser scenarios in which jitter and not (or HDL-compatible) model of a DCO that may be im-
precise phase noise level is of paramount importance, al- plemented either in Verilog or any high-level synthesis
lowed replacement of power-hungry time-to-digital con- language. Besides the basic frequency tuning curve it
verters (TDCs) with rather simple bang-bang (1-bit) also features extensions for PVT corner/variability and
binary phase detectors [4] and/or pulse injectors [2, 3]. noise simulations thus enabling a quick system-level op-
Area efficiency of digital loop filters is primarily at- timization and possibility of rapid DPLL prototyping.
tributed to elimination of bulky analog filter capacitors.
Furthermore, they are easily tailored to different needs
by soft programming. Finally, the synthesizable PLL
dc
topologies rely on standard-cell libraries and commer-
d fDCO nc fDCO
cial EDA tools, thereby considerably shortening design
df
cycle and cost. All these facts promote digital PLLs to n
design of choice in modern deeply-scaled technologies. nf

V. Milovanović is with the Faculty of Engineering, University of

Kragujevac, Sestre Janjić 6, Kragujevac, (e-mail: vlada@kg.ac.rs) a) b)
B. Nikolić is with the Department of Electrical Engineering and
Computer Sciences, University of California at Berkeley, 2108 All- Fig. 1. DCO in which the oscillating frequency fDCO depends
ston Way, Berkeley, CA 94704, (e-mail: bora@eecs.berkeley.edu). on a) single, and b) coarse and fine, multibit control codes d.

978-1-5386-2563-7/17/$31.00 ©2017 IEEE

205
 III. DCO Corner Cases and Variability Model
d vtune fDCO The previously outlined digitally-controlled oscillator
n
D/A model did not account for different process (P) corners,
supply voltage (V) nor temperature (T) dependence.
Model extensions that involve PVT variability are crit-
ical in functional verification as they can increase yield.
Fig. 2. DCO simply formed by cascading a DAC and a VCO.
A. DCO Frequency as a Function of Process Corners

II. DCO Frequency vs Code Tuning Curves Presumably the easiest way to include various pro-
cess corners into the proposed HDL oscillator model is
Undoubtedly, the most critical component of any through compiler directives and parametrized modules.
digital PLL system is a digitally-controlled oscillator. In this manner, for example, five front end of line
DCO’s oscillating frequency/period at its output is pro- (FEOL) process corners, in particular typical-typical
portional to the digital code word on its input(s). This (TT), fast-fast (FF), slow-slow (SS), fast-slow (FS), and
frequency/period dependence on the input data does slow-fast (SF) would merely correspond to five sets of
not have to be linear. A single and more multibit inputs DCO parameters and several preprocessor directives.
are equally common, as illustrated by Fig. 1 symbols. Similarly, adding the back end of line (BEOL) tech-
Practical DCOs seldom have linear dependence and use nology corners, or any other kind of corners, indeed
only one n-bit wide input bus. Regardless, linear oscil- reduces down to analogous SPICE simulation followed
lating frequency or period dependence as expressed by: by the extraction and inclusion of the free-running oscil-
fDCO = f0 + KF · d ⇐⇒ TDCO = T0 + KT · d lating frequency/period and its input code sensitivities.

in which f0 /T0 and KF /KT represent the free-running B. Supply Voltage Dependence of the DCO Frequency
frequency/period of the DCO and its frequency/period Even though digitally- and voltage-controlled oscil-
linear sensitivity on the input data d are very useful. lators are almost exclusively supplied through a linear
It should be noted that the equation for the oscil- regulator to prevent power supply noise coupling, it is
lating period directly translates to HDL’s parametric occasionally beneficial to include this indicator, too.
delay control (e.g., #<time> <statement>; in Verilog). As a matter of fact, equipping the provided model
Nonetheless, simple relationship between the oscillating with the dependence on supply voltage VDD does not
frequency and period TDCO = 1/fDCO , enables conve- differ from what has already been done with input d,
nient use of either DCO quantity for its description. apart from supply pin’s analog nature. Even if creating
Linear frequency and period dependencies give an im- a floating-point port in an HDL of choice (e.g., plain
portant insight into the ratio between the sensitivities Verilog) is not supported, it is trivial to circumvent.
at some particular oscillating point. It can be written: It should be stressed here that the very same method-
2 2
ology can be applied to build an HDL model of a VCO.
KF /KT = fDCO /TDCO = fDCO = 1/TDCO .
C. Temperature Dependence of the DCO Frequency
The previous expression provides means to switch be-
tween instantaneous oscillating frequency and period of In practice, output frequency of every oscillator oper-
oscillation even for nonlinear oscillator tuning curves. ating in an open loop will display certain temperature
In cases where independent coarse/fine digital tuning dependence. This temperature instability is eventually
inputs are available, the oscillating frequency or period compensated in the negative feedback loop. In order to
may be coded using additional sensitivity parameters: model temperature-related frequency drift, another real
DCO module input port is allocated and the actual am-
fDCO = f0 + KFcoarse · dcoarse + KFfine · dfine . bient temperature is administered from the testbench.
Internally, the free-running and sensitivity DCO pa-
It usually makes sense when physically independent
rameters would not stay constant, rather they will be a
DCO tuning mechanisms are used, like for example,
function of this floating-point input. There are no lim-
regulating ring oscillator’s supply voltage rail for coarse
itations on the temperature dependency function, but
and capacitive tap load or current through starved in-
straightforward polynomial fit with the coefficients ex-
verters for fine grain frequency or period modulation.
tracted from adequate SPICE simulations often suffice.
To account for potential nonlinearities in, let’s say,
For linear DCO curve, this is analytically expressed:
hybrid DCOs of Fig. 2, the introduction of quadratic,
cubic and even higher order terms in general is just as fDCO (d, T ) = f0 (T ) + KF (T ) · d ,
easily accomplished to fit any tuning curve. Exploiting
look-up table as the universal modeling instrument can where T is the ambient temperature. The given model
also be utilized for rather complex dependency curves. enables realistic prediction of frequency vs temperature.

206
 Oscillator Phase Noise (L) [dBc/Hz]
Power Spectral Density [dBm/Hz] pink
noise thermal & flicker noise −40 thermal & flicker noise
−80 1/f 3

 thermal noise only 
 thermal noise only
−60
−90 corner
frequency
−100 −80
1/f 2

−110 −100


1/f 0
−120 −120
?
−130
−140
−140
−160

104 105 106 107 108 109 104 105 106 107 108 109
Frequency on a Logarithmic Scale (f ) [Hz] Frequency Offset from the Carrier (Δf ) [Hz]

Fig. 3. Generated noise power spectra for the oscillator model. Fig. 4. Simulated phase-noise spectra with the oscillator model.

D. Random Variability of the DCO Tuning Curve Oscillator perturbations observable in the frequency
Yet another crucial component for predicting and im- domain have the underlying cause in the time domain,
proving manufacturing yields in integrated circuit (IC) where the exact time of one oscillating period differs
design are statistical simulations. Perhaps the simplest from another. This timing error variance is called jitter.
form of randomness that could be brought into a model A normally distributed random variable with zero
is by picking its parameters from a predefined proba- mean added to the oscillating period value would act as
bility distribution. That is to say, every parameter of period jitter. In the phase noise power spectral density
the presented oscillator model is sampled from the nor- (PSD) plot it will mimic the thermal noise region featur-
mal distribution (incorporated in Verilog HDL through ing the 1/f 2 slope. To avoid potential spurious tones, a
$dist_normal() system call/function). The expected high quality pseudorandom number generator (PRNG)
parameter value (mean) coincides with the nominal cor- with long repetition periods, such as the widely avail-
ner while its standard deviation is drawn from results able standard Mersenne Twister, should be employed.
of the corresponding SPICE-level Monte-Carlo simula- Contrary to the white one, the colored noise is more
tions. Ultimately, the DCO model parameters are taken challenging to synthesize. Even though approximative
from these distributions before digital simulation is ran. time-domain methods for generating pink (1/f α ) noise
do exist [7], the artificially created noise with arbitrary
IV. Oscillator Phase Noise Modeling frequency shape and accuracy can only be retrieved by
An ideal oscillator concentrates all of its power in a specifying its spectrum. More specifically, in this imple-
single frequency. Real oscillators, however, spread their mentation, the noise sequence values are a product of an
power also into the nearby frequencies. This spectral inverse (Fast) Fourier Transform (FFT) of spectral co-
frequency spreading is often referred to as phase noise. efficients properly scaled within the frequency domain.
Power spectral density of computer-generated pseu- Namely, a temporal noise sequence featuring what-
dorandom noise used in the proposed HDL model and ever noise spectrum profile (including the flicker’s 1/f )
the simulated phase-noise spectrum of a typical oscil- may be obtained by generating the appropriate noise
lator are respectively given in Fig. 3 and Fig. 4 as log- coefficients in spectral space. The magnitudes of the co-
log graphs. The latter one is ordinarily normalized to efficients should be chosen to produce the desired spec-
dBc/Hz and plotted against the offset frequency Δf trum shape while phases should be taken randomly.
from the carrier. The phase noise frequency profile com- Following the inverse FFT with the upper coefficients
monly traverses from the 1/f 3 over 1/f 2 down to 1/f 0 as argument yields the wanted noise sequence values. A
slope regions. The part in the middle is the so-called slight caveat to this method is that precise specification
thermal noise region because it is induced by white or of the coefficient magnitudes would not be strictly cor-
uncorrelated timing variations in the period of oscilla- rect (as they should also be random due to the stochas-
tion. It is actually the up-converted Gaussian noise and tic nature of the process). To fabricate a faithful pink
generally represents the dominant noise mechanism in noise time series, firstly the discrete Fourier transform
oscillators [1]. The 1/f flicker noise of electronic devices (DFT) of time domain white noise is computed to pro-
is also substantial particularly for lower offset frequen- duce its spectrum. This spectrum is then shaped ac-
cies where after upconversion it appears as 1/f 3 region. cording to the noise color flavor (1/f α ) and its parame-
Finally, the flat-band region is the thermal electronic ters (α and the corner frequency fc ). Lastly, the IFFT
noise added outside the oscillator, such as in an output gives desired sequence with the disadvantage that max-
buffer, and does not affect the oscillator’s time base. imum simulation time needs to be known beforehand.

207
 −40

DPLL Phase Noise (L) [dBc/Hz]

fREF ctrl d fOUT bang-bang digital PLL
ε
BPD DLF ΔΣM n free-running DCO
m −60
corner
frequency
−80
fDIV
÷N −100

synthesizable part −120

Fig. 5. Simplified block diagram of a bang-bang digital PLL. −140

−160

V. HDL-Based Digital PLL Design Example 104 105 106 107 108 109
Although noiseless oscillator models can be of use in Frequency Offset from the Carrier (Δf ) [Hz]
analyzing cases when period quantization errors intro-
Fig. 6. Phase-noise of the optimized digital PLL clock generator.
duced by the concurrent presence of phase detector and
finite resolution DCOs are much larger than random-
noise fluctuations, the real difference is made by fully VI. Conclusions
featured oscillator noise model. Now not only the spu-
rious tone locations determined by the limit cycle fre- A complete DCO model intended for digital PLL de-
quencies and caused by quasi-periodic orbits in the state sign and ready to use inside discrete-event HDL sim-
space can be obtained, but also their magnitudes. ulators together with standard digital circuitry is de-
scribed. The proposed model can be exploited to spec-
For the sake of demonstrating the full capability of
ify oscillator requirements or refine them in a system-
the presented DCO model a conventional design proce-
wide DPLL optimization that may be quickly per-
dure [4] was carried out for a study case of a regular
formed within the same HDL environment. It might be
digital PLL clock generator for system on a chip which
further used to explore and verify system-level perfor-
contains large synchronous digital fabric accompanied
mance which would be too complex to handle by an ana-
with mixed-signal circuitry like data converters. On
log simulation. After the target specifications are met,
the account of a fairly relaxed application in which the
portions of the system’s logic can be synthesized from
absolute jitter is the key metric, a bang-bang type-II
library cells. This eliminates the necessity to use other
second-order integer-N digital PLL of Fig. 5 was se-
tools and may dramatically accelerate the design cycle.
lected. To further alleviate demands on the DCO’s fre-
quency resolution a MASH 1-1 digital ΔΣ modulator Acknowledgements
was used as fractional three-bit dithering signal.
System-level digital PLL specifications also included: The authors would like to thank and acknowledge all
valuable contributions of the students, faculty, staff and
• fREF = 125 MHz – input reference clock frequency;
the sponsors of the Berkeley Wireless Research Center.
• fOUT = 2 GHz – synthesized output clock frequency;
with RMS absolute and period jitter values below 1 ps. References
The above clock synthesizer requirements can be sat- [1] R. B. Staszewski and P. T. Balsara, All-Digital Frequency
isfied with DCO oscillating frequency gain of approxi- Synthesizer in Deep-Submicron CMOS. Wiley, Sep. 2006.
mately KF = 3.14 MHz/bit which @2 GHz translates to [2] A. Musa, W. Deng, T. Siriburanon, M. Miyahara, K. Okada,
and A. Matsuzawa, “A compact, low-power and low-jitter
period sensitivity of KT = 0.785 ps/bit. These numbers dual-loop injection locked PLL using all-digital PVT calibra-
can be even achieved [5] with a ring-based oscillator. tion,” IEEE Journal of Solid-State Circuits, vol. 49, no. 1,
The rest of the sub-blocks in this DPLL are described pp. 50–60, Jan. 2014.
[3] W. Deng, D. Yang, T. Ueno, S. Kondo, K. Okada, and
on a behavior RTL, synthesized from it and automati- A. Matsuzawa, “A fully synthesizable all-digital PLL with
cally placed & routed in a well-established digital flow. interpolative phase coupled oscillator, current-output DAC,
With the free running DCO period jitter of ≈ 0.12 ps and fine-resolution digital varactor using gated edge injection
technique,” IEEE Journal of Solid-State Circuits, vol. 50,
and the corner knee frequency fc = 1 MHz, which are no. 1, pp. 68–80, Jan. 2015.
obtained from SPICE simulations, the fully equipped [4] G. Marucci, S. Levantino, P. Maffezzoni, and C. Samori,
“Analysis and design of low-jitter digital bang-bang phase-
DCO model is built. This model is used along-side HDL locked loops,” IEEE Transactions on Circuits and Systems
description of the remaining DPLL modules in an event- I: Regular Papers, vol. 61, no. 1, pp. 26–36, Jan. 2014.
driven simulator for system optimization & verification. [5] J. A. Tierno, A. V. Rylyakov, and D. J. Friedman, “A wide
power supply range, wide tuning range, all static CMOS all
The ability of achieving the frequency and phase lock digital pll in 65 nm SOI,” IEEE Journal of Solid-State Cir-
under all conditions is proved. DPLL’s phase noise in cuits, vol. 43, no. 1, pp. 42–51, Jan. 2008.
the sweet spot of the trade-off between random and [6] M. H. Perrott, “CppSim – a C++ system-level simulator,”
http://www.cppsim.com, accessed: 2017/10/14.
quantization noise is shown in Fig. 6. Integrated PSD of [7] R. Whittle, “DSP generation of the pink (1/f ) noise,”
the PLL yields jitter values that meet the specifications. www.firstpr.com.au/dsp/pink-noise, accessed: 2011/03/20.

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