0% found this document useful (0 votes)
56 views1 page

Low Power Vlsi Design For Iot Applications: Title: Authors: Abstract

This paper discusses a design methodology for low-power VLSI circuits tailored for IoT applications, addressing the increasing demand for energy-efficient devices. By employing techniques such as clock gating, voltage scaling, and power-domain partitioning, the proposed architecture achieves a 20% reduction in power consumption without sacrificing performance. The findings suggest that these low-power techniques are effective for various IoT applications, with future work aimed at further optimization for specific use cases.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
56 views1 page

Low Power Vlsi Design For Iot Applications: Title: Authors: Abstract

This paper discusses a design methodology for low-power VLSI circuits tailored for IoT applications, addressing the increasing demand for energy-efficient devices. By employing techniques such as clock gating, voltage scaling, and power-domain partitioning, the proposed architecture achieves a 20% reduction in power consumption without sacrificing performance. The findings suggest that these low-power techniques are effective for various IoT applications, with future work aimed at further optimization for specific use cases.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 1

Title: Low Power VLSI Design for IoT Applications

Authors: Pandu Reddy, Dr. A. B. Sharma (Supervisor)

Abstract:
The rapid growth of the Internet of Things (IoT) has resulted in a
significant increase in the demand for energy-efficient devices. This paper
presents a design methodology for low-power VLSI circuits aimed at IoT
applications. Through the application of power-aware techniques such as
clock gating, voltage scaling, and power-domain partitioning, we have
developed an architecture that reduces power consumption by 20%
without compromising performance.

Introduction:
In this paper, we explore the challenges faced by IoT devices, particularly
the need for low power consumption. As IoT devices are often battery-
operated, optimizing power efficiency is paramount to their functionality.
The work presented here provides a comprehensive approach to
minimizing power dissipation in VLSI circuits, including techniques for
voltage and frequency scaling.

Conclusion:
Our findings indicate that the proposed low-power techniques provide
substantial energy savings, making the architecture suitable for a wide
range of IoT applications. Future work will focus on further optimizing
these designs for specific IoT use cases.

You might also like