Roll Number:__________________________

Thapar Institute of Engineering & Technology, Patiala

Department of Computer Science and Engineering
MID SEMESTER EXAMINATION
B. E. (Third Year): Semester-VI (2023/24) Course Code: UCS617
(COE) Course Name: Microprocessor Based Systems Design
Date: March 17, 2024 Time: 11:00 AM – 1:00 PM
Duration: 2 Hours, M. Marks: 25 Name of Faculty: ANJ, MJU, AAS, SMV
Note: Attempt all questions in a proper sequence with justification. Assume missing data, if any, suitably.

Q. No. Questions Marks CO BL

Q1(a) Consider the following segments of the 8085-assembly language program stored at memory (2+2) CO2 L4
locations C000H for part I and E000H for part II and answer the questions given below:
(I) Memory (II) Memory
Instruction Instruction
Location Location
C000H LXI SP, EFFFH E000H MVI A, CFH
C003H CALL 9400H E002H MVI B, E2H
..... E004H ADD B
9400H LXI H, 3CF4H E005H DAA
9403H PUSH PSW E006H ANI E7H
9404H SPHL E008H STC
9405H POP PSW E009H RAL
9406H RET E00AH RST 5
On completion of RET instruction, what is the Write the content of the accumulator
content of the stack pointer? Also, write the and flag register after the execution of
value of the stack pointer after the execution of each instruction.
every instruction.
Q1(b) Differentiate between maskable and non-maskable interrupts. Write an assembly language (2+1) CO2 L3
program to update the content of the accumulator using SIM instruction that will only unmask and
reset RST 7.5.
Q2 Design the timing diagram and also write the values at each machine cycle as below mentioned (6) CO1 L6
table for the following instruction:
7FFF H: XRA M (M: 8AEF H, 8AEF: 9F, A: B9 and Opcode for XRA M: AEH)
A0-A7 D0-D7 A8-A15 ALE ̅
𝐼𝑂/M S0, S1 ̅̅̅̅
𝑅𝐷 ̅̅̅̅̅
𝑊𝑅 A (Accumulator)

Q3 A program developed in assembly language for the 8085-microprocessor for the Delay subroutine (1+2+3) CO2 L4
is given below:
Delay: LXI B, Count 2
Loop 2: LXI D, Count 1
Loop 1: DCX D
MOV A, E
ORA D
JNZ Loop 1
DCX B
MOV A, C
ORA B
JNZ Loop 2
RET
By analysing the program, calculate:
a. The total number of T-states required to execute the program.
b. The time taken by the processor in nanoseconds for one T-state, when the crystal
oscillator frequency is 6 MHz.
c. Calculate the maximum amount of delay caused by the execution of this program by
considering the maximum count value for Count 1 and Count 2. Write your final
maximum delay in the Hours and Minutes format (Eg. __Hours and ___Minutes).
Q4(a) Suppose the segment registers, CS, SS, DS, ES of 8086 microprocessor contains segment address (4) CO1 L3
A100H, B200H, C300H, and D400H respectively and offset register contains the offset address
BX = 348BH, SI = E432H, DI = 6D79H, SP = 8421H, and BP = 0798H. Calculate the offset
address and physical memory address for each instruction given below from where the destination
registers will retrieve the data.
a. MOV AL, [SP-6H]
b. MOV DL, [BX+DI+10H]
c. MOV AX, [BP+SI]
d. MOV DX, [SP+DI-200H]
Q4(b) Discuss the following pins for 8086 microprocessor: (2) CO1 L5
i. MN / MX ii. BHE

Blooms's Level wise Marks

Distribution

L1
0%
24% L2
28%
L3
8% L4
L5
40%
L6

Course Outcome Wise Marks Distribution

14
12
10
8
6
4
2
0
CO1 CO2 CO3 CO4

Marks