CA Project 1 Report
李佳恩 B07902096
1. Module Explanation
Control
Control module reads Op, NoOp as input, and output ALUOp, ALUSrc,
RegWrite, MemtoReg, MemRead, MemWrite, and Branch.
If NoOp_i is true : set all the output to zero as initiation.
if NoOp_i is false: set the value of the output according to the Op_i
Opcode)
ALU Control
ALU Control module reads funct, ALUOp as input, and output ALUCtrl.
This module read the value of funct and ALUOp, to know what operator it is.
Then, it set the ALUCtrl value to the corresponding value.
ALU
ALU module reads data1, data2, ALUCtrl as input, and output the calculation
answer as output. First, read the value of ALUCtrl to get the operator of
instruction, then we calculate data1 and data2, and output the answer of it.
Adder
Adder module reads data1_i and data2_i as input and outputs data_o (the sum
of both the inputs). This module used in:
Add_PC to calculate the next program counter in general.
Add_PC_Branch: to calculate the next program counter if branch.
MUX32
This module reads data1, data2, and select bit as input, then output the chosen
data. We select data1 or data 2 to become the output according the value of
CA Project 1 Report 1
select bit. If the bit is 0, then output the value of data1. Otherwise, output the
value of data2.
MUX2
MUX2 module has 4 inputs: data0_i, data1_i, data2_i, forward_i and data_o as
the output. This module will decides:
forward_i = 00 data_o = data0_i. (no need to forward, read data from
register)
forward_i = 01 data_o = data1_i. (forward the result from MEM/WB
forward_i = 01 data_o = data2_i. (forward the result from EX/MEM
Imm_Gen
Imm_Gen module reads all bits of instruction as input and output the immediate
part of this instruction. It will proceeds the different instruction type and get
the immediate value of the instruction and then it will extend it to 32 bits as the
output
Hazard_Detection
This module reads data1_i, data2_i, data3_i, and MemRead_i as the input. then
it will outputs PCWrite_o, Stall_o and NoOp_o.
As we know, Hazard happens when we have to do memory read and either the
address of RS1 or RS2 in the ID/EX is the same as the address of RD in the
EX/MEM stage.
If hazard is detected, then sends signal not to update PCWrite_o = 0, do Stall
Stall_o = 1 and give no operation signal NoOp_o = 1
else, sends signal to update PC PCWrite_o = 1 ), don't stall , and don't give
NoOp signal NoOp_o = 0
Forwarding_Unit
Forward Unit reads MemRegWrite i, MemRd i, WBRegWrite i, WBRd i, EXRs1 i,
EXRs2 i as inputs, and outputs ForwardA o and ForwardB o.
We determine whether there exists EX hazard or MEM-hazard by checking the
input values. The default value of ForwardA o and ForwardB o are two-bit
CA Project 1 Report 2
zero(00). If the inputs satisfy EX-hazard’s condition, the output will be 10. If the
inputs satisfy MEM-hazard’s condition, the output will be 01.
Register_IFID
The module has five inputs, clk_i, Stall_i, Flush_i, PC_i, instr_i, and two outputs
PC_o, instr_o.
On every clock edge, if the value of Stall i is 1, which means we have to stall for
a cycle, we let PC o equals to 32-bit zero while instr o remain unchanged.
If there is no need of stalling, PC o equals to PC i, while the value of instr_o
depends on Flush i. If Flush_i equals to 1, which means that we have to jump to
the branching address.
As a result, we let instr o equals to 32-bit zero and wait for the next cycle.
Otherwise, instr_o is equal to instr_i.
Register_IDEX
IDEX passes down control signals, register data, immediate, and instructions.
On every clock edges, we update every output by the corresponding input
values.
Register_EXMEM
EXMEM passes down some of the control signals, ALU result, memory write
data address, and rd address. On every clock edges, we update every output
by the corresponding input values.
Register_MEMWB
MEMWB passes down some of the control signals, ALU result, data memory
result and rd address. On every clock edges, we update every output by the
corresponding input values.
IF_Branch
This module reads data1_i, data2_i, and Branch_i as input, and outputs data o.
We use compare (a temporary register) to represent the value in data1_i and
data2_i are the same 1 if same, 0 if not). Then calculate data o = compare &
Branch_i. This module is used to check either we have to do branch in the next
cycle.
CA Project 1 Report 3
CPU
CPU connects all of the modules inside this project.
TestBench
Initialize the value of all registers used in the pipeline latch, changed the signal
to count flush.
CPU.If_Branch_data_o used to determine if we have to do branch. If so, do the
flush
2. Difficulties Encountered and Solutions in This
Project
Lots of Modules that should be written, and cause some bugs to the
program
When the testData Changed, I spent quiet a lot of time to debug it, until I
realise we just need to add some Registers and Data Memory initialization
to the testbench
Stall: in IFID module, at first i assign 0 to instr_o if we have to stall, but in
the end i realise the value of instr_o should not be changed.
3. Development Environment
OS MacOS, NTU CSIE Workstation
Compiler: iverilog
CA Project 1 Report 4
