Ain Shams University

Faculty of Engineering

Washing Machine Controller

Electronic Design Automation

CSE 312

Presented to:
DR. Eman El Mandouh
ENG. Abdelrahman Shereif

Presented by:
Moaz Mohamed Zakaria 22p0307
Seif elhusseiny 22p0215
Omar walid 22p0166
Ibrahim Amr Mohamed 19p2223
Osama lasheen 19p6937

Ahmed Mohamed Alamin

22p0137
Ali Khaled Elemam 22p0260
 • Table of Contents

Proposed Design Specification.............................................................................................. 3

Objective of the Project....................................................................................................... 3
System Overview................................................................................................................. 3
FSM State Diagram ................................................................................................................ 5
State Transitions.................................................................................................................. 5
FSM Diagram ....................................................................................................................... 7
Design RTL Code .................................................................................................................... 8
RTL Components ................................................................................................................ 8
Code Organization .............................................................................................................. 9
Code Snippets ................................................................................................................... 10
Verification Plan .................................................................................................................... 16
Test Scenarios ................................................................................................................... 16
Code Coverage.................................................................................................................. 17
Assertion............................................................................................................................. 17
Test Bench Code................................................................................................................... 19
Simulation Waveform Snippets ........................................................................................... 25
Proposed Design Specification

Objective of the Project

The primary objective of this project is to design and implement a
Washing Machine Controller using Verilog, adhering to the following
key functionalities:
1. Automate washing cycles based on the selected mode (Mode 1,
Mode 2, or Mode 3).
2. Support multiple washing states, including Idle, Ready, Prewash,
Soak, Wash, Rinse, Spin, and Dry.
3. Enable precise timing for each stage, customized to the load of the
clothes.
4. Ensure safety through features such as pause when the lid is
open and reset when power is off or the process is canceled.
5. Indicate the machine's current state and completion of the washing
process via output signals.
This project aims to provide an efficient and functional digital design that
simulates the behavior of a real-world washing machine controller.

System Overview
The washing machine controller is designed as a finite state machine
(FSM) with well-defined states and transitions. The system operates in
various modes depending on the weight of the laundry, which is
selected using input signals (i_mode_1, i_mode_2, i_mode_3).
Key system components:

• Input Signals:

▪ i_clk: Clock signal for timing operations.

▪ i_power: Power signal to enable or disable the system.
▪ i_cancel: Cancel signal to reset the process.
▪ i_lid: Detects if the lid is open, pausing the process if true.
▪ Mode signals (i_mode_1, i_mode_2, i_mode_3) to select the
washing cycle based on load.
 • States:

▪ IDLE: Waiting for the user to power on and select a mode.

▪ READY: System ready to start the washing process.
▪ PREWASH: Initial cleaning cycle.
▪ SOAK: Allowing detergent to penetrate the fabrics.
▪ WASH: Main cleaning stage.
▪ RINSE: Removing detergent and residues.
▪ SPIN: Extracting excess water from clothes.
▪ DRY: Final drying process.

• Output Signals:
The controller generates outputs (o_idle, o_ready, o_prewash,
etc.) indicating the current state and auxiliary outputs such as:

▪ o_dooropen: Indicates when the door is open or ready for

access.
▪ o_waterinlet: Active during water-reliant stages (Soak, Wash,
Rinse).
▪ o_done: Signifies the end of the washing process.

• Safety and Control Features:

▪ Pause functionality when the lid is open during any stage.

▪ Reset functionality on power loss or cancel command.
▪ Timers for each stage, configurable based on the selected
mode.

The design is verified using simulation testbenches, ensuring that the

controller adheres to the specified functionality under various operating
conditions.
FSM State Diagram
State Transitions
The washing machine controller operates as a Finite State Machine
(FSM) with well-defined states and transitions. The transitions between
states are determined by input signals and system conditions. Below is a
description of the state transitions:

• Idle State (IDLE):

▪ The system starts in the IDLE state.

▪ Transition to READY occurs when the i_power signal is active
and a valid mode (i_mode_1, i_mode_2, or i_mode_3) is
selected.

• Ready State (READY):

▪ From READY, the machine begins the washing process,

transitioning to PREWASH.
▪ If i_lid is open, the system pauses and remains in this state until
the lid is closed.

• Prewash State (PREWASH):

▪ After completing the prewash cycle, the machine transitions to

SOAK.
▪ If i_cancel or i_power is deactivated, the system transitions
back to IDLE.

• Soak State (SOAK):

▪ After soaking, the machine transitions to the WASH state.

• Wash State (WASH):

▪ After the washing process is complete, the machine transitions

to RINSE.
• Rinse State (RINSE):

▪ Upon completing the rinse cycle, the machine transitions to the

SPIN state.

• Spin State (SPIN):

▪ After extracting water, the system transitions to the DRY state.

• Dry State (DRY):

▪ The machine completes the cycle in the DRY state,

transitioning back to IDLE when the process is done.
▪ The o_done signal is activated to indicate the end of the cycle.

• Special Transitions:

▪ If i_lid is open during any stage, the system pauses and

resumes the current state when the lid is closed.
▪ If i_cancel is activated at any point, the system resets to IDLE.
FSM Diagram
Design RTL Code

RTL Components

• Registers

▪ prewashcounter, soakcounter, washcounter, rinsecounter,

spincounter, drycounter : Counters for timers associated with
each washing stage.
▪ prewash_done, soak_done, wash_done, rinse_done,
spin_done, dry_done : Flags to indicate when a stage
completes.

• Wires

▪ prewash_up, soak_up, wash_up, rinse_up, spin_up, dry_up:

Indicate when a stage's timer should increment.
▪ prewash_pause, soak_pause, wash_pause, rinse_pause,
spin_pause, dry_pause: Indicate when timers should pause due

• Sequential logic

▪ Implements stage-specific timers that increment, reset, or pause

based on stage completion and lid status.

• Combinational logic

▪ Determines the next state (NS) based on PS, inputs, and stage
completion flags
▪ Evaluates stage completion conditions based on the mode and
counter values.
Code Organization

• Inputs:
▪ Control inputs (i_clk, i_start, i_cancel, i_power, i_lid) and mode
selectors (i_mode_1, i_mode_2, i_mode_3).

• Outputs:
▪ State indicators (o_idle, o_ready, etc.).
▪ Functional outputs (o_dooropen, o_waterinlet, o_done).

• States:
▪ The FSM transitions through washing stages: IDLE → READY
→ PRE_WASH → SOAK → WASH → RINSE → SPIN → DRY
→ IDLE

• State Transition Conditions:

▪ Stage completion
▪ Inputs like i_cancel, i_power, and i_lid.
▪ Selected modes (i_mode_1, i_mode_2, i_mode_3).

• Timers:
▪ Each stage has a dedicated timer (<stage>counter) that
increments when the stage is active and pauses if the lid is
open.
▪ Completion is flagged based on the counter value and selected
mode.

• Outputs
▪ Outputs like o_idle, o_ready, and o_waterinlet are directly tied
to FSM states or stage-specific conditions.

• Timer Logic:
▪ Reset when the stage begins or completes.
▪ Increment when active.
▪ Pause when the lid is open .
Code Snippets

• Inputs and outputs

• States

• Registers
• State Logic
• Timer
• Output Logic
Verification Plan

Test Scenarios

1) Basic Operation (Mode 1): Starts the washing machine with MODE 1.

2) Multiple Modes (Mode 1 & 2): Tests behavior when MODE 1 and MODE
2 are both selected.

3) Heavy Load (Mode 3):Starts the machine with MODE 3.

4) No Mode Selection: Tests starting the machine without selecting any

mode.

5) Cancellation During Operation: Cancels the washing process mid-cycle.

6) Lid Open During Operation: Simulates opening and closing the lid during
operation with MODE 3.

7) Power Off During Operation: Turns off and then on the power during
MODE 1.

8) Cancel and Resume: Activates and deactivates the cancel signal.

9) Start With Lid Open: Tests starting the machine while the lid is open.

10) Open Lid After Canceling: Cancels the process and then opens the lid.

11) All Modes Enabled: Simulates a scenario where all modes are selected
simultaneously.

12) Immediate Cancelation: Starts the machine and cancels immediately.

13) Randomized Scenarios(13-20): Use randomize_inputs or

randomize_running_inputs to generate random input sequences, simulating
unpredictable real-world conditions.
Code Coverage

A coverage report was made containing all types of coverage including

branch, condition, FSM, statement and toggle coverage.
This coverage counts the transitions between each state and checks if some
states are inaccessible.
The coverage report is attached in the zip folder .

Assertion

• Transition Assertions

▪ Assert that state transitions happen correctly based on

conditions.
▪ Ensures that when the machine is powered and in IDLE, it
transitions to READY when no cancel or lid is open.

• Output Assertions

▪ Water Inlet Assertions: Ensures water is ON only during active

states like SOAK, WASH, and RINSE.
 ▪ Door Assertions: Ensures the door (o_dooropen) opens only in
valid states (e.g., IDLE, after drying).

• Cancellation Assertions

▪ Verify that i_cancel

▪ always forces a transition to IDLE
Test Bench Code

Signals Declaration (wires , reg)

module Declaration (washing machine Controller)

Modes declaration

Displays to track the scenario part 1

Part2

Part 3
Part 4

Test scenarios (scenario 1 & scenario 2)

Scenario 3 & Scenario 4 Test

Scenario 5 & 6 & 7 test

Scenario 8 & 9 Test

Scenario 10 & Scenario 11 Test

Scenario 12 Test and code Termination

Simulation Waveform Snippets