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XGMII Interface Update: IEEE 802.3ae

The document provides an update on the 10 Gigabit Media Independent Interface (XGMII) for Ethernet, detailing its goals, assumptions, and electrical characteristics. It outlines the coding scheme, including the use of embedded delimiters and control bits, as well as timing specifications for data transmission. The proposal is deemed stable, with references to the EIA/JEDEC SSTL_2 standard for electrical specifications and a call for further discussion on timing proposals.

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32 views12 pages

XGMII Interface Update: IEEE 802.3ae

The document provides an update on the 10 Gigabit Media Independent Interface (XGMII) for Ethernet, detailing its goals, assumptions, and electrical characteristics. It outlines the coding scheme, including the use of embedded delimiters and control bits, as well as timing specifications for data transmission. The proposal is deemed stable, with references to the EIA/JEDEC SSTL_2 standard for electrical specifications and a call for further discussion on timing proposals.

Uploaded by

redstar829
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
You are on page 1/ 12

IEEE P802.

3ae
10 Gigabit Ethernet Task Force

XGMII Update

La Jolla, CA
11-July-2000
Howard Frazier - Cisco Systems

IEEE 802.3ae
XGMII Update Page 1 of 12
10 Gigabit Ethernet
hmf 11-July-2000
Goals and Assumptions

n Allow multiple PHY variations


n Provide a convenient partition for implementers
n Provide a standard interface between MAC and PHY
n Reference industry standard electrical specifications

IEEE 802.3ae
XGMII Update Page 2 of 12
10 Gigabit Ethernet
hmf 11-July-2000
Interface Locations

XGMII XAUI

TXC
TXD

XGXS

PMA

PMD
PCS
MAC RS 36 XGXS
RXC
RXD
36
PHY

MDC
Mgmt
MDIO

Management

IEEE 802.3ae
XGMII Update Page 3 of 12
10 Gigabit Ethernet
hmf 11-July-2000
10 Gigabit Media Independent Interface

n 32 data bits, 4 control bits, one clock, for transmit


n 32 data bits, 4 control bits, one clock, for receive
n Dual Data Rate (DDR) signaling, with data and control
driven and sampled on both rising edge and falling edge of clock

Clock

Control

Data[A/B] Data[A] Data[B]

n 32 bit data paths are divided into four 8 bit “lanes”, with one
control bit for each lane

IEEE 802.3ae
XGMII Update Page 4 of 12
10 Gigabit Ethernet
hmf 11-July-2000
10 Gigabit Media Independent Interface - Coding

n Use embedded delimiters rather than discrete signals


n Control bit (C) is “1” for delimiter and special characters
n Control bit (C) is “0” for normal data characters
n Delimiter and special character set includes:
n Idle, Start, Terminate, Error
n Delimiters and special characters are distinguished by the value
of the 8 bit data lane when the corresponding control bit is “1”
n Data (d) symbols are striped on lane 1, lane 2, lane 3, lane 0, etc.
n Frames (packets) may be any number of symbols in length
subject to minFrameSize and maxFrameSize

IEEE 802.3ae
XGMII Update Page 5 of 12
10 Gigabit Ethernet
hmf 11-July-2000
10 Gigabit Media Independent Interface - Coding

n Idle (I) is signaled


n during the Inter-Packet Gap
n when there is no data to send
n Start (S) is signaled
n for one byte duration at the beginning of each packet
n always on lane 0
n Terminate (T) is signaled
n for one byte duration at the end of each packet
n may appear on any lane
n Error (E) is signaled
n when an error is detected in the received signal
n when an error needs to be forced into the transmitted signal

IEEE 802.3ae
XGMII Update Page 6 of 12
10 Gigabit Ethernet
hmf 11-July-2000
10 Gigabit Media Independent Interface - Coding

Shorthand Name Code Point Code Point


(Control) (Data)
I Idle 1 0x07
S Start 1 0xFB
T Terminate 1 0xFD
E Error 1 0xFE
d Data 0 0x00 - 0xFF

IEEE 802.3ae
XGMII Update Page 7 of 12
10 Gigabit Ethernet
hmf 11-July-2000
10 Gigabit Media Independent Interface - Example

clk
C0

D<0:7> I S d d d d d d d d d d I I I
p p f

C1

D<8:15> I d
p
d
p
d d d d d d d d
f
T I I I

C2

D<16:23> I d
p
d
p
d d d d d d d d
f
I I I I

C3

D<24:31> I d
p
d
s
d d d d d d d d
f
I I I I

IEEE 802.3ae
XGMII Update Page 8 of 12
10 Gigabit Ethernet
hmf 11-July-2000
10 Gigabit Media Independent Interface -
Electrical Characteristics

n Use Stub Series Terminated Logic for 2.5 Volts


n SSTL_2
n EIA/JEDEC Standard EIA/JESD8-9
n Class I (8 ma) output buffers

VDDQ Symbol Parameter Min Typ Max

VIH(ac) VDDQ Supply Voltage 2.3 2.5 2.7

VIH(dc) VREF Reference Voltage 1.15 1.25 1.35


VTT Termination Voltage VREF-0.04 VREF VREF+0.04
VREF VIH(dc) dc input logic high VREF+0.18 VDDQ+0.3
VIL(dc) dc input logic low -0.3 VREF-0.18
VIL(dc)
VIH((ac) ac input logic high VREF+0.35
VIL(ac)
VSS VIL(ac) ac input logic low VREF-0.35

IEEE 802.3ae
XGMII Update Page 9 of 12
10 Gigabit Ethernet
hmf 11-July-2000
10 Gigabit Media Independent Interface -
Circuit Topology Example

VTT

VDDQ 50 Ohms

Z=50 Ohms
RS = 25 Ohms
VREF

IEEE 802.3ae
XGMII Update Page 10 of 12
10 Gigabit Ethernet
hmf 11-July-2000
10 Gigabit Media Independent Interface - Timing

VIH_AC(min)

Clock
VIL_AC(max)

Data VIH_AC(min)

or
Control VIL_AC(max)

tsetup

thold

Symbol Driver Receiver Units


t setup 960 480 ps
t hold 960 480 ps

IEEE 802.3ae
XGMII Update Page 11 of 12
10 Gigabit Ethernet
hmf 11-July-2000
Summary

n The XGMII coding proposal is stable


n The EIA/JEDEC SSTL_2 standard can be referenced for the
XGMII electrical specification
n The timing proposal presented herein is a starting point
for further discussion

IEEE 802.3ae
XGMII Update Page 12 of 12
10 Gigabit Ethernet
hmf 11-July-2000

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