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The document provides an overview of FIFO (First in First Out) design, detailing both synchronous and asynchronous FIFO implementations using Verilog. It explains the operations of writing and reading data, the conditions for empty and full states, and includes sample Verilog code for implementation. Additionally, it describes the test bench setup for writing and reading operations, including data validation and simulation data dumping.

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HARDIK UPRETI
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14 views11 pages

Presentation 3

The document provides an overview of FIFO (First in First Out) design, detailing both synchronous and asynchronous FIFO implementations using Verilog. It explains the operations of writing and reading data, the conditions for empty and full states, and includes sample Verilog code for implementation. Additionally, it describes the test bench setup for writing and reading operations, including data validation and simulation data dumping.

Uploaded by

HARDIK UPRETI
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as KEY, PDF, TXT or read online on Scribd
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FIFO Design

Synchronous and Asynchronous FIFO Design using


Verilog

Hardik Upreti
FIFO
What is FIFO?

FIFO stands for First in First


Out
It is a buffer that is used for
synchronization and
handshaking between
modules.
FIFO Depth: The number of
slots or rows in FIFO.
Width of FIFO: The number of
bits that can be stored in
each slot or row.
Synchronous FIFO

Data Read and Write use the same clock frequency.


Used with high clk frequency to support high speed systems.
Synchronous FIFO
Operation: Write

FIFO stores the data at every posedge of the clock based on wr_en
signals till the FIFO is full.
Write pointer increments on every data write in FIFO memory.
Synchronous FIFO
Operation: Read

Data can be read at every posedge of the clk based on rd_en


signal till teh FIFO is empty.
The read pointer gets incremented on every data read form FIFO
memory.
Implementation of Synchronous FIFO

Width of write and read pointer = log2(FIFO Depth)


Empty Condition:
When wr_ptr == rd_ptr (read and write pointers jave the same
value)
Full Condition
Full condition means every FIFO slot is occupied.
But wr_ptr and rd_ptr are equal, how to identify empty or full
condition?
We keep last slot of FIFO intentionally empty hence the full condition
becomes wr_ptr = rd_ptr-1
Verilog Code for this Implementation

->DEPTH = 8, WIDTH = 8 Bit


->5 inputs:
clk,rst_n,w_en,r_en,data_in
->3 Outputs: data_out,full,empty
->Width of read and write pointers:
log2(Depth)
->Fifo declaration with depth 8 and
width of each slot = 8 bits
—->RESET FIFO Values using rst_n
signal (1st always block)
Verilog Code for this Implementation
—>Always Block 2: To write data into
FIFO
If write enable = 1 and full = 0
Non blocking assignment to fifo at w_ptr
location and Increment the w_ptr
—>Always Block 3: To Read data
from FIFO
Id read enable = 1 and empty = 0
Data_out <=fifo[r_ptr] and Increment
r_ptr by 1
—>Assign Statements
Test Bench
Initial Testbench

Wdata_q: is queu to
store data that gets
written into the FIFO
Wdata: Temporary
variable to hodl data
read from wdata_q

Instantiate the FIFO


module
Generate clock 10ns
period
Test Bench
Write Operation

Initialize
clk=0,rst_n=0,w_en=0,data_in=0
Line 22: wait for 10 clk cycles
Perform Write for 2 rounds, each of
30 cycles: i=0, waits for posedge
clk,write enable is toggled every
cycle(line 28)
If write enable is HIGH and
full=0(FIFO is not FULL), generate
random data and push it into the
queue.
Test Bench
Read Operation
Initializes CLK=0,rst_n=0,r_en=0
Wait for 20 cycles and deassert
reset_n=1
Perform read operation for 2
rounds each of 30 cycles.
Read enable is toggled every
second cycle.
Whne read enable is HIGH and
FIFO is not empty, read data
from FIFO.
Retrieve data from pop_front to
wdata.
Compare data_out with wdata
and print error if they don’t
match.
Dump the simulation data to a
VCD file.

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