MASTERING SYSTEMVERILOG
CONSTRAINTS: ADVANCED
QUESTIONS & INTERVIEW
GUIDE
IMPORTANT INTERVIEW QUESTIONS
CHALLENGING PROGRAMMING QUESTIONS
USEFUL INTERVIEW TIPS
Prasanthi Chanda
1. How can constrained randomization be used to verify an AXI
bus transaction generator?
To verify an AXI transaction generator, randomization ensures
diverse address, data, and burst sizes while maintaining
protocol compliance.
class AXI_Transaction;
rand bit [31:0] address;
rand bit [127:0] data;
rand int burst_size;
constraint addr_align { address % 4 == 0; } // Ensure 4-byte
alignment
constraint burst_range { burst_size inside {[1:16]}; } // AXI burst
sizes
endclass
This ensures address alignment and valid burst sizes during
testing.
2. How do you randomize an Ethernet frame while ensuring it
follows the minimum and maximum frame size requirements?
Ethernet frames should be randomized within valid length
constraints (64 to 1518 bytes).
class EthernetFrame;
rand bit [11:0] frame_size;
constraint valid_size { frame_size inside {[64:1518]}; }
endclass
This ensures only legal Ethernet frame sizes are generated.
3. How do you use SystemVerilog constraints to generate memory
accesses that avoid bank conflicts in an SDRAM controller?
Bank conflicts occur when multiple accesses target the same
bank simultaneously.
class SDRAM_Access;
rand bit [2:0] bank;
rand bit [12:0] row;
rand bit [9:0] column;
// Example restriction
constraint avoid_conflicts { !(bank == 3 && row == 100); }
endclass
This constraint prevents a specific bank-row combination that
causes conflicts.
4. How can you ensure that randomly generated UART transactions
do not exceed a specified baud rate?
Use a constraint to limit the baud rate.
class UART_Transaction;
rand int baud_rate;
constraint valid_baud { baud_rate inside {9600, 19200, 38400,
57600, 115200}; }
endclass
This ensures only supported baud rates are chosen.
5. How do you generate randomized test cases for a multi-core
processor ensuring each core executes different instructions?
Ensure instructions assigned to different cores are unique.
class MultiCoreTest;
rand bit [7:0] core0_instr, core1_instr;
constraint unique_instr { core0_instr != core1_instr; }
endclass
This prevents two cores from executing the same instruction.
6. How do you randomize SPI transactions while ensuring valid
clock polarity and phase settings?
Ensure only valid SPI mode settings (CPOL and CPHA) are
selected.
class SPI_Config;
rand bit cpol, cpha;
constraint valid_modes { (cpol == 0 && cpha inside {0, 1}) || (cpol
== 1 && cpha inside {0, 1}); }
endclass
This ensures only valid SPI clock settings are used.
7. How can constrained randomization be used to test a PCIe
transaction layer by generating valid TLP packets?
Generate packets with valid header types and payload lengths.
class PCIe_TLP;
rand bit [6:0] header_type;
rand bit [15:0] payload_length;
constraint valid_header { header_type inside {7'h00, 7'h20,
7'h40}; } // Memory, I/O, Config
constraint valid_length { payload_length inside {[4:4096]}; }
endclass
This ensures valid transaction layer packets (TLPs)
8. How do you generate random test cases for an I2C controller
ensuring proper START and STOP conditions?
Ensure a START is followed by address/data and ends with
STOP.
class I2C_Transaction;
rand bit start, stop;
constraint valid_sequence { start == 1 -> stop == 1; } // START
must have a STOP
endclass
This prevents protocol violations.
9. How do you randomize a cache coherence test such that no
two cores write to the same cache line simultaneously?
Ensure exclusive writes by different cores do not overlap.
class CacheTest;
rand bit [7:0] core_id;
rand bit [31:0] address;
constraint unique_write { !(core_id == 1 && address ==
32'hA0B0_C0D0); }
endclass
This avoids coherence conflicts.
10. How can constrained randomization be used to verify a RISC-
V instruction fetch unit?
Generate valid instruction addresses aligned to instruction word
size.
class RISC_V_IFU;
rand bit [31:0] pc;
constraint align { pc % 4 == 0; }
endclass
This ensures proper instruction alignment.
11. How do you generate test patterns for a DRAM refresh
controller ensuring refresh cycles occur within a specified time
window?
Ensure refresh cycles are constrained by timing rules.
class DRAM_Refresh;
rand int refresh_interval;
constraint timing { refresh_interval inside {[64:128]}; } // Within
valid refresh period
endclass
This enforces timing compliance.
12. How can you ensure that a set of randomly generated
Ethernet frame sizes maintains a specific distribution (e.g., 50%
minimum size, 30% mid-range, 20% maximum size)?
Use a dist constraint to enforce probability distribution.
class EthernetFrame;
rand bit [11:0] frame_size;
constraint frame_distribution {
frame_size dist {64 := 50, [500:1000] := 30, 1518 := 20};
}
endclass
This ensures controlled distribution of frame sizes.
13. How do you enforce a constraint where the sum of three
randomly generated operands does not exceed a 16-bit ALU's
maximum output?
class ALU_Operands;
rand bit [15:0] op1, op2, op3;
constraint sum_limit { op1 + op2 + op3 <= 16'hFFFF; }
endclass
Prevents overflow conditions.
14. How do you generate randomized cache eviction policies
ensuring at least one random policy is LRU?
class CachePolicy;
rand bit [2:0] policy;
constraint one_lru { policy inside {3'b000, 3'b001, 3'b010,
3'b011}; } // Ensure LRU (least recently used)
endclass
Guarantees LRU is always in the set.
15. How do you ensure randomly generated data packets always
have a valid CRC value?
class DataPacket;
rand bit [127:0] data;
rand bit [15:0] crc;
constraint valid_crc { crc == compute_crc(data); }
endclass
Ensures CRC consistency.
FINAL NOTE
Mastering SystemVerilog randomization and constraints is essential
for advanced verification roles.
HERE ARE SOME KEY TIPS TO EXCEL IN INTERVIEWS:
✅ Understand Constraint Propagation: Be ready to explain how
constraints affect random variable generation.
✅ Debugging Constraints: Know how to debug unsolvable
constraints using constraint_mode(0) and $display.
✅ Practical Applications: Always connect your answers to real-
world scenarios, like cache management, arbitration, or
memory access patterns.
✅ Performance Optimization: Be prepared to discuss constraint
solver efficiency and avoiding over-constraining.
✅ Hands-On Practice: Interviewers may ask you to write
constraints live—practice coding without syntax errors!
If you need further guidance or support, feel free to reach us out.
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