MC14013B

Dual Type D Flip-Flop

The MC14013B dual type D flip−flop is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Each flip−flop has independent Data, (D), Direct
Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary
outputs (Q and Q). These devices may be used as shift register http://onsemi.com
elements or as type T flip−flops for counter and toggle applications.

Features MARKING
DIAGRAMS
• Static Operation 14
• Diode Protection on All Inputs PDIP−14
P SUFFIX MC14013BCP
• Supply Voltage Range = 3.0 Vdc to 18 Vdc AWLYYWWG
CASE 646
• Logic Edge−Clocked Flip−Flop Design 1
• Logic state is retained indefinitely with clock level either high or
low; information is transferred to the output only on the 14
positive−going edge of the clock pulse SOIC−14
14013BG
D SUFFIX
• Capable of Driving Two Low−power TTL Loads or One Low−power
CASE 751A
AWLYWW
Schottky TTL Load Over the Rated Temperature Range
1
• Pin−for−Pin Replacement for CD4013B
• These Devices are Pb−Free, Halogen Free and are RoHS Compliant 14
• NLV Prefix for Automotive and Other Applications Requiring 14
TSSOP−14 013B
Unique Site and Control Change Requirements; AEC−Q100 DT SUFFIX ALYW G
Qualified and PPAP Capable CASE 948G G
1
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol Parameter Value Unit
14
VDD DC Supply Voltage Range −0.5 to +18.0 V SOEIAJ−14
F SUFFIX MC14013B
Vin, Vout Input or Output Voltage Range −0.5 to VDD + 0.5 V
ALYWG
(DC or Transient) CASE 965

Iin, Iout Input or Output Current ± 10 mA 1

(DC or Transient) per Pin

PD Power Dissipation, per Package 500 mW A = Assembly Location

(Note 1) WL, L = Wafer Lot
YY, Y = Year
TA Ambient Temperature Range −55 to +125 °C WW, W = Work Week
Tstg Storage Temperature Range −65 to +150 °C G or G = Pb−Free Package
(Note: Microdot may be in either location)
TL Lead Temperature 260 °C
(8−Second Soldering)
Stresses exceeding Maximum Ratings may damage the device. Maximum ORDERING INFORMATION
Ratings are stress ratings only. Functional operation above the Recommended See detailed ordering and shipping information in the package
Operating Conditions is not implied. Extended exposure to stresses above the dimensions section on page 2 of this data sheet.
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.

© Semiconductor Components Industries, LLC, 2012 1 Publication Order Number:

September, 2012 − Rev. 9 MC14013B/D
 MC14013B

TRUTH TABLE
Inputs Outputs
Clock† Data Reset Set Q Q
0 0 0 0 1
1 0 0 1 0
X 0 0 Q Q No
Change
X X 1 0 0 1
X X 0 1 1 0
X X 1 1 1 1
X = Don’t Care
† = Level Change

PIN ASSIGNMENT BLOCK DIAGRAM

QA 1 14 VDD 6

QA 2 13 QB S
5 D Q 1
CA 3 12 QB
RA 4 11 CB
DA 5 10 RB 3 C Q 2
R
SA 6 9 DB
4
VSS 7 8 SB
8

S
9 D Q 13

11 C Q 12
R
VDD = PIN 14
10
VSS = PIN 7

ORDERING INFORMATION
Device Package Shipping†
MC14013BCPG PDIP−14
25 Units / Rail
NLV14013BCPG* (Pb−Free)

MC14013BDG SOIC−14
55 Units / Rail
NLV14013BDG* (Pb−Free)

MC14013BDR2G SOIC−14
NLV14013BDR2G* (Pb−Free)
2500 Units / Tape & Reel
MC14013BDTR2G TSSOP−14
NLV14013BDTR2G* (Pb−Free)

MC14013BFG SOEIAJ−14 50 Units / Rail

MC14013BFELG (Pb−Free) 2000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.

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2
 MC14013B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ ÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
− 55_C 25_C 125_C
VDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol Vdc Min Max Min Typ (2) Max Min Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Voltage “0” Level VOL 5.0 − 0.05 − 0 0.05 − 0.05 Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin = VDD or 0 10 − 0.05 − 0 0.05 − 0.05
15 − 0.05 − 0 0.05 − 0.05

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Vin = 0 or VDD “1” Level VOH 5.0 4.95 − 4.95 5.0 − 4.95 − Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 9.95 − 9.95 10 − 9.95 −
15 14.95 − 14.95 15 − 14.95 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Voltage “0” Level

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
VIL Vdc
(VO = 4.5 or 0.5 Vdc) 5.0 − 1.5 − 2.25 1.5 − 1.5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VO = 9.0 or 1.0 Vdc) 10 − 3.0 − 4.50 3.0 − 3.0
(VO = 13.5 or 1.5 Vdc) 15 − 4.0 − 6.75 4.0 − 4.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VO = 0.5 or 4.5 Vdc) “1” Level VIH 5.0 3.5 − 3.5 2.75 − 3.5 − Vdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VO = 1.0 or 9.0 Vdc) 10 7.0 − 7.0 5.50 − 7.0 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VO = 1.5 or 13.5 Vdc) 15 11 − 11 8.25 − 11 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Drive Current IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 – 3.0 − – 2.4 – 4.2 − – 1.7 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOH = 4.6 Vdc) 5.0 – 0.64 − – 0.51 – 0.88 − − 0.36 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOH = 9.5 Vdc) 10 – 1.6 − − 1.3 – 2.25 − – 0.9 −
(VOH = 13.5 Vdc) 15 – 4.2 − − 3.4 − 8.8 − − 2.4 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOL = 0.4 Vdc) Sink IOL 5.0 0.64 − 0.51 0.88 − 0.36 − mAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOL = 0.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(VOL = 1.5 Vdc)
10
15
1.6
4.2
−
−
1.3
3.4
2.25
8.8
−
−
0.9
2.4
−
−

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Current Iin 15 − ± 0.1 — ± 0.00001 ± 0.1 − ± 1.0 mAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Input Capacitance Cin − − − − 5.0 7.5 − − pF
(Vin = 0)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Quiescent Current
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(Per Package)
IDD 5.0
10
−
−
1.0
2.0
−
−
0.002
0.004
1.0
2.0
−
−
30
60
mAdc

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 − 4.0 − 0.006 4.0 − 120

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ
Total Supply Current (3) (4) IT 5.0 IT = (0.75 mA/kHz) f + IDD mAdc
(Dynamic plus Quiescent, 10 IT = (1.5 mA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Per Package) 15 IT = (2.3 mA/kHz) f + IDD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
(CL = 50 pF on all outputs, all
buffers switching)
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL − 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.002.

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 MC14013B

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (5) (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic Symbol VDD Min Typ (6) Max Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Output Rise and Fall Time tTLH, ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTHL 5.0 − 100 200

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns 10 − 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns 15 − 40 80

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Propagation Delay Time tPLH ns
Clock to Q, Q tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns 5.0 − 175 350

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns 10 − 75 150
15 − 50 100
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Set to Q, Q

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 90 ns 5.0 − 175 350

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 42 ns 10 − 75 150
tPLH, tPHL = (0.5 ns/pF) CL + 25 ns 15 − 50 100

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset to Q, Q
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tPLH, tPHL = (1.7 ns/pF) CL + 265 ns 5.0 − 225 450

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
tPLH, tPHL = (0.66 ns/pF) CL + 67 ns 10 − 100 200
tPLH, tPHL = (0.5 ns/pF) CL + 50 ns 15 − 75 150
Setup Times (7)
ÎÎÎ tsu 5.0 40 20 − ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 20 10 −
−

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 15 7.5
Hold Times (7) th 5.0 40 20 − ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 10 20 10 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 15 7.5 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Width tWL, tWH 5.0 250 125 − ns
10 100 50 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 15 70 35 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Frequency fcl 5.0 − 4.0 2.0 MHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
10 − 10 5.0
15 − 14 7.0

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Clock Pulse Rise and Fall Time
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
tTLH
tTHL
5.0
10
−
−
−
−
−
−
15
5.0
ms

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 4.0
Set and Reset Pulse Width tWL, tWH − ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
5.0 250 125
10 100 50 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 15 70 35 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Removal Times trem ns
Set 5 80 0 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 10 45 5 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
15 35 5 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Reset 5 50 – 35 −
10 30 – 10 −

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
5. The formulas given are for the typical characteristics only at 25_C.
15 25 –5 −

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
7. Data must be valid for 250 ns with a 5 V supply, 100 ns with 10 V, and 70 ns with 15 V.

LOGIC DIAGRAM (1/2 of Device Shown)

S
C C Q

C C Q
C C

C C
C C
C
R

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 MC14013B

20 ns 20 ns
VDD
90%
D 50% 20 ns 20 ns
10% VSS VDD
tsu (H) tsu (L) 90%
20 ns SET OR 50%
th VDD RESET 10%
90% VSS
C 50% tw trem
10% 20 ns 20 ns
VSS 90% VDD
tWH tWL 50%
CLOCK 10%
1 VSS
fcl tPLH tw
tPLH tPHL
VOH tPHL
90% VOH
Q 50% Q OR Q 50%
10% VOL
VOL
tTLH tTHL
Inputs R and S low.

Figure 1. Dynamic Signal Waveforms Figure 2. Dynamic Signal Waveforms

(Data, Clock, and Output) (Set, Reset, Clock, and Output)

TYPICAL APPLICATIONS

n−STAGE SHIFT REGISTER

1 2 nth
D D Q D Q D Q Q

C Q C Q C Q

CLOCK

BINARY RIPPLE UP−COUNTER (Divide−by−2n)

1 2 nth
D Q D Q D Q Q

CLOCK C Q C Q C Q

T FLIP-FLOP

MODIFIED RING COUNTER (Divide−by−(n+1))

1 2 nth
D Q D Q D Q Q

C Q C Q C Q

CLOCK

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 MC14013B

PACKAGE DIMENSIONS

PDIP−14
CASE 646−06
ISSUE P

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14 8 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1 7 5. ROUNDED CORNERS OPTIONAL.

INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
F L C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
N C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
−T− J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
SEATING L 0.290 0.310 7.37 7.87
PLANE
K J M −−− 10 _ −−− 10 _
H G D 14 PL N 0.015 0.039 0.38 1.01
M
0.13 (0.005) M

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 MC14013B

PACKAGE DIMENSIONS

SOIC−14 NB
CASE 751A−03
ISSUE K

D A NOTES:
1. DIMENSIONING AND TOLERANCING PER
B ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
14 8 3. DIMENSION b DOES NOT INCLUDE DAMBAR
A3 PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
H E 4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
L 5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
1 7 DETAIL A
MILLIMETERS INCHES
0.25 M B M 13X b DIM MIN MAX MIN MAX
A 1.35 1.75 0.054 0.068
0.25 M C A S B S A1 0.10 0.25 0.004 0.010
A3 0.19 0.25 0.008 0.010
DETAIL A b 0.35 0.49 0.014 0.019
h
A X 45 _
D 8.55 8.75 0.337 0.344
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.019
M L 0.40 1.25 0.016 0.049
e A1
SEATING M 0_ 7_ 0_ 7_
C PLANE

SOLDERING FOOTPRINT*
6.50 14X
1.18
1

1.27
PITCH

14X
0.58

DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 MC14013B

PACKAGE DIMENSIONS

TSSOP−14
CASE 948G
ISSUE B

14X K REF NOTES:

1. DIMENSIONING AND TOLERANCING PER
0.10 (0.004) M T U S V S ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
N EXCEED 0.15 (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE
2X L/2 INTERLEAD FLASH OR PROTRUSION.
M INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
B 5. DIMENSION K DOES NOT INCLUDE
L DAMBAR PROTRUSION. ALLOWABLE
PIN 1
−U− N
DAMBAR PROTRUSION SHALL BE 0.08
IDENT. F (0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
1 7
DETAIL E CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
0.15 (0.006) T U S
A K DETERMINED AT DATUM PLANE −W−.
MILLIMETERS INCHES

ÉÉÉ
ÇÇÇ
−V− K1 DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200

ÇÇÇ
ÉÉÉ
B 4.30 4.50 0.169 0.177
J J1 C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
SECTION N−N G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C −W− K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
0.10 (0.004) L 6.40 BSC 0.252 BSC
M 0_ 8_ 0_ 8_
−T− SEATING D G H DETAIL E
PLANE

SOLDERING FOOTPRINT*

7.06

0.65
PITCH

14X 14X
0.36
1.26
DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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8
 MC14013B

PACKAGE DIMENSIONS

SOEIAJ−14
CASE 965
ISSUE B

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
14 8 LE MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
Q1 (0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
E HE M_ REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
1 7 L TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DETAIL P DAMBAR CANNOT BE LOCATED ON THE LOWER
Z RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
D TO BE 0.46 ( 0.018).

VIEW P MILLIMETERS INCHES

e A DIM MIN MAX MIN MAX
A --- 2.05 --- 0.081
c A1 0.05 0.20 0.002 0.008
b 0.35 0.50 0.014 0.020
c 0.10 0.20 0.004 0.008
D 9.90 10.50 0.390 0.413
b A1 E 5.10 5.45 0.201 0.215
e 1.27 BSC 0.050 BSC
0.13 (0.005) M 0.10 (0.004) HE 7.40 8.20 0.291 0.323
L 0.50 0.85 0.020 0.033
LE 1.10 1.50 0.043 0.059
M 0_ 10 _ 0_ 10 _
Q1 0.70 0.90 0.028 0.035
Z --- 1.42 --- 0.056

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