MCP2561/2

High-Speed CAN Transceiver

Features: • High ESD Protection on CANH and CANL, Meets
IEC61000-4-2 greater ±8 kV
• Supports 1 Mb/s Operation
• Available in PDIP-8L, SOIC-8L and 3x3 DFN-8L
• Implements ISO-11898-5 Standard Physical Layer
• Temperature ranges:
Requirements
- Extended (E): -40°C to +125°C
• Very Low Standby Current (5 µA, typical)
- High (H): -40°C to +150°C
• VIO Supply Pin to Interface Directly to
CAN Controllers and Microcontrollers with
1.8V to 5.5V I/O Description:
• SPLIT Output Pin to Stabilize Common Mode in The MCP2561/2 is a Microchip Technology Inc. second
Biased Split Termination Schemes generation high-speed CAN transceiver. It serves as an
• CAN Bus Pins are Disconnected when Device is interface between a CAN protocol controller and the
Unpowered physical two-wire CAN bus.
- An Unpowered Node or Brown-Out Event will The device meets the automotive requirements for
Not Load the CAN Bus high-speed (up to 1 Mb/s), low quiescent current,
• Detection of Ground Fault: electromagnetic compatibility (EMC) and electrostatic
- Permanent Dominant Detection on TXD discharge (ESD).
- Permanent Dominant Detection on Bus
Package Types
• Power-on Reset and Voltage Brown-Out
Protection on VDD and VIO Pin MCP2561 MCP2562
• Protection Against Damage Due to Short-Circuit PDIP, SOIC PDIP, SOIC
Conditions (Positive or Negative Battery Voltage) TXD 1 8 STBY TXD 1 8 STBY
• Protection Against High-Voltage Transients in VSS 2 7 CANH VSS 2 7 CANH
Automotive Environments
VDD 3 6 CANL VDD 3 6 CANL
• Automatic Thermal Shutdown Protection RXD 4 5 SPLIT RXD 4 5 VIO
• Suitable for 12V and 24V Systems
• Meets or exceeds stringent automotive design
MCP2561 MCP2562
requirements including “Hardware Requirements
3x3 DFN* 3x3 DFN*
for LIN, CAN and FlexRay Interfaces in Automo-
tive Applications”, Version 1.3, May 2012 TXD 1 8 STBY TXD 1 8 STBY
• High-Noise Immunity Due to Differential Bus VSS 2 EP 7 CANH VSS 2 EP 7 CANH
Implementation 9 VDD 3 9
VDD 3 6 CANL 6 CANL
RXD 4 5 SPLIT RXD 4 5 VIO

* Includes Exposed Thermal Pad (EP); see Table 1-2

MCP2561/2 Family Members

Device Feature Description
MCP2561 Split pin Common mode stabilization
MCP2562 VIO pin Internal level shifter on digital I/O pins
Note: For ordering information, see the “Product Identification System” section on page 27.

 2013 Microchip Technology Inc. DS25167B-page 1

MCP2561/2
Block Diagram
SPLIT(2) VIO(3) VDD

Digital I/O Thermal POR

VDD/2
Supply Protection UVLO

VIO

Permanent
TXD
Dominant Detect

Driver CANH
VIO and
Slope Control
CANL
Mode
STBY
Control

CANH
Wake-Up
LP_RX(1)
Filter
CANL

Receiver
RXD CANH
HS_RX
CANL

VSS
Note 1: There is only one receiver implemented. The receiver can operate in Low-Power or High-Speed mode.
2: Only MCP2561 has the SPLIT pin.
3: Only MCP2562 has the VIO pin. In MCP2561, the supply for the digital I/O is internally connected to VDD.

DS25167B-page 2  2013 Microchip Technology Inc.

 MCP2561/2
1.0 DEVICE OVERVIEW 1.1 Mode Control Block
The MCP2561/2 is a high-speed CAN, fault-tolerant The MCP2561/2 supports two modes of operation:
device that serves as the interface between a CAN • Normal
protocol controller and the physical bus. The
• Standby
MCP2561/2 device provides differential transmit and
receive capability for the CAN protocol controller, and These modes are summarized in Table 1-1.
is fully compatible with the ISO-11898-5 standard. It will
operate at speeds of up to 1 Mb/s. 1.1.1 NORMAL MODE
Typically, each node in a CAN system must have a Normal mode is selected by applying a low-level to the
device to convert the digital signals generated by a STBY pin. The driver block is operational and can drive
CAN controller to signals suitable for transmission over the bus pins. The slopes of the output signals on CANH
the bus cabling (differential output). It also provides a and CANL are optimized to produce minimal
buffer between the CAN controller and the high-voltage electromagnetic emissions (EME).
spikes that can be generated on the CAN bus by The high speed differential receiver is active.
outside sources.
1.1.2 STANDBY MODE
The device may be placed in Standby mode by
applying a high-level to the STBY pin. In Standby
mode, the transmitter and the high-speed part of the
receiver are switched off to minimize power
consumption. The low-power receiver and the wake-up
filter block are enabled in order to monitor the bus for
activity. The receive pin (RXD) will show a delayed
representation of the CAN bus, due to the wake-up
filter.

TABLE 1-1: MODES OF OPERATION

RXD Pin
Mode STBY Pin
LOW HIGH
Normal LOW Bus is dominant Bus is recessive
Standby HIGH Wake-up request is detected No wake-up request detected

1.2 Transmitter Function 1.4 Internal Protection

The CAN bus has two states: Dominant and CANH and CANL are protected against battery short-
Recessive. A Dominant state occurs when the circuits and electrical transients that can occur on the
differential voltage between CANH and CANL is CAN bus. This feature prevents destruction of the
greater than VDIFF(D)(I). A Recessive state occurs transmitter output stage during such a fault condition.
when the differential voltage is less than VDIFF(R)(I). The device is further protected from excessive current
The Dominant and Recessive states correspond to the loading by thermal shutdown circuitry that disables the
Low and High state of the TXD input pin, respectively. output drivers when the junction temperature exceeds
However, a Dominant state initiated by another CAN a nominal limit of +175°C. All other parts of the chip
node will override a Recessive state on the CAN bus. remain operational, and the chip temperature is low-
ered due to the decreased power dissipation in the
1.3 Receiver Function transmitter outputs. This protection is essential to
protect against bus line short-circuit-induced damage.
In Normal mode, the RXD output pin reflects the differ-
ential bus voltage between CANH and CANL. The Low
and High states of the RXD output pin correspond to the
Dominant and Recessive states of the CAN bus,
respectively.

 2013 Microchip Technology Inc. DS25167B-page 3

MCP2561/2
1.5 Permanent Dominant Detection 1.6 Power-On Reset (POR) and
The MCP2561/2 device prevents two conditions:
Undervoltage Detection
• Permanent dominant condition on TXD The MCP2561/2 has undervoltage detection on both
• Permanent dominant condition on the bus supply pins: VDD and VIO. Typical undervoltage thresh-
olds are 1.2V for VIO and 4V for VDD.
In Normal mode, if the MCP2561/2 detects an
extended Low state on the TXD input, it will disable the When the device is powered on, CANH and CANL
CANH and CANL output drivers in order to prevent the remain in a high-impedance state until both VDD and
corruption of data on the CAN bus. The drivers will VIO exceed their undervoltage levels. In addition,
remain disabled until TXD goes High. CANH and CANL will remain in a high-impedance state
if TXD is Low when both undervoltage thresholds are
In Standby mode, if the MCP2561/2 detects an reached. CANH and CANL will become active only
extended dominant condition on the bus, it will set the after TXD is asserted High. Once powered on, CANH
RXD pin to Recessive state. This allows the attached and CANL will enter a high-impedance state if the volt-
controller to go to Low-Power mode until the dominant age level at VDD or VIO drop below the undervoltage
issue is corrected. RXD is latched High until a levels, providing voltage brown-out protection during
Recessive state is detected on the bus, and the normal operation.
wake-up function is enabled again.
In Normal mode, the receiver output is forced to
Both conditions have a time-out of 1.25 ms (typical). Recessive state during an undervoltage condition. In
This implies a maximum bit time of 69.44 µs Standby mode, the low-power receiver is only enabled
(14.4 kHz), allowing up to 18 consecutive dominant bits when both VDD and VIO supply voltages rise above
on the bus. their respective undervoltage thresholds. Once these
threshold voltages are reached, the low-power receiver
is no longer controlled by the POR comparator and
remains operational down to about 2.5V on the VDD
supply (MCP2561/2). The MCP2562 transfers data to
the RXD pin down to 1V on the VIO supply.

1.7 Pin Descriptions

Table 1-2 describes the pinout.

TABLE 1-2: MCP2561/2 PINOUT

MCP2561 MCP2561 MCP2562 MCP2562
Symbol Pin Function
3x3 DFN PDIP, SOIC 3x3 DFN PDIP, SOIC
1 1 1 1 TXD Transmit Data Input
2 2 2 2 VSS Ground
3 3 3 3 VDD Supply Voltage
4 4 4 4 RXD Receive Data Output
5 5 — — SPLIT Common Mode Stabilization - MCP2561 only
— — 5 5 VIO Digital I/O Supply Pin - MCP2562 only
6 6 6 6 CANL CAN Low-Level Voltage I/O
7 7 7 7 CANH CAN High-Level Voltage I/O
8 8 8 8 STBY Standby Mode Input
9 — 9 — EP Exposed Thermal Pad

DS25167B-page 4  2013 Microchip Technology Inc.

 MCP2561/2
1.7.1 TRANSMITTER DATA 1.7.9 STANDBY MODE INPUT PIN (STBY)
INPUT PIN (TXD) This pin selects between Normal or Standby mode. In
The CAN transceiver drives the differential output pins Standby mode, the transmitter, high speed receiver and
CANH and CANL according to TXD. It is usually SPLIT are turned off, only the low power receiver and
connected to the transmitter data output of the CAN wake-up filter are active. STBY is connected to an
controller device. When TXD is Low, CANH and CANL internal MOS pull-up resistor to VDD or VIO, in the
are in the Dominant state. When TXD is High, CANH MCP2561 or MCP2562, respectively. The value of the
and CANL are in the Recessive state, provided that MOS pull-up resistor depends on the supply voltage.
another CAN node is not driving the CAN bus with a Typical values are 660 k for 5V, 1.1 M for 3.3V and
Dominant state. TXD is connected to an internal pull-up 4.4 M for 1.8V
resistor (nominal 33 k) to VDD or VIO, in the MCP2561
or MCP2562, respectively. 1.7.10 EXPOSED THERMAL PAD (EP)
It is recommended to connect this pad to VSS to
1.7.2 GROUND SUPPLY PIN (VSS) enhance electromagnetic immunity and thermal
Ground supply pin. resistance.

1.7.3 SUPPLY VOLTAGE PIN (VDD)

Positive supply voltage pin. Supplies transmitter and
receiver.

1.7.4 RECEIVER DATA

OUTPUT PIN (RXD)
RXD is a CMOS-compatible output that drives High or
Low depending on the differential signals on the CANH
and CANL pins, and is usually connected to the
receiver data input of the CAN controller device. RXD is
High when the CAN bus is Recessive, and Low in the
Dominant state. RXD is supplied by VDD or VIO, in the
MCP2561 or MCP2562, respectively.

1.7.5 SPLIT PIN (MCP2561 ONLY)

Reference Voltage Output (defined as VDD/2). The pin
is only active in Normal mode. In Standby mode, or
when VDD is off, SPLIT floats.

1.7.6 VIO PIN (MCP2562 ONLY)

Supply for digital I/O pins. In the MCP2561, the supply
for the digital I/O (TXD, RXD and STBY) is internally
connected to VDD.

1.7.7 CAN LOW PIN (CANL)

The CANL output drives the Low side of the CAN
differential bus. This pin is also tied internally to the
receive input comparator. CANL disconnects from the
bus when MCP2561/2 is not powered.

1.7.8 CAN HIGH PIN (CANH)

The CANH output drives the high-side of the CAN
differential bus. This pin is also tied internally to the
receive input comparator. CANH disconnects from the
bus when MCP2561/2 is not powered.

 2013 Microchip Technology Inc. DS25167B-page 5

MCP2561/2
1.8 Typical Applications

FIGURE 1-1: MCP2561 WITH SPLIT PIN

VBAT 5V LDO
0.1 μF

VDD CANH
VDD
CANH
TXD

MCP2561
CANTX 60:
300:
PIC CANRX RXD SPLIT
4700 pF
RBX STBY Optional(1) 60: CANL
CANL
VSS VSS

Note 1: Optional resistor to allow communication during bus failure (CANL shorted to ground).

FIGURE 1-2: MCP2562 WITH VIO PIN

VBAT 5V LDO

1.8V LDO
0.1 μF 0.1 μF

VDD CANH
VDD VIO
CANTX CANH
MCP2562

TXD
PIC CANRX RXD 120:
RBX STBY CANL
VSS Vss CANL

DS25167B-page 6  2013 Microchip Technology Inc.

 MCP2561/2
2.0 ELECTRICAL 2.1.5 DIFFERENTIAL VOLTAGE, VDIFF
CHARACTERISTICS (OF CAN BUS)
Differential voltage of the two-wire CAN bus, value
2.1 Terms and Definitions VDIFF = VCANH – VCANL.

A number of terms are defined in ISO-11898 that are 2.1.6 INTERNAL CAPACITANCE, CIN
used to describe the electrical characteristics of a CAN (OF A CAN NODE)
transceiver device. These terms and definitions are
Capacitance seen between CANL (or CANH) and
summarized in this section.
ground during the Recessive state, when the CAN
2.1.1 BUS VOLTAGE node is disconnected from the bus (see Figure 2-1).

VCANL and VCANH denote the voltages of the bus line 2.1.7 INTERNAL RESISTANCE, RIN
wires CANL and CANH relative to ground of each (OF A CAN NODE)
individual CAN node.
Resistance seen between CANL (or CANH) and
2.1.2 COMMON MODE BUS VOLTAGE ground during the Recessive state, when the CAN
RANGE node is disconnected from the bus (see Figure 2-1).

Boundary voltage levels of VCANL and VCANH with

FIGURE 2-1: PHYSICAL LAYER
respect to ground, for which proper operation will occur,
DEFINITIONS
if up to the maximum number of CAN nodes are
connected to the bus.
ECU
2.1.3 DIFFERENTIAL INTERNAL
CAPACITANCE, CDIFF RIN
(OF A CAN NODE) CANL
Capacitance seen between CANL and CANH during RDIFF CDIFF
the Recessive state, when the CAN node is RIN
disconnected from the bus (see Figure 2-1). CANH
CIN CIN
2.1.4 DIFFERENTIAL INTERNAL GROUND
RESISTANCE, RDIFF
(OF A CAN NODE)
Resistance seen between CANL and CANH during the
Recessive state when the CAN node is disconnected
from the bus (see Figure 2-1).

 2013 Microchip Technology Inc. DS25167B-page 7

MCP2561/2
Absolute Maximum Ratings†
VDD .............................................................................................................................................................................7.0V
VIO ..............................................................................................................................................................................7.0V
DC Voltage at TXD, RXD, STBY and VSS .............................................................................................-0.3V to VIO + 0.3V
DC Voltage at CANH, CANL and SPLIT ...................................................................................................... -58V to +58V
Transient Voltage on CANH, CANL (ISO-7637) (Figure 2-5) ................................................................... -150V to +100V
Storage temperature ...............................................................................................................................-55°C to +150°C
Operating ambient temperature ..............................................................................................................-40°C to +150°C
Virtual Junction Temperature, TVJ (IEC60747-1) ....................................................................................-40°C to +190°C
Soldering temperature of leads (10 seconds) .......................................................................................................+300°C
ESD protection on CANH and CANL pins for MCP2561 (IEC 61000-4-2).............................................................±14 kV
ESD protection on CANH and CANL pins for MCP2562 (IEC 61000-4-2)...............................................................±8 kV
ESD protection on CANH and CANL pins (IEC 801; Human Body Model)..............................................................±8 kV
ESD protection on all other pins (IEC 801; Human Body Model).............................................................................±4 kV
ESD protection on all pins (IEC 801; Machine Model) ............................................................................................±300V
ESD protection on all pins (IEC 801; Charge Device Model) ..................................................................................±750V

† NOTICE: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.

DS25167B-page 8  2013 Microchip Technology Inc.

 MCP2561/2
2.2 DC Characteristics
Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C and High (H): TAMB = -40°C to +150°C;
VDD = 4.5V to 5.5V, VIO = 1.8V to 5.5V (Note 2), RL = 60; unless otherwise specified.
Characteristic Sym Min Typ Max Units Conditions

SUPPLY
VDD Pin
Voltage Range VDD 4.5 — 5.5
Supply Current IDD — 5 10 mA Recessive; VTXD = VDD
— 45 70 Dominant; VTXD = 0V
Standby Current IDDS — 5 15 µA MCP2561
— 5 15 MCP2562; Includes IIO
High Level of the POR VPORH 3.8 — 4.3 V
Comparator
Low Level of the POR VPORL 3.4 — 4.0 V
Comparator
Hysteresis of POR VPORD 0.3 — 0.8 V
Comparator
VIO Pin
Digital Supply Voltage Range VIO 1.8 — 5.5 V
Supply Current on VIO IIO — 4 30 µA Recessive; VTXD = VIO
— 85 500 Dominant; VTXD = 0V
Standby Current IDDS — 0.3 1 µA (Note 1)
Undervoltage detection on VIO VUVD(IO) — 1.2 — V (Note 1)
BUS LINE (CANH; CANL) TRANSMITTER
CANH; CANL: VO(R) 2.0 0.5VDD 3.0 V VTXD = VDD; No load
Recessive Bus Output Voltage
CANH; CANL: VO(S) -0.1 0.0 +0.1 V STBY = VTXD = VDD; No load
Bus Output Voltage in Standby
Recessive Output Current IO(R) -5 — +5 mA -24V < VCAN < +24V
CANH: Dominant VO(D) 2.75 3.50 4.50 V TXD = 0
Output Voltage
CANL: Dominant 0.50 1.50 2.25
Output Voltage
Symmetry of Dominant VO(D)(M) -400 0 +400 mV VTXD = VSS
Output Voltage
(VDD – VCANH – VCANL)
Dominant: Differential VO(DIFF) 1.5 2.0 3.0 V VTXD = VSS;
Output Voltage Figure 2-2, Figure 2-4
Recessive: -120 0 12 mV VTXD = VDD,
Differential Output Voltage Figure 2-2, Figure 2-4
-500 0 50 mV VTXD = VDD,no load.
Figure 2-2, Figure 2-4
CANH: Short Circuit IO(SC) -120 85 — mA VTXD = VSS; VCANH = 0V;
Output Current CANL: floating
CANL: Short Circuit — 75 +120 VTXD = VSS; VCANL = 18V;
Output Current CANH: floating
Note 1: Only characterized; not 100% tested.
2: Only MCP2562 has VIO pin. For the MCP2561, VIO is internally connected to VDD.
3: -12V to 12V is ensured by characterization, tested from -2V to 7V.

 2013 Microchip Technology Inc. DS25167B-page 9

MCP2561/2
2.2 DC Characteristics (Continued)
Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C and High (H): TAMB = -40°C to +150°C;
VDD = 4.5V to 5.5V, VIO = 1.8V to 5.5V (Note 2), RL = 60; unless otherwise specified.
Characteristic Sym Min Typ Max Units Conditions

BUS LINE (CANH; CANL) RECEIVER

Recessive Differential VDIFF(R)(I) -1.0 — +0.5 V Normal Mode;
Input Voltage -12V < V(CANH, CANL) < +12V;
See Figure 2-6 (Note 3)
-1.0 — +0.4 Standby Mode;
-12V < V(CANH, CANL) < +12V;
See Figure 2-6 (Note 3)
Dominant Differential VDIFF(D)(I) 0.9 — VDD V Normal Mode;
Input Voltage -12V < V(CANH, CANL) < +12V;
See Figure 2-6 (Note 3)
1.0 — VDD Standby Mode;
-12V < V(CANH, CANL) < +12V;
See Figure 2-6 (Note 3)
Differential VTH(DIFF) 0.5 0.7 0.9 Normal Mode;
Receiver Threshold V -12V < V(CANH, CANL) < +12V;
See Figure 2-6 (Note 3)
0.4 — 1.15 Standby Mode;
-12V < V(CANH, CANL) < +12V;
See Figure 2-6 (Note 3)
Differential VHYS(DIFF) 50 — 200 mV Normal mode, see Figure 2-6,
Input Hysteresis (Note 1)
Common Mode RIN 10 — 30 k (Note 1)
Input Resistance
Common Mode RIN(M) -1 0 +1 % VCANH = VCANL, (Note 1)
Resistance Matching
Differential Input RIN(DIFF) 10 — 100 k (Note 1)
Resistance
Common Mode CIN(CM) — — 20 pF VTXD = VDD; (Note 1)
Input Capacitance
Differential CIN(DIFF) — — 10 VTXD = VDD; (Note 1)
Input Capacitance
CANH, CANL: ILI -5 — +5 µA VDD = VTXD = VSTBY = 0V.
Input Leakage For MCP2562, VIO = 0V.
VCANH = VCANL = 5 V.
COMMON MODE STABILIZATION OUTPUT (SPLIT)
Output Voltage Vo 0.3VDD 0.5VDD 0.7VDD V Normal mode;
ISPLIT = -500 µA to +500 µA
0.45VDD 0.5VDD 0.55VDD V Normal mode; RL  1 M
Leakage Current IL -5 — +5 µA Standby mode;
VSPLIT = -24V to + 24V
(ISO 11898: -12V ~ +12V)
Note 1: Only characterized; not 100% tested.
2: Only MCP2562 has VIO pin. For the MCP2561, VIO is internally connected to VDD.
3: -12V to 12V is ensured by characterization, tested from -2V to 7V.

DS25167B-page 10  2013 Microchip Technology Inc.

 MCP2561/2
2.2 DC Characteristics (Continued)
Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C and High (H): TAMB = -40°C to +150°C;
VDD = 4.5V to 5.5V, VIO = 1.8V to 5.5V (Note 2), RL = 60; unless otherwise specified.
Characteristic Sym Min Typ Max Units Conditions
DIGITAL INPUT PINS (TXD, STBY)
High-Level Input Voltage VIH 0.7VIO — VIO + 0.3 V
Low-Level Input Voltage VIL -0.3 — 0.3VIO V
High-Level Input Current IIH -1 — +1 µA
TXD: Low-Level Input Current IIL(TXD) -270 -150 -30 µA
STBY: Low-Level Input Current IIL(STBY) -30 — -1 µA
RECEIVE DATA (RXD) OUTPUT
High-Level Output Voltage VOH VDD - 0.4 — — V IOH = -2 mA (MCP2561); typi-
cal -4 mA
VIO - 0.4 — — IOH = -1 mA (MCP2562); typi-
cal -2 mA
Low-Level Output Voltage VOL — — 0.4 V IOL = 4 mA; typical 8 mA
THERMAL SHUTDOWN
Shutdown TJ(SD) 165 175 185 °C -12V < V(CANH, CANL) < +12V,
Junction Temperature (Note 1)
Shutdown TJ(HYST) 20 — 30 °C -12V < V(CANH, CANL) < +12V,
Temperature Hysteresis (Note 1)
Note 1: Only characterized; not 100% tested.
2: Only MCP2562 has VIO pin. For the MCP2561, VIO is internally connected to VDD.
3: -12V to 12V is ensured by characterization, tested from -2V to 7V.

 2013 Microchip Technology Inc. DS25167B-page 11

MCP2561/2
FIGURE 2-2: PHYSICAL BIT REPRESENTATION AND SIMPLIFIED BIAS IMPLEMENTATION

Normal Mode Standby Mode

CANH
CANH, CANL, SPLIT

SPLIT SPLIT
floating

CANL

Recessive Dominant Recessive

Time

VDD

CANH

VDD/2 Normal RXD

Standby
Mode
CANL

DS25167B-page 12  2013 Microchip Technology Inc.

 MCP2561/2
2.3 AC Characteristics
Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C and High (H): TAMB = -40°C to +150°C;
VDD = 4.5V to 5.5V, VIO = 1.8V to 5.5V (Note 2), RL = 60; unless otherwise specified.
Param.
Sym Characteristic Min Typ Max Units Conditions
No.
1 tBIT Bit Time 1 — 69.44 µs
2 fBIT Bit Frequency 14.4 — 1000 kHz
3 tTXD-BUSON Delay TXD Low to Bus Dominant — — 70 ns
4 tTXD-BUSOFF Delay TXD High to Bus Recessive — — 125 ns
5 tBUSON-RXD Delay Bus Dominant to RXD — — 70 ns
6 tBUSOFF-RXD Delay Bus Recessive to RXD — — 110 ns
7 tTXD - RXD Propagation Delay TXD to RXD — — 125 ns Negative edge on TXD
8 — — 235 Positive edge on TXD
9 tFLTR(WAKE) Delay Bus Dominant to RXD 0.5 1 4 µs Standby mode
(Standby mode)
10 tWAKE Delay Standby 5 25 40 µs Negative edge on STBY
to Normal Mode
11 tPDT Permanent Dominant Detect Time — 1.25 — ms TXD = 0V
12 tPDTR Permanent Dominant Timer Reset — 100 — ns The shortest recessive
pulse on TXD or CAN bus
to reset Permanent
Dominant Timer

FIGURE 2-3: TEST LOAD CONDITIONS

Load Condition 1 Load Condition 2

VDD/2

RL

CL CL
Pin Pin
RL = 464 
CL = 50 pF for all digital pins VSS VSS

FIGURE 2-4: TEST CIRCUIT FOR ELECTRICAL CHARACTERISTICS

VDD 0.1 µF

CANH
TXD

SPLIT CAN RL 100 pF

Transceiver
RXD
30 pF CANL
GND STBY

Note: On MCP2562, VIO is connected to VDD.

 2013 Microchip Technology Inc. DS25167B-page 13

MCP2561/2
FIGURE 2-5: TEST CIRCUIT FOR AUTOMOTIVE TRANSIENTS
CANH 500 pF
TXD

SPLIT CAN Transient

RL
Transceiver Generator
RXD
CANL 500 pF
GND STBY
Note: On MCP2562, VIO is connected to VDD.

The wave forms of the applied transients shall be in accordance

with ISO-7637, Part 1, test pulses 1, 2, 3a and 3b.

FIGURE 2-6: HYSTERESIS OF THE RECEIVER

RXD (receive data

VOH
output voltage)
VDIFF (r)(i) VDIFF (d)(i)

VOL

VDIFF (h)(i)

0.5 VDIFF (V) 0.9

DS25167B-page 14  2013 Microchip Technology Inc.

 MCP2561/2
2.4 Timing Diagrams and
Specifications

FIGURE 2-7: TIMING DIAGRAM FOR AC CHARACTERISTICS

VDD
TXD (transmit data
input voltage)
0V

VDIFF (CANH,
CANL differential
voltage)

RXD (receive data

output voltage) 3
5
7 4 6
8

FIGURE 2-8: TIMING DIAGRAM FOR WAKEUP FROM STANDBY

VSTBY VDD
Input Voltage

0V
VDD/2
VCANH/VCANL

VTXD = VDD 10

FIGURE 2-9: PERMANENT DOMINANT TIMER RESET DETECT

Minimum pulse width until CAN bus goes to dominant after the falling edge

TXD

VDIFF (VCANH-VCANL)
Driver is off

11 12

 2013 Microchip Technology Inc. DS25167B-page 15

MCP2561/2
2.5 Thermal Specifications
Parameter Symbol Min Typ Max Units Test Conditions
Temperature Ranges
Specified Temperature Range TA -40 — +125 C
-40 — +150
Operating Temperature Range TA -40 — +150 C
Storage Temperature Range TA -65 — +155 C
Thermal Package Resistances
Thermal Resistance, 8L-DFN 3x3 JA — 56.7 — C/W
Thermal Resistance, 8L-PDIP JA — 89.3 — C/W
Thermal Resistance, 8L-SOIC JA — 149.5 — C/W

DS25167B-page 16  2013 Microchip Technology Inc.

 MCP2561/2
3.0 PACKAGING INFORMATION
3.1 Package Marking Information

8-Lead DFN (3x3 mm) Example:

Part Number Code
MCP2561-E/MF DADR
MCP2561T-E/MF DADR DADR
MCP2561-H/MF DADS 1307
256
MCP2561T-H/MF DADS
MCP2562-E/MF DADU
MCP2562T-E/MF DADU
MCP2562-H/MF DADT
MCP2562T-H/MF DADT

8-Lead PDIP (300 mil) Example:

XXXXXXXX MCP2561 MCP2561

XXXXXNNN E/P e^^256
3
OR
H/P e^^256
3

1307 1307
YYWW
8-Lead PDIP (300 mil) Example:

8-Lead SOIC (150 mil) Example:

MCP2561E MCP2561H
SN e^^1246
3 OR SN e^^1246
3
256 256
NNN

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator (e3)
can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

 2013 Microchip Technology Inc. DS25167B-page 17

MCP2561/2

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS25167B-page 18  2013 Microchip Technology Inc.

 MCP2561/2

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2013 Microchip Technology Inc. DS25167B-page 19

MCP2561/2

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS25167B-page 20  2013 Microchip Technology Inc.

 MCP2561/2

        

  3 & ' !&" & 4# *!( !!&    4 %&  &#&
&& 255***'    '5 4

NOTE 1
E1

1 2 3

D
E

A A2

A1 L
c

e
b1 eB
b

6&! 7,8.
'! 9'&! 7 7: ;
7"')  %! 7 <
&  1,
& &  = = 
 ##4 4!!   - 
1!& &   = =
 "# &  "# >#& .  - -
 ##4>#& .   <
:  9&  -< -? 
 & & 9  - 
9# 4!!  <  
6  9#>#& )  ? 
9 * 9#>#& )  < 
:   * + 1 = = -
  
  !"#$%&" '  ()"&'"!&) &#*& &  & # 
 +%&,  & !&
- '! !#.#  &"#' #%!   & "! ! #%!   & "! !!  &$#/  !#
 '! #&    .0
1,21!'!   &$& "! **& "&&  !

        * ,<1

 2013 Microchip Technology Inc. DS25167B-page 21

MCP2561/2

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS25167B-page 22  2013 Microchip Technology Inc.

 MCP2561/2

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2013 Microchip Technology Inc. DS25167B-page 23

MCP2561/2

    !  ""#$%& !'

  3 & ' !&" & 4# *!( !!&    4 %&  &#&
&& 255***'    '5 4

DS25167B-page 24  2013 Microchip Technology Inc.

 MCP2561/2
APPENDIX A: REVISION HISTORY

Revision B (March 2013)

• Updated the “MCP2561/2 Family Members”
table on page 1.

Revision A (March 2013)

• Original Release of this Document.

 2013 Microchip Technology Inc. DS25167B-page 25

MCP2561/2
NOTES:

DS25167B-page 26  2013 Microchip Technology Inc.

 MCP2561/2
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. -X /XX
Examples:
Device Temperature Package a) MCP2561-E/MF: Extended Temperature,
Range 8LD 3x3 DFN package.
b) MCP2561T-E/MF: Tape and Reel,
Extended Temperature,
Device: MCP2561: High-Speed CAN Transceiver with SPLIT
8LD 3x3 DFN package.
MCP2561T: High-Speed CAN Transceiver with SPLIT
(Tape and Reel) (DFN and SOIC only) c) MCP2561-E/P: Extended Temperature,
MCP2562: High-Speed CAN Transceiver with VIO 8LD PDIP package.
MCP2562T: High-Speed CAN Transceiver with VIO d) MCP2561-E/SN: Extended Temperature,
(Tape and Reel) (DFN and SOIC only) 8LD SOIC package.
e) MCP2561T-E/SN: Tape and Reel,
Extended Temperature,
Temperature E = -40°C to +125°C (Extended) 8LD SOIC package.
Range: H = -40°C to +150°C (High)
a) MCP2561-H/MF: High Temperature,
Package: MF = Plastic Dual Flat, No Lead Package - 3x3x0.9 mm 8LD 3x3 DFN package.
Body, 8-lead b) MCP2561T-H/MF: Tape and Reel,
P = Plastic Dual In-Line - 300 mil Body, 8-lead High Temperature,
SN = Plastic Small Outline - Narrow, 3.90 mm Body, 8LD 3x3 DFN package.
8-lead c) MCP2561-H/P: High Temperature,
8LD PDIP package.
d) MCP2561-H/SN: High Temperature,
8LD SOIC package.
e) MCP2561T-H/SN:Tape and Reel,
High Temperature,
8LD SOIC package.

 2013 Microchip Technology Inc. DS25167B-page 27

MCP2561/2
NOTES:

DS25167B-page 28  2013 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, dsPIC,
and may be superseded by updates. It is your responsibility to
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
ensure that your application meets with your specifications.
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
MICROCHIP MAKES NO REPRESENTATIONS OR and UNI/O are registered trademarks of Microchip Technology
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
Incorporated in the U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, MTP, SEEVAL and The Embedded Control Solutions
QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology
FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Silicon Storage Technology is a registered trademark of
devices in life support and/or safety applications is entirely at Microchip Technology Inc. in other countries.
the buyer’s risk, and the buyer agrees to defend, indemnify and
Analog-for-the-Digital Age, Application Maestro, BodyCom,
hold harmless Microchip from any and all damages, claims,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
suits, or expenses resulting from such use. No licenses are
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
conveyed, implicitly or otherwise, under any Microchip
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
intellectual property rights.
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2013, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62077-091-7

QUALITY MANAGEMENT SYSTEM Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
CERTIFIED BY DNV Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures

== ISO/TS 16949 ==
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

 2013 Microchip Technology Inc. DS25167B-page 29

 Worldwide Sales and Service
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Asia Pacific Office India - Bangalore Austria - Wels
2355 West Chandler Blvd. Suites 3707-14, 37th Floor Tel: 91-80-3090-4444 Tel: 43-7242-2244-39
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Tel: 480-792-7200 Harbour City, Kowloon Denmark - Copenhagen
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Fax: 480-792-7277 Hong Kong Tel: 45-4450-2828
Tel: 91-11-4160-8631
Technical Support: Tel: 852-2401-1200 Fax: 45-4485-2829
Fax: 91-11-4160-8632
http://www.microchip.com/ Fax: 852-2401-3431
India - Pune France - Paris
support
Australia - Sydney Tel: 91-20-2566-1512 Tel: 33-1-69-53-63-20
Web Address:
Tel: 61-2-9868-6733 Fax: 91-20-2566-1513 Fax: 33-1-69-30-90-79
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China - Zhuhai
Tel: 86-756-3210040
11/29/12
Fax: 86-756-3210049

DS25167B-page 30  2013 Microchip Technology Inc.