Notes By Prof.

Tanya Shrivastava

UNIT – 2

COMPUTER ORGANIZATION AND ARCHITECTURE

 MINTERMS and MAXTERMS

Every canonical SOP form is Minterm. The sum of Minterm forms SOP (Sum of Product)
functions. It is represented by m. and Minterm are represented by high input (1).
 Normal input variable A1
 Complemented variable A’0
Every canonical POS form is Maxterm. The product of Maxterm forms POS (Product of
Sum) functions. It is represented by M. and Maxterm are represented by low signal (0).
 Normal input variable A0
 Complemented variable A’1
 HALF ADDER
 Half adder is also known as 2 input and 2 output circuits.
 A half adder is a digital logic circuit that performs binary addition of two bit binary numbers.
 It has two inputs, A and B, and two outputs, SUM (S) and CARRY (C).
 The half adder can be implemented using basic gates such as XOR and AND gates.

Now write the equation of SUM and CARRY by using Minterm:

In case of SUM we take corresponding input values where we get SUM 1 in output, so we write the
equation according to Minterm like A1, A’0, B1, B’0

SUM = A’B + AB’ (here we can see this equation is of XOR gate, see the table given below)

So, SUM = A ⊕ B
Similar for carry we take corresponding input values where we get CARRY 1 in output, so we write the
equation according to Minterm like A1, A’0, B1, B’0

CARRY = AB

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Now draw the circuit diagram of half adder:

 FULL ADDER
 Full adder is also known as 3 input and 2 output circuits.
 A full adder is a digital logic circuit that performs binary addition of three bit binary numbers.
 It has three inputs, A, B and C, and two outputs, SUM (S) and CARRY (C).
 The full adder can be implemented using basic gates such as OR, XOR and AND gates.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Now write the equation of SUM and CARRY by using Minterm:

In case of SUM we take corresponding input values where we get SUM 1 in output, so we write the
equation according to Minterm like A1, A’0, B1, B’0

SUM = A’ B’C + A’BC’ + AB’C’ + ABC

SUM = A’(B’C + BC’) + A (B’C’ + BC)

XOR XNOR

SUM = A’(B ⊕ C) + A(B ⊕ C)

Let B ⊕ C = W and B ⊕ C= W’

SUM = A’W + AW’ = A⊕W

SUM = A⊕W, now put the value of W = B ⊕ C

SUM = A⊕ B ⊕ C

Similar for carry we take corresponding input values where we get CARRY 1 in output, so we write the
equation according to Minterm like A1, A’0, B1, B’0

CARRY = A’ BC + AB’C + ABC’ + ABC

CARRY = C(A’B + AB’) + AB(C’+C)

XOR 1

CARRY = C(A⊕ B) + AB

Now draw the circuit diagram of full adder:

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

 HALF SUBTRACTOR
 Half subtractor is also known as 2 input and 2 output circuits.
 A half subtractor is a digital logic circuit that performs binary subtraction of two bit binary
numbers.
 It has two inputs, A and B, and two outputs, DIFFERENCE and BORROW.
 The half subtractor can be implemented using basic gates such as NOT, XOR and AND gates.

 The SOP form of the Difference and Borrow is as follows:

 Diff= A'B+AB' = (A⊕ B)
 Borrow = A'B

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

 FULL SUBTRACTOR
 Full subtractor is also known as 3 input and 2 output circuits.
 A full subtractor is a digital logic circuit that performs binary subtraction of three bit binary
numbers.
 It has three inputs, A, B and C, and two outputs DIFFERENCE and BORROW.
 The full subtractor can be implemented using basic gates such as OR, NOT, XOR and AND
gates.

 The SOP form of the Difference and Borrow is as follows:

 Diff= (A⊕ B) ⊕ C
 Borrow = A'B + (A ⊕ B)'C

 PARALLEL ADDER / RIPPLE CARRYADDER / BINARY ADDER

The Parallel Adder is formed with the help of the Full-Adder circuit. The Full-Adders are connected
in series, and the output carry of the first Adder will be treated as the input carry of the next Full-
Adder.
 A parallel adder is a combinational circuit use to add group of bits or we can say use to add 4
bits or more than 4 bit binary numbers.
 Also known as Ripple Carry Adder.
 The circuit of parallel adder contains several full adders, because each full adder takes 3 inputs
A, B and C (carry). Initial carry (Cin) will be 0.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

 Also in parallel adder all the full adders are not working together, because each full adder is
depend on carry input. Until next full adder does not receive carry the work of circuit does not
move further. So it does not allow using all the full adder simultaneously.
 Also parallel adder contains propagation delay, because next full adder has to wait for carry bit.
 To overcome the disadvantage of parallel adder we use carry look ahead adder means in
parallel adder propagation delay is generated because all the adders are wait for carry. But in
carry look ahead adder we generate a carry in advance, so we don’t need to wait for the carry.

Fig. 4 bit parallel adder

 LOOK AHEAD CARRIES ADDER / CARRY LOOK AHEAD ADDER

 Carry look ahead adder is used to speeding up the process by elimination
propagation delay. In parallel adder propagation delay is generated because each
adder is waiting for carry, so it creates lots of delays.
 So in carry look ahead adder we generate carry in advance in order to avoid this
delay. For example if the data is of 32 bit, 10 bit, 12 bit, we can generate the carry
in advance without calculation.
 Carry look ahead adder works in 2 functions:
 Carry Generate (Gi)
 Carry Propagate (Pi)

Equation of sum and carry of full adder in general is:

SUM = Si = Ai ⊕ Bi ⊕ Ci
CARRY = Ci+1 = (Ai ⊕ Bi) Ci + AiBi

Let, Pi = Ai ⊕ Bi (carry propagator)

Gi = AiBi (carry generator)

Hence, Si = Pi ⊕ Ci and Ci+1 = PiCi + Gi

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Now generate carry in advance with the help of carry equation Ci+1 = PiCi + Gi :
C0 is always zero because initial carry always we assume 0. C0=0

For i=0
Ci+1 = PiCi + Gi
C1 = P0C0 +G0 (1 AND and 1 OR gate)

For i=1
Ci+1 = PiCi + Gi
C2 = P1C1 +G1 (Put the value of C1 in this equation)
C2 = P1 (P0C0 +G0) +G1
C2 = P1P0C0 +P1G0 +G1 (2 AND and 1 OR gate)

For i=2
Ci+1 = PiCi + Gi
C3 = P2C2 +G2 (Put the value of C2 in this equation)
C3 = P2 (P1P0C0 +P1G0 +G1) +G2
C3 = P2P1P0C0 +P2P1G0 +P2G1 +G2 (3 AND and 1 OR gate)

For i=3
Ci+1 = PiCi + Gi
C4 = P3C3 +G3 (Put the value of C2 in this equation)
C4 = P3 (P2P1P0C0 +P2P1G0 +P2G1 +G2) +G3
C4 = P3P2P1P0C0 +P3P2P1G0 + P3P2G1 + P3G2 +G3 (4 AND and 1 OR gate)

Hence, according to the circuit diagram up to C4 there is total 10 AND gates and 4 OR gates.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Numerical based on Carry Look Ahead Adder:

Q. Let x be the number of AND gates present in the 4 bit carry look ahead adder and y be the
number of OR gates Numerical presents in that adder then the value of 2x + 2y is

Answer.
Here n= 4, hence
Formula: AND gates = n(n + 1)/2
Formula: OR gates = n
So AND gates = 10
OR gates = 4
So,2x+2y=28

Q. 1-bit full-adder takes 20 ns to generate carry-out bit and 40 ns for the sum bit. The maximum rate
of addition per second, when four 1-bit full adders are cascaded is ×106/sec

Solution

Maximum rate of addition = 1/100ns = 107/sec = 10×106/sec

Q. The carry and sum of a full-adder takes 20 ns and 30 ns respectively. Then calculate the maximum
number of additions performed in a second, if three full adders are cascaded ×106/sec (Round
of two decimal points).
Solution
Tcarry = 20 ns, Tsum = 30 ns (given)

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Q. In a 4 bit carry look ahead adder the input bits are 1011 & 1001, the Generate, Propagate and
carry signal from the third stage respectively:

1. 0,0,0
2. 0,1,0
3. 1,1,0
4. 1,0,1

Solution: hence, Pi = Ai ⊕ Bi and Gi = AiBi

1 0 1 1 A3 A2 A1 A0 = 1011
+1 0 0 1 B3 B2 B1 B0 = 1001

C0 = G0 + P0Cin

= A0B0 + (A0 ⊕ B0) Cin

= 1.1 + (1⊕1)0 (Cin = 0, initial carry always 0)

=1

C1 = G1 + P1C0

= A1B1 + (A1 ⊕ B1) C0

= 1.0 + (1⊕0)1

=1

C2 = G2 + P2C1

= A2B2 + (A2 ⊕ B2) C1

= 0.0 + (0⊕0)1

=0

Hence in 3rd stage the value is A2 = 0, B2 = 0, C2 = 0

Generation of 3rd stage = G2 = A2.B2 = 0.0 = 0

Propagation of 3rd stage = P2 = A2 ⊕ B2 = 0 ⊕ 0 = 0

So, the generate, propagate and carry signal from the third stage are 0,0,0 respectively.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

 MULTIPLICATION: SIGNED OPERAND MULTIPLICATION or SIGNED

MAGNITUDE MULTIPLICATION
Multiplication of two fixed point binary number in signed magnitude representation is done with
process of successive shift and add operation.

Hardware Implementation:
Following components are required for the Hardware Implementation of multiplication
algorithm :

Hence Multiplicand is the first no. and multiplier is the second no.
 Multiplicand always store in B register in the form of binary.
 Sign bit of multiplicand store in BSign register.
 Multiplier always store in Q register in the form of binary.
 Sign bit of multiplier store in QSign register.
 And the A register contains partial addition
 ASign register contains partial addition sign bit
Sequence Counter register (SC) is used to store number of bits in the multiplier.

Shift Right = 10010 ×

Insert 0 01001

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

 BOOTHS ALGORITHM
The booth algorithm is a multiplication algorithm that allows us to multiply the two signed binary
integers in 2's complement, respectively. It is also used to speed up the performance of the multiplication
process. It is very efficient too.

Arithmetic Shift Right

In case of shift right we simply perform shift right operation. (shift the binary no.to the
right ).
But Arithmetic Shift Right operation is different in this first we perform shift right
operation and then copy the last bit. For ex.
1 1 0 0×
Last bit is 1 1 1 0 Arithmetic Shift Right
copied

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Q. Multiply 7 and 3 using Booth’s Algorithm.

Solution: let’s assume register size = 4 bit. Hence we get the answer in 4 cycles. Here both the values
7 & 3 are positive.

M = Multiplicand = 7 = 0111 AC = AC + M
Q = Multiplier = 3 = 0011
-M = 2’s Complement of M AC = AC – M, so we can also write
M = 0111 this equation in another way:
1’s = 1000 AC = AC + (-M)
2’s = +1
2’s = 1001 For negative value we always find 2’s complement
-M = 1001

AC Q Q-1 Operation
0000 0011 0 Initial
1001 0011 0 Q0.Q-1 = 10, AC=AC+(-M), AC= 1001
1100 1001 1 Arithmetic shift right
1110 0100 1 Q0.Q-1= 11, Arithmetic shift right
0101 0100 1 Q0.Q-1=01, AC=AC+M, AC=1110,
M=0111, AC = 10101 carry discarded

0010 1010 0 Arithmetic shift right

0001 0101 0 × Q0.Q-1=00, Arithmetic shift right

Hence 7 * 3 = 21, 00010101 = 21

Q. Multiply -7 and 3 using Booth’s Algorithm.

Solution: let’s assume register size = 4 bit. Hence we get the answer in 4 cycles. Here the value 7 is
negative & 3 is positive.

For any negative value we always find 1’S and 2’s complement first.

M = Multiplicand = -7 = 1001 For negative value we always find 2’s complement

-7= 0111,
1’s 1000 AC = AC + M
2’s +1
1001 AC = AC – M, so we can also write
Q = Multiplier = 3 = 0011 this equation in another way:

AC = AC + (-M)

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

-M = 2’s Complement of M
M = 1001
1’s = 0110
2’s = +1
2’s = 0111
-M = 0111

AC Q Q-1 Operation
0000 0011 0 Initial

0111 0011 0 Q0.Q-1=10, AC=AC-M, AC=AC+(-

M), AC=0111
0011 1001 1 ARITHMETIC SHIFT RIGHT
0001 1100 1 Q0.Q-1=11, ARITHMETIC
SHIFT RIGHT

1010 1100 1 Q0.Q-1=01, AC=AC+M, AC=1010

1101 0110 0 ARITHMETIC SHIFT RIGHT

1110 1011 0 Q Q0.Q-1=00, ARITHMETIC
SHIFT RIGHT
HENCE -7*3 = -21 so we have to find 2’s of the negative value

11101011
1’s = 00010100
2’s = +1
2’s = 00010101 -21

Q. Multiply -7 and -3 using Booth’s Algorithm. Register Size 4 Bits

Solution: here both the numbers are negative so we have to find 2’s of both the no.
M = -7 = 2’s = 1001 AC = AC + M
Q = -3 = 2’s = 1101
AC = AC – M, so we can also write
-M = 0111 ( -M => M=1001, 1’s = 0110, 2’s = 0111)
this equation in another way:
Here we have to perform 4 cycles because
register size = 4 bits AC = AC + (-M)

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

AC Q Q-1 Operation
0000 1101 0 Initial

0111 1101 0 Q0.Q-1=10, AC=AC-M, AC=AC+(-

M), AC=0000, -M=0111, AC= 0111
0011 1110 1 ARITHMETIC SHIFT RIGHT
1100 1110 1 Q0.Q-1=01, AC=AC+M, AC=
1100
1110 0111 0 ARITHMETIC SHIFT RIGHT
Q0.Q-1=10, AC=AC-M, AC=AC+(-
0101 0111 0 M), AC= 1110, -M=0111, AC=10101
CARRY DISCARDED
0010 1011 1 ARITHMETIC SHIFT RIGHT
0001 0101 1 × Q0.Q-1=11, ARITHMETIC
SHIFT RIGHT
HENCE -7 * -3 = 21 value is positive so we don’t need to find any 2’s
complement.
00010101 = 21

 ARRAY MULTIPLIER
 An array multiplier is a digital combinational circuit used for multiplying two binary numbers by
employing an array of full adders and half adders. This array is used for the nearly simultaneous
addition of the various product terms involved. To form the various product terms, an array of
AND gates is used before the Adder array.
 Array multiplier is faster than signed magnitude multiplication and booth algorithm because in this
we do not perform any arithmetic shift operations or do not find any 1’s or 2’s complement, in this
we simply perform multiplication of the given numbers.
 Array multiplier circuit is based on add and shift algorithm.
 The addition can be performed with normal carry and adder.
 Here mainly we use adder like half adder, full adder and 4 bit parallel adder and AND gates.
Example: 2 by 2 bit array multiplier

Here we need 4 AND gates and 2

half adder, half adder because
here we perform partial addition
between two bit binary number.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Example: 4 by 4 bit array multiplier

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Q. An array multiplier is used to find the product of a 3 bit number with a 4 bit
number. How many 4 bits addresses are required to perform multiplication?

Solution:
Given no. are 3 bit and 4 bit, let A = a2 a1 a0 and B = b3 b2 b1 b0

Hence A total no. of Two 4 bit addresses are required for the multiplication operation.

 DIVISION AND LOGIC OPERATION

The Division of two fixed-point binary numbers in the signed-magnitude representation is done by the
cycle of successive compare, shift, and subtract operations.
The binary division is easier than the decimal division because the quotient digit is either 0 or 1. Also,
there is no need to estimate how many times the dividend or partial remainders adjust to the divisor..

The division algorithm is generally of two types, i.e., fast algorithm and slow algorithm. Fast
algorithm is restoring algorithm and slow algorithm is non restoring algorithm.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Restoring division operates on fixed point fractional numbers and depends on the assumption
0 < D < N,
Where,
N = Numerator (dividend)
D = Denominator (divisor)
Restoring division is usually performed on the fixed point fractional numbers. When we perform
division operations on two numbers, the division algorithm will give us two things, i.e., quotient and
remainder. This algorithm is based on the assumption that 0 < D < N. With the help of digit set {0, 1},
the quotient digit q will be formed in the restoring division algorithm

Non-restoring division uses the digit set {−1, 1} for the quotient digits instead of {0, 1}. The algorithm
is more complex, but has the advantage when implemented in hardware that there is only one decision
and addition/subtraction per quotient bit; there is no restoring step after the subtraction, which
potentially cuts down the numbers of operations by up to half and lets it be executed faster.

RESTORING DIVISION ALGORITHM

Some steps of restoring division algorithm, which is described as follows:

Step 1: In this step, the corresponding value will be initialized to the registers, i.e., register A will
contain value 0, register M will contain Divisor, register Q will contain Dividend, and N is used to
specify the number of bits in dividend.

Notes By Prof. Tanya Shrivastava

 Notes By Prof. Tanya Shrivastava

Step 2: In this step, register A and register Q will be treated as a single unit, and the value of both the
registers will be shifted left.

Step 3: After that, the value of register M will be subtracted from register A. The result of subtraction
will be stored in register A.

Step 4: Now, check the most significant bit of register A. If this bit of register A is 0, then the least
significant bit of register Q will be set with a value 1. If the most significant bit of A is 1, then the least
significant bit of register Q will be set to with value 0, and restore the value of A that means it will
restore the value of register A before subtraction with M.

Step 5: After that, the value of N will be decremented. Here n is used as a counter.

Step 6: Now, if the value of N is 0, we will break the loop. Otherwise, we have to again go to step 2.

Step 7: This is the last step. In this step, the quotient is contained in the register Q, and the remainder is
contained in register A.

For example:

In this example, we will perform a Division restoring algorithm.

HERE REGISTER
1. Q = Dividend = 7 = 111 SIZE IS 3 BITS, SO
2. M = Divisor = 3 = 011 IN 3 CYCLES WE
3. -M = 101 GET THE ANSWER.

S
M A Q OPERATION
011 ×000 111 INITIAL

001 110 INSERT 0 SHIFT LEFT AQ

MSB 110 110 Q0 A=A-M, A= A+(-M), A=001 -M=101
A=110,
Restore A 001 110 Here MSB of A= 1, Q(0)=0, Restore A
011 100 INSERT 0 SHIFT LEFT AQ
000 100 A=A-M, A=A+(-M) A=011, -M=101,
A=1000, CARRY DISCARDED
A=000
000 101 Here MSB of A=0, Q(0)=1
001 010 INSERT 0 SHIFT LEFT AQ
110 010 A=A-M, A=A+(-M), A=001, -M=101,
A=110
001 010 Here MSB of A= 1, Q(0)=0, Restore A
REMAINDER QUOTIENT STOP
001 = 1 010 = 2

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

NON - RESTORING DIVISION ALGORITHM

steps of the non-restoring division algorithm, which are described as follows:

Step 1: In this step, the corresponding value will be initialized to the registers, i.e., register A will
contain value 0, register M will contain Divisor, register Q will contain Dividend, and N is used to
specify the number of bits in dividend.

Step 2: In this step, we will check the sign bit of A.

Step 3: If this bit of register A is 1, then shift the value of AQ through left, and perform A = A + M. If
this bit is 0, then shift the value of AQ into left and perform A = A - M. That means in case of 0, the 2's
complement of M is added into register A, and the result is stored into A.

Step 4: Now, we will check the sign bit of A again.

Step 5: If this bit of register A is 1, then Q[0] will become 0. If this bit is 0, then Q[0] will become 1.
Here Q[0] indicates the least significant bit of Q.

Step 6: After that, the value of N will be decremented. Here N is used as a counter.

Step 7: If the value of N = 0, then we will go to the next step. Otherwise, we have to again go to step 2.

Notes By Prof. Tanya Shrivastava

 Notes By Prof. Tanya Shrivastava

Step 8: We will perform A = A + M if the sign bit of register A is 1.

Step 9: This is the last step. In this step, register A contains the remainder, and register Q contains the
quotient.

For example:

In this example, we will perform a Non-Restoring Division algorithm with the help of an Unsigned
integer.

1. Q = Dividend = 7 = 111
2. M = Divisor = 3 = 011
3. -M = 101

M A Q OPERATION
011 000 111 INITIAL
SIGN BIT OF A=0
001 110 LEFT SHIFT AQ
110 110 A=A-M, A=A+(-M), A=001, -M=101
A=110
110 110 SIGN BIT OF A=1, Q(0)=0
SIGN BIT OF A=1
101 101 LEFT SHIFT AQ
000 101 A=A+M, A=101, M=011
A=1000 CARRY DISCARDED
000 101 SIGN BIT OF A=0, Q(0)=1
SIGN BIT OF A=0
001 010 LEFT SHIFT AQ
110 010 A=A-M, A=A+(-M), A=001, -M=101
A=110
110 010 SIGN BIT OF A=1, Q(0)=0
001 010 Hence 3 cycles are done, counter=N=0
So we will perform algorithm further
SIGN BIT OF A=1
A=A+M, A=110, M=011
A=1001, CARRY DISCARDED
REMAINDER QUOTIENT

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

 ARITHMETIC AND LOGIC UNIT DESIGN

The Arithmetic Logic Unit (ALU) is the heart of any CPU. An ALU performs three kinds of
operations, i.e.

 Arithmetic operations such as Addition/Subtraction,

 Logical operations such as AND, OR, etc. and
 Data movement operations such as Load and Store

ALU derives its name because it performs arithmetic and logical operations. A simple ALU design is
constructed with Combinational circuits. ALUs that perform multiplication and division are designed
around the circuits developed for these operations while implementing the desired algorithm. More
complex ALUs are designed for executing Floating point, Decimal operations and other complex
numerical operations.

Combinational ALU
 A primitive ALU supporting three functions AND, OR and ADD is explained in figure 1 The
ALU has two inputs A and B.
 These inputs are fed to AND gate, OR Gate and Full ADDER.
 The Full Adder also has CARRY IN as an input. The combinational logic output of A and B is
statically available at the output of AND, OR and Full Adder.
 The desired output is chosen by the Select function, which in turn is decoded from the
instruction under execution.
 Multiplexer passes one of the inputs as output based on this select function.
 Select Function essentially reflects the operation to be carried out on the operands A and B.
Thus A and B, A or B and A+B functions are supported by this ALU. When ALU is to be
extended for more bits the logic is duplicated for as many bits and necessary cascading is done.
 The AND and OR logic are part of the logical unit while the adder is part of the arithmetic unit.

Figure 1 A Primitive ALU supporting AND, OR and ADD function

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

The simplest ALU has more functions that are essential to support the ISA of the CPU. Therefore the
ALU combines the functions of 2's complement, Adder, Subtractor, as part of the arithmetic unit. The
logical unit would generate logical functions of the form f(x,y) like AND, OR, NOT, XOR etc. Such a
combination supplements most of a CPU's fixed point data processing instructions.

Figure 2 ALU Symbol

So far what we have seen is a primitive ALU. ALU can be as complex as the variety of functions that
are carried out by the ALU. The powerful modern CPUs have powerful and versatile ALUs. Modern
CPUs have multiple ALU to improve efficiency.

 FLOATING POINT ARITHMETIC OPERATION

 IEEE STANDARD FOR FLOATING POINT NUMBERS
 IEEE STANDARD 754 FOR FLOATING POINT NUMBERS

A floating point number is a positive or negative whole number with a decimal point. For example,
5.5, 0.25, and -103.342 are all floating point numbers, while 91, and 0 are not these are fixed point
numbers. Floating point numbers get their name from the way the decimal point can "float" to any
position necessary.
A float represents numbers using a binary-equivalent of scientific notation. For example, the number
1.2 x 103 can be represented as a float. Floats work well when we're dealing with very large or very
small values but perfectly accurate measurements and arithmetic are not required.

Floating point representation has three parts:

 Mantissa
 Base = M * BE
 Exponent

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Number Mantissa Base Exponent

3 * 106 3 10 6
110 * 28 110 2 8
6132.784 6132784 10 -3

IEEE 754 FLOATING POINT NUMBER REPRESENTATION

Q. Represent (1259.125)10 in single and double precision format.

Solution: The number is a decimal fraction in single and double-precision format

Step 1: Convert the decimal number into binary format, divide it into two points by lower cumulative
multiplication we get,
1259 = (10011100011)
0.125 = 0.125*2= 0.250 = 0
=0.250*2 =0.500 = 0
=0.500*2=1.00 = 1
0.125 = (001)
1259.125 = (10011100011.001)
Step 2: Normalize the number
A single precision formula is (1.N ) 2e-127,

A double precision formula is (1.N ) 2e-1023

(10011100011.001) you have to float the number to the right side

i.e 1.0011100011001 x 2¹⁰ (the number of moved bits) here N = 0011100011001 is mantissa, also
mantissa include sign bit so first bit of sign bit is 0.
Sign bit
Step 3 : Single precision format :

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

(1.N ) 2e-127= 1.0011100011001 x 2 ¹⁰

e-127= 10, e = 137 (now convert decimal to binary)
e= 137 (10001001).

Step 4: Double precision format:

(1-N ) 2e-1023= 1.0011100011001 x 2 ¹⁰
e-1023= 10, e = 1033 (now convert decimal to binary)
e= 1033 (10000001001). (you need to have 11 bits here.)

This is how we represent a binary number in single precision format and double precision format.

Q. Represent the following decimal number in IEEE Standard floating point format in a single
precision and Double precision representation method.

i. (32.75) 10

ii. (-506.257) 10

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Solution:

i. (32.75) 10

Step 1: Convert the decimal number into binary format, divide it into two points by lower cumulative
multiplication we get,
32 = (100000)
0.75 = 0.75*2= 1.50 = 1
=0.50*2 =1.00 = 1
0.75 = (11)
32.75 = (100000.11)
Step 2: Normalize the number
A single precision formula is (1.N ) 2e-127,

A double precision formula is (1.N ) 2e-1023

(100000.11) you have to float the number to the right side

i.e 1.0000011 x 25 (the number of moved bits) here N = 0000011 is mantissa, also mantissa include sign
bit so first bit of sign bit is 0.
Sign bit
Step 3 : Single precision format :

(1.N ) 2e-127= 1.0000011 x 25

e-127= 5, e = 132 (now convert decimal to binary)
e= 132 (10000100).

10000100 00000000000000000000000

Step 4: Double precision format:

(1-N ) 2e-1023= 1.0000011 x 25
e-1023= 5, e = 1028 (now convert decimal to binary)
e= 1028 (10000000100). (you need to have 11 bits here.)

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

10000000100 00000

This is how we represent a binary number in single precision format and double precision format.

ii (-114.625) 10

Step 1: Convert the decimal number into binary format, divide it into two points by lower cumulative
multiplication we get,
114 = (01110010)
0.625 = 0.625*2= 1.250 = 1
=0.250*2 =0.500 = 0
=0.500*2=1.00 = 1
0.625 = (101)
114.625 = (01110010.101)
Step 2: Normalize the number
A single precision formula is (1.N ) 2e-127,

A double precision formula is (1.N ) 2e-1023

(01110010.101) you have to float the number to the right side

i.e 1.110010.101 x 26 (the number of moved bits) here

Step 3 : Single precision format :

(1.N ) 2e-127= 1.110010101 x 26

e-127= 6, e = 133 (now convert decimal to binary)

e= 133 (10000101).

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

1 10000101 11001000000000000000000

Step 4: Double precision format:

(1-N ) 2e-1023= 1.110010101 x 26

e-1023= 6, e = 1029 (now convert decimal to binary)

e= 1029 (10000000111). (you need to have 11 bits here.)

1 10000000111 11001

This is how we represent a binary number in single precision format and double precision format.

Notes By Prof. Tanya Shrivastava

Notes By Prof. Tanya Shrivastava

Q. Represent floating point representation in 32 bits of binary number

00110010101110100000000000000000.

Solution: 00110010001110100000000000000000

Sign bit = 0

Exponent = 01100100 = (100)10

Mantissa = 01110100000000000000000 = 1.1101 * 1021

Q. Perform arithmetic operations on the following decimal numbers in binary using signed-
magnitude representation.

1. (+42) +(-13)

2. (-42) -(-13)

Solution:

42: 101010

-13 = 110011
13: 001101
1’s: 110010
2’s: +1
2’s: 110011

(+42)10 + (-13)10 = (101010)2 + (-1101)2 = (101010)2 + (110011)2 = (1011101)2 = (11101)2 =

(29)10

(-42)10 - (-13)10 = -42 + (-(-13)) = -42 + 13 = (-101010)2 + (1101)2 = (-101010)2 + (1101)2=

(010110)2 + (001101)2 = (100011)2 There is no carry. Thus the answer is (-11101)2 = (-29)10

Notes By Prof. Tanya Shrivastava