Canada HSD Event

High-Speed
Digital Design
Workshop
Oct 2022

1
Next-Generation Memory Solutions

2
 Topics Covered
M E M O R Y S I M U L AT I O N C H A L L E N G E S A N D S O L U T I O N S

• Market insights in Memory Technologies

• Equalizations and forwarded clocking
• Going higher with PAM3 and PAM4

3
Market Insights in Memory
Technologies

4
Example of Memory Systems
Xilinx Versal Platform
FPGA (Controller)

On-Board LPDDR

DIMM Connector
DIMM Module (DDR)

5
Advances and Latest Standards in Memory Interfaces
DRAM - (Dynamic Random Access Memory) and NAND Flash (Nonvolatile)

• DDR (Double Data Rate) Market to

o Can be used as a discrete device or in DIMM (Dual Inline Memory Module) $$ stay flat or shrink
DDR3,4 LPDDR4,4x GDDR6, HBM2
o Wide channel widths, high densities, and multiple form factors
o Application: PCs, servers, cloud computing, networking, etc

• LPDDR (Low Power Double Data Rate)

o Low power, narrower channel width year
o Application: Mobile devices, automotive applications

• GDDR (Graphics Double Data Rate) and HBM (High Bandwidth Memory)
o Higher data throughput
o Application: Graphics, AI, data centers, etc $$
DDR5 LPDDR5 GDDR6x,7, HBM2E,3

• Flash Memory Market to

o Non-volatile memories grow
o Application: typically, storage applications
year

6
Path, We Took and Path Ahead of Us!
The road to next generation

Speed Class “Low Speed” “High Speed” “Serial Speed” “Hyper Speed” “Light Speed”

Memory Type SDR & Flash DDR1/2/3 DDR4 DDR5 Post DDR5

Bit Rate 133 400-1600 3200 6400/8400 12000+?

What’s Next?

New Fanout Timing & Random Impulse SoC? Complex

Technology Signal jitter & Response modulation
Integrity noise (PAM3, PAM4..)

2001 2014 2018 2022 2026?

Interval
~ 20 years ~ 13 years ~ 4 years ~ 4 years Conceptual
Disruption 7
What Matters in Memory Simulations?
A SIMPLE PICTURE OF MEMORY SYSTEMS

DRAM

8
* Courtesy of HP
 What Matters in Memory Simulations?
AMI MODELS, CHANNEL MODELS Simulation Technologies:
• Transient Convolution
• DDR Bus Sim
• Bit-by-Bit
IBIS Models
• Statistical
(Input/Output Buffer Information)

AMI Models
(Algorithmic Modeling Interface)

HSPICE Models

DRAM

Pre- and Post-Layout

Channel Models 9
Next Generation Memory Systems - Market Insight #1
SPEED NEVER GOES DOWN! GDDR6x : 19GT and 21GT

LPDDR5 : 8.5G

Compare:
PCIe Gen4: ~16GT/s per lane
PCIe Gen5: ~32GT/s per lane

10
 Next Generation Memory Systems - Market Insight #2
BEFORE DDR5, LPDDR5, AND GDDR6X

• Clear boundaries between DDR and SerDes

Forwarded Clocking
SerDes Embedded Clocking
DC Memory
Equalization CAC
CDR Data Cycle DBI Vref
AMI Fly-by
Retimer Timing
DFE Single Ended
Redriver Pre-amble
PAM3 NRZ Burst Mode
Optical PAM4 Write Leveling IBIS
Differential Strobe
Post-amble

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 Next Generation Memory Systems - Market Insight #2
BLURRY BOUNDARIES IN SERDES/MEMORY

• Blurry boundaries between DDR and SerDes

Forwarded Clocking
SerDes Embedded Clocking
DC Memory
Equalization CAC
CDR Data Cycle DBI Vref
AMI Fly-by
Retimer Timing
DFE Single Ended
Redriver Pre-amble
PAM3 NRZ Burst Mode
Optical PAM4 Write Leveling IBIS
Differential Strobe
Post-amble

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 Next Generation Memory Systems - Market Insight #3
E Q U A L I Z AT I O N I N M E M O R Y S I N G L E E N D E D S I G N A L S ?

Controller

Hmm… Closed Eye Hey, Got it right!

DRAM

Single-ended (DC components) Single-ended (DC components)

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 Equalizations and
Forwarded Clocking

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 Modeling and Simulation Challenges
AL G O R I T H M I C M O D E L I N G I N T E R FAC E ( AM I )

• Memory data signals are single ended signals, having DC components

o Solved in IBIS-AMI with DC_Offset parameter

• Asymmetric rise and fall edges in single-ended I/O

o Solved with separate impulse response for rise and fall edges

• Memory has the clock forwarding architecture than embedded clocking in SerDes
o DQ Rx uses a DQS signal as the forwarded clock to clock the DQ Rx DFE slicer and data sampling
oSolved in IBIS-AMI with three clocking options (IBIS BIRD 209) – included in IBIS 7.1
➢Ideal clocking
➢Time data clocking
➢Waveform data clocking (a.k.a GetWave2 – Two inputs, Data and Strobe inputs)
oADS2023 Update1 officially supports BIRD209

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 Forwarded Clocking in Memory Equalizations
F O RWAR D E D C L O C K I N G AN D J I T T E R T R AC K I N G
W/O PI W/ PI

• Memory Designer addresses:

o Phase Interpolator in Rx controller to adjust the DQ-DQS skew for
optimal DQ Rx DFE clocking in READ operations
No Jitter Tracking

o Jitter tracking (less-correlated jitter between DQ and DQS Rx)

Jitter Tracking
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 PI Output Delay Nonlinearity and Discretization
P H A S E I N T E R P O L AT O R

𝒏 𝑵−𝒏 Output delay with Ideal inputs

𝒗𝒐𝒖𝒕 𝒕 = 𝒗𝒊𝒏 𝒕 − 𝝉𝟏 + 𝒗𝒊𝒏 𝒕 − 𝝉𝟐 , 𝒏 = 𝟎, 𝟏, … , 𝑵
𝑵 𝑵
PI output waveforms

PI input waveforms No
LPF
n
Output delay after LPF

time

Delay nonlinearity and With

discretization can only be LPF
captured by physical model of time Reference linear delay
phase interpolator! Actual delay
n
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 DQS Jitter Amplification by Phase Interpolator
B E N E F I T S O F F O RWAR D E D C L O C K I N G

• Example of DQS jitter amplification by phase interpolator (PI)

𝒏 𝑵−𝒏
𝒗𝒐𝒖𝒕 𝒕 = 𝒗𝒊𝒏 𝒕 − 𝝉𝟏 + 𝒗𝒊𝒏 𝒕 − 𝝉𝟐 , 𝒏 = 𝟎, 𝟏, … , 𝑵
𝑵 𝑵

• N=32, t1=0, t2=UI/2, and sinusoidal vin without LPF

• 10% DCD in phase interpolator input DQS
• Output DQS DCD >= 10% and varies with n
• Jitter amplification is a direct result of mixing
• With LPF the amplification is even larger

Impossible to model this effect without

DQS waveform input (GetWave2)!
Keysight Webinar Sept 2021 18
 DQS Correlated Voltage Noise
B E N E F I T S O F F O RWAR D E D C L O C K I N G

• DQ and DQS voltage noise can be correlated

• If this effect is not modeled, eye width can be underestimated by up to 10%
• DQS waveform is needed to model voltage noise impacts on phase interpolator, slicer and hence
DFE

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 Comparison Between BIRD209 Clock Options
BENEFIT SUMMARY

• These factors critically impact system performance

• IC vendors specifically request these effects to be modeled
• Note that GetWave2 is still supported for the backward compatibility.

Effect to model Waveform Time Data internal CDR

Input input
Clock forwarding and DQ-DQS jitter tracking Yes Yes No
DQ slicer sensitivity in terms of DQS slew rate Yes No No
Physical model of phase interpolator (PI) Yes No No
PI output delay nonlinearity and discretization Yes No No
DQS correlated voltage noise Yes No No
DQS jitter amplification by PI Yes No No

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 Difficulties to Generate AMI Models…
A M I M O D E L G E N E R AT I O N M AY B E C O M E A B O T T L E N E C K

• Not every silicon vendor provides AMI models

• Memory interface designers are new to AMI models
• Existing AMI modeling tool kits are quite complicated, difficult, and not user-friendly
• “I don’t want to learn new tools, ex SystemVue or matlab, and c-programming, etc”
• “I only need models for DDR5 or LPDDR5, but simple and quick way!”
• Etc…

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 Memory Interface AMI Model Builder
DDR5/LPDDR5/GDDR7 AMI MODEL BUILDING WIZARD

Don’t have AMI model for DDR5/LPDDR5/GDDR7? No problem!

You can build your own AMI models easily and quickly!

Wizard like guided AMI model building process

.ami
.dll or .so
Build
.ibs
View CTLE frequency response .conf (re-usable)

Extensive standard model features:

• Delay
• Vref Calibration
• CTLE
• AGC
• Compression
• DFE
• Forward clocking (GetWave2)
• …
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Going Higher With PAM3
and PAM4

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 Refresher on PAM4
H I G H E R T H R O U G P U T W I T H S I N G L E - E N D E D PA M 4

• Widely used in SerDes applications with embedded clocking

• PAM4 carries 2 bits per symbol or one PAM4 level
11 10
• PAM4 symbol rate is half of bit rate, which increase bandwidth
efficiency on high-speed data and potential reduction on clock 10 11
Linear Gray
frequency. Data rate = 2 x symbol rate 01 01
• Level separation in PAM4 is 1/3 of that in NRZ → -9.5dB SNR 00 00
penalty, which must be offset by
• Sufficient dynamic and linearity range

• Powerful equalization capability

• Efficient tuning and optimization

• Reduced jitter and noise impairments

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 Single-Ended PAM4 Signaling in AMI Simulation
S I N G L E E N D E D P A M 4 A M I S I M U L AT I O N W O R K F L O W

• IBIS-AMI is proven a versatile and high-performance modeling and simulation framework for
serial and parallel link analyses
• AMI simulation workflow for single-ended PAM4:
• Assumed to be constant
• Midpoint between level 0 and 3
static state voltage at Rx input
• ADS characterize it and pass it
Stimulus input waveform to Rx_Init through DC_Offset
to Tx GetWave
𝑽𝑫𝑪_𝒐𝒇𝒇𝒔𝒆𝒕
Rx GetWave recovers
𝒗𝒊𝒏 𝒕 = 𝑽𝑫𝑪_𝒐𝒇𝒇𝒔𝒆𝒕 + 𝒗𝒅𝒊𝒇𝒇 (𝒕) 𝒗𝒊𝒏 𝒕 by adding
SE signal at Rx input is 𝒗𝒅𝒊𝒇𝒇 (𝒕) 𝑽𝑫𝑪_𝒐𝒇𝒇𝒔𝒆𝒕 to 𝒗𝒅𝒊𝒇𝒇 (𝒕)
decomposed into common
• Differential and differential components
• 4 levels at -1/2, -1/6, 1/6, and 1/2 • Results of convolution between
• Symbols 0, 1, 2, 3 Tx GetWave and the channel
impulse response
• Input waveform to Rx GetWave

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 What Can be Modeled? - Transmitter Nonlinearity (RLM)
L E V E L M I S M AT C H R AT I O

1/2
• Stimulus input waveform to Tx GetWave has four idea levels of -1/2, -1/6,
1/6 and 1/2 V, representing four PAM4 levels linearly separated by a 1/6

uniform step of 1/3 V -1/6

• Tx GetWave can internally map these levels to non-ideal values to model -1/2
Tx nonlinearity
Linear Tx Nonlinear Tx

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 What Can be Modeled? - Transmitter SNDR
S I G N A L - T O - N O I S E - A N D - D I S T O R T I O N - R AT I O

• 𝑝𝑚𝑎𝑥 : maximum Tx output signal amplitude 𝒑𝟐𝒎𝒂𝒙

𝑺𝑵𝑫𝑹 = 𝟏𝟎𝒍𝒐𝒈𝟏𝟎
• 𝜎𝑒 : RMS of Tx output nonlinear distortion 𝝈𝟐𝒆 + 𝝈𝟐𝒏
• 𝜎𝑛 : RMS of Tx output noise

Without Tx noise With 12dB Tx noise

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What Can be Modeled? - Transmitter Equalization
PRE-SHOOT AND DE-EMPHASIS

Without Tx EQ With 3dB Tx deemphasis

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What Can be Modeled? - Rx Equalization
CTLE AND DFE

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PAM4 AMI Model Generation With Custom CTLE Support
AD VA N C E D M E M O RY I N T E R FAC E AM I M O D E L B U I L D E R PAM3 from
ADS2023U1

RLM (Level Mismatch Ratio)

SNDR (Signal to Noise Distortion Ratio)

Build
New PAM3, PAM4 Modulation Custom CTLE Setup

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Mixed-Domain Pre-Layout Solution

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Topics Covered

• Quick recap on memory buses

• Mixed-domain channel modeling approach
• CA/Data Bus Pre-Layout Builder using mixed-domain channel modeling approach
• Validation test cases - Pre-Layout memory bus vs. Post-Layout memory bus
• Design to Test – Compliance Solution

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Quick Recap on Memory Buses
Highlights – It is all about channels, but a lot!

• Point-to-Point connection
DRAM
• Data Bus:
• Data signal : DQ, single ended 8 Bytes 64 data signals
• Data strobe : DQS, differential 8 strobe signals
• Data mask : DM, single ended 8 data mask signals

• Fly-by connection
• Command Address Bus: DIMM Board
• Address signal : A0~A17, single ended signals
• Command, Clock signal : CK_t, CK_c, differential
• Control signal: CS

• Increased speed grade for next generation memories

• 6800Mbps for DDR5
• Equalizations: 4-tap DFE, CTLE, etc
Channel loss, Grounding, ISI, Crosstalk,
Reflection, Termination, etc… Fly-By connection
33
Courtesy of HP
 What Are Typical Methods Used for Modeling the Channels?
System Design (Pre-Layout) Workflow vs. Verification (Post-Layout) Workflow

System Design - Pre-Layout Workflow (no layout is done…)

• Rule of thumb Speed
Slot 1 Slot 2
Raw Card D 1R x8 Small outline DIMM
• Equation-based circuit models
• Static cross-sectional models
• Quasi-static electro-magnetic models Pseudo open Drain
VDD „1“ (no DC current)

• … VDD

• Hybrid EM solvers „0“

VSS

• Full-wave 3D electro-magnetic models

• FEM, FDTD, FIT, MoM, etc
Accuracy
• …
Verification - Post-Layout (layout is done and available)

34
What is Mixed-Domain Modeling Approach?
For System Design Pre-Layout Workflow

• Typical high speed channel observations:

• Transmission lines are typically well designed and constructed, meaning good grounding, no void, and no slots
• Vias are generally main source of SI culprits including cross-talk and reflections, and hard to make the via
impedance matched for all frequency bands. This is where full-wave EM modeling is necessary
• Quasi-static EM models are very accurate to represent typical transmission line structures

• Mixed-domain channel modeling → Quasi-static EM transmission models +Fullwave via EM models

• Very practical and highly accurate modeling solution for the pre-layout workflow

Quasi-static EM, stripline

35
 Etch effects

Controlled Line Impedance Designer (CILD)

Quasi-Static EM solution to analyze and synthesize transmission line (bus) structures

• Single-ended and differential transmission lines

• Reflect etch effects

• Quasi-static electromagnetic field numerical solution
• Extraction of odd-mode, even-mode, common and
differential impedance
• Calculation of attenuation, delay, propagation velocity,
effective dielectric constant, etc
• Conversion into a bus structure (Line Type models)

36
 ADS Symbol generated

Via Designer
FEM (Finite Element Method) Full Wave EM Solver

• Accurate parameterized via

models in pre-layout simulation
environment
• Via arrays for memory bus vias
• Breakout-feed vias – for memory
command address buses
• Micro vias – stacked and
staggered vias
• Custom stitching via layers
More Modeling Options:
• Simple via arrays
• Teardrop pads
• Conical lasered vias
• Diving boards

37
Validation Data 1: Mixed-Domain Channel Modeling Approach
DQ Line Example
Mixed-Domain Representation 3D EM Via
3D EM Via
CILD, stripline

Red = Measured data

38
Green = Mixed-domain
 Validation Data 2: Mixed-Domain Channel Modeling Approach
DQ Strobe Line Example
SDD21 SDD22
3D EM Via

TDR – SDD11
3D EM Via

Measurement: GigaTest Lab

Red = Measured data

39
Green = Mixed-domain
 Validation Data 3: Mixed-Domain Channel Modeling Approach
Differential Signals
SCC21 SDD21

• Measured and compared up to 40GHz

3D EM Via

SDD11 TDR SDD11

CILD, stripline

Red = Measured data

40
Green = Mixed-domain
CA/Data Bus Pre-Layout Builder Using
Mixed-Domain Channel Modeling Approach

DRAM

Efficient construction of
41
pre-layout memory bus
CA/Data Bus Pre-Layout Builder
Command Address (CA) and Data Bus Pre-Layout Modeling Workflow

Line Via Line

42
Things to Know
CILD for transmission lines and S-para/emmodels for Via
Via without breakout feed

out
• Substrate definition - Required
in
• Buses and vias require a stack-up or substrate definition to start with

• CILD models - Required

• Build various data and CA buses using CILD
• The models built are automatically listed
• If the model you want is not listed, create a new one on the fly Via with breakout feed
• Via models - Required
• Short – Used for a simple model construction and an evaluation of the via
out in
impact to the design
• S-parameter data – bring 3rd party data or measurements
• emmodel – a workflow with Via Designer
Break-out

43
Examples : DIMM Case
Data Bus - One Channel 2 DIMM System

• Tips:
• Use “via with breakout feed” to make a
connection to the first DIMM, D0
• Use RefDes selection (highlighted “D1” in the
table) to assign D1 as for the last RefDes
• In this case, the last via has a psuedo-
breakout, as in it connects to just the top layer.

Old Way New Way

44
 • Tips:
• All vias have breakout feed
Examples : Embedded Case
• The end line connects to Term
Embedded CA Bus with 4 DRAMs

45
Examples : Clam-Shell Case
Clam-Shell Configuration with Term

• Tips:
• Use “via with breakout feed” and enable “Clam
shell topology”
• Use each RefDes, M0 and M1, to connect to
the two DRAMs
• Make sure the emmodel port number ordering
matches to the connection

46
Validation Test Cases

Xilinx Versal Platform

47
Case1 – Byte1 (DQ0~DQ7,DQS0 and DM0) on Platform Board
Simulation Structure, Setup, and Results
With 3D EM Model (SIPro)
Mixed-Domain Pre-Layout
FPGA
Vias around BGA

DQ3

With Mixed-Domain Model

DQ3
Vias around DIMM
Verification Post-Layout

DRAM

48
Case1 – Byte1 (DQ0~DQ7,DQS0 and DM0) on Platform Board
Mixed-Domain System Design Pre-Layout Data Bus (w/ CA/Data Bus Pre-Layout Builder)

49
Case1 – Byte1 (DQ0~DQ7,DQS0 and DM0) on Platform Board
Verification (Post-Layout) Data Bus (w/ SIPro)

50
Case1 – Byte1 (DQ0~DQ7,DQS0 and DM0) on Platform Board DQ1
Comparison Notes: Mixed-Domain (CA/DataBus Pre-Layout Builder) vs. SIPro DQ3

• In general, very good co-relation between pre- (mixed-domain) vs. post-layout results
• However, the two should have some differences due to :
• Pre-layout models are all straight transmission line, meaning no skew, no change on impedance
• Post-layout models are all physical models with real skew and impedance changes (more reflections)

• Summary data for Byte1 results

Best case DQ Worst case DQ Best eye height Worst eye height Best eye width Worst eye width

DQ3 DQ1 3mV 52mV 0 ps 6.3ps

• Averaged comparison
• 18.2mV for eye height and 2.3ps for eye width

Mixed-Domain Pre-Layout Verification Post-Layout 51

Case 2 – Byte7 (DQ48~DQ55, DQS6, and DM6) on Full System
Simulation Structure, Setup, and Results Verification Post-Layout

2.2mV for Eye Height

FPGA 3.7ps for Eye Width

Mixed-Domain Pre-Layout

DIMM Connector

DRAM

52
Case 2 – Byte7 (DQ48~DQ55, DQS6, and DM6) on Full System
Mixed-Domain System Design Pre-Layout vs Post-Layout Data Bus Comparison

Mixed Domain

SIPro 53
 Case 3 – Command Address Control Bus on Platform Board
Simulation Structure, Setup, and Results
Verification Post-Layout

Vias around BGA

FPGA
A0

50.mV for Eye Height

A1
Mixed-Domain Pre-Layout 6.9ps for Eye Width
CK

CKE
CK A17

A2 DIMM Connector Vias around DIMM

A7

A13
CKE
A13
DRAM CK
A1
U10

54
Case 3 – Command Address Control Bus on Platform Board
Mixed-Domain System Design Pre-Layout vs Post-Layout CAC Bus Comparison

Mixed Domain

SIPro 55
Case 4 – Fly-By CAC (A0~A13, CLK, CS, and CKE) on Full System
Simulation Structure, Setup, and Results

5mV~57mV for Eye Height

0.4ps~46.9ps for Eye Width Verification Post-Layout

Mixed-Domain Pre-Layout
FPGA Xilinx Versal Platform

DIMM Connector

DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM Term

56
 Case 4 – Fly-By CAC (A0~A13, CLK, CS, and CKE) on Full System
Mixed-Domain System Design Pre-Layout vs Post-Layout CAC Bus Comparison

@U1 @U2 @U3 @U4 @U5 @U7 @U8 @U9 @U10

EH = 35mv EH = 5mv EH = 31mv EH = 17mv Mixed Domain EH = 16mv EH = 57mv EH = 45mv EH = 27mv
EW = 0.4ps EW = 2.6ps EW = 34.3ps EW = 6.2ps EH = 20mv EW = 9.4ps EW = 18.8ps EW = 9.3ps EW = 46.9ps
EW = 28.1ps

SIPro
57
Demo

58
Summary

59
Summary of Supported Memory Interfaces
Today
Best design platform for Memory Systems

Nov 2022

Pathfinding
Interfaces

PAM3,
PAM4,
PAM6
PAM8,
PAM16

One Tool, Multiple Standards Covered! 60

Workflow Becomes Even Smarter!
SIMPLER & EASIER & LESS ERROR PRONE
DRAM DRAM DRAM DRAM
Old Way

Smart Bus Wires

Memory
Controller PCB
New CA
Way Termination

Smart Components

Memory
Probe

All signals automatically exposed

61
VRM & PDN Design exploration & compliance tests
Design With Confidence!
WHILE MAKING EYES WIDE OPEN!

Topics Covered
LPDDR5 – 6400 LPDDR5 – 6400
No Jitter w/ Xtalk 15ps Rj & 0.1DCD w/ Xtalk

LPDDR5 – 6400
After 1-Tap DFE
Equalization w/
Jitter tracking Single Ended IBIS-AMI Modeling w/ forwarded clocking +
DDR Bus Sim + Accurate EM modeling of the PCB =
Confident Prediction of Margin to Mask
Keysight Webinar Sept 2021 62 62
SerDes Solutions

63
High Speed SerDes Link Design Challenges
• Channel loss and ISI
• Jitter and noise
• Crosstalk
• Compression
• Low BER target (e. g. 10−12 )

64
Channel Loss and Inter-symbol-interference (ISI)
• Channel loss attenuates high frequency parts of the signal. Loss grows exponentially with data rate.
• Pulse is broadened in time by channel loss. The higher the loss, the broader the pulse in UI after the channel.
• Signal of current bit interferes with neighboring bits, reducing the eye open.

Channel insertion loss Pulse before and after channel ISI

10dB loss 15dB loss 20dB loss

65
Data Rate Evolution
Example - PCI Express

• Interval between PCIe Generations Reduced by 1/3 2021-2022

• Increased speed means Increased complexity 2019
PCIe 6.0 (64 GT/s)

• New measurement challenges are here PCIe 5.0 (32 GT/s)

2017
• No sign of slowing… PCIe 4.0 (16 GT/s)

2010
PCIe 3.0 (8 GT/s)

2006
PCIe 2.0 (5 GT/s)

2003
PCIe 1.0 (2.5 GT/s)

© Keysight Technologies 2022 66

Jitter and Noise
• Jitter: timing impairment
• Noise: voltage impairment

Noise

Jitter

• Jitter types: DCD, DJ, SJ, and RJ

• Tx jitter is caused by internal clock jitter and power supply noise
• Rx jitter is caused by ISI, Tx jitter, crosstalk and noise
67
Crosstalk
Far-end (FEXT) and near-end (NEXT) aggressors

Channel

Rx4 Tx4 NEXT aggressor

FEXT aggressor Tx2 Rx2

Victim Tx Tx1 Rx1 Victim Rx

FEXT aggressor
Tx3 Rx3

Rx5 Tx5 NEXT aggressor

68
Technologies Employed to Mitigate Signal Impairments
• Tx FFE: boost high frequency components to compensate channel loss
• Rx CTLE and FFE: boost high frequency components to compensate channel loss
• Rx DFE: cancel post-cursors
• Rx CDR: track and cancel jitter when sampling the signal
• Repeater
• Active devices placed the middle of the channel to compensate the upstream channel loss in the input
signal before re-transmitting it into the downstream channel
• Two types: redriver and retimer
• Redriver: output is continuously driven by the input analog signal. Does not sample the signal.
• Retimer: output is triggered by digital data recovered by data sampling. Transition edges are reformed by
the retimer Tx.
• PAM
• Combines multiple binary bits into one multi-level symbol (e. g. PAM4 combines two bits into one 4-level
symbol)
• Reduces symbol rate, hence lower loss (e. g. PAM4 symbol rate = half of NRZ bit rate)
69
 Multi-Level Signaling
MAKE YOUR CHANNEL GO FURTHER!

• PAM-4 used in multiple standards

• Some standards are already using modulation other than
PAM-4
• Channel reach can be extended further by changing
modulation scheme
• Let’s use this Channel as an example:
The Channel has 22.5 dB loss at 10 GHz

70
Typical SerDes Link Architecture
• Tx implements FFE
• Rx implements CTLE, AGC, DFE and CDR

Rx EQ & CDR
Tx EQ
Output Input DFE
FFE CTLE AGC
buffer buffer CDR

71
ADS SerDes Link Analysis Solution
• Requirements for high-speed link analysis
• Capture Tx and Rx functionalities including EQ, AGC and CDR
• Simulate millions of bits to reliably predict link performance at low BER

• ADS SerDes Simulation Solution

• AMI-based end-to-end channel simulation
• AMI Model Builder inside ADS (not SVU)
• Spec-based reference models and channels
• Built-in eye measurements and link to FlexDCA

72
Overview of AMI (Algorithmic Modeling Interface)
• AMI is a behavioral modeling standard for SerDes transceivers
• AMI addresses following challenges in high-speed link analyses
• Capture Tx and Rx functionalities in end-to-end channel simulations
• Achieve high simulation throughput to enable computations of millions of bits
• Protect IC vendors' IP
• Model interoperability and portability

• Each AMI model is a combination of an analog model and an algorithmic model and consists
of three files (.ibs, .ami and DLL files)
• Analog model is specified in the .ibs file
• DLL is the executable of the algorithmic model, whose parameters are specified in the .ami file

DLL .ibs .ibs DLL

Tx model Rx model
73
IBIS File
• Each pin is associated with a Model
• Each model specifies analog
parameters and algorithmic model files
• DLL/.so file name, .ami file name and
DLL/.so compiler version of the
algorithmic model are specific under
the [Algorithmic Model] keyword

DLL/.so file name .ami file name

DLL/.so compiler version

74
Analog Model
• Analog model is an IBIS model specified by the .ibs file
• For Tx, IBIS model represents output impedance and transition slew rates
• Tx output impedance is specified by I-V tables under [Pullup] and [Pulldown] keywords and the
C_comp parameter
• Tx pullup and pulldown waveforms are specified by V-T tables under [Rising Waveform] and
[Falling Waveform] keywords, respectively
C_comp 0.4pF 0.39pF 0.41pF

[Pullup]
|Voltage I(typ) I(min) I(max)
-0.8V 20mA 20mA 20mA
-0.4V 10mA 10mA 10mA
0V 0.0mA 0.0mA 0.0mA
0.4V -10mA -10mA -10mA
0.8V -20mA -20mA -20mA

[Rising Waveform]
|time V(typ) V(min) V(max)
0.0ps 0.533V 0.507V 0.56V
50.0ps 0.533V 0.507V 0.56V
150.0ps 1.20V 1.14V 1.26V
160.0ps 1.20V 1.14V 1.26V
IBIS output model 75
Analog Model (cont’d)
• For Rx, IBIS model represents termination
• Rx input impedance is specified by I-V tables under [POWER Clamp] and [GND Clamp]
keywords and the C_comp parameter
• Three ways to include packages in IBIS model
• R_pkg, L_pkg, C_pkg parameters
• Package models
• EBD (Electrical Board Description)

C_comp 0.4pF 0.39pF 0.41pF

[POWER Clamp]
|Voltage I(typ) I(min) I(max)
-0.8V 20mA 20mA 20mA
-0.4V 10mA 10mA 10mA
0V 0.0mA 0.0mA 0.0mA
0.4V -10mA -10mA -10mA
0.8V -20mA -20mA -20mA

IBIS input model

76
Algorithmic Model
• The DLL executable supports a set of standard C function
(Reserved_Parameters
APIs that models Tx/Rx functionalities including gain, (Init_Returns_Impulse (Usage Info) (Type Boolean) (Default True)
equalization and CDR (Description "Init_Returns_Impulse False"))
(GetWave_Exists (Usage Info) (Type Boolean) (Default True)
• Two most important APIs: AMI_Init and AMI_GetWave (Description “Model has GetWave function"))
(Max_Init_Aggressors (Usage Info) (Type Integer) (Default 1000000)
(Description "Max number of aggressors allowed by model"))
• Algorithmic model parameters are specified in the .ami file (Ignore_Bits (Usage Info) (Type Integer) (Default 1000)
(Description “Model ramp-up time”))
• Two sections of parameters: Reserved and (Rx_Rj (Usage Info) (Type UI) (Corner 0.005 0.006 0.004)
(Description “Rx random jitter”))
Model_Specific )
(Model_Specific
• Reserved parameters are defined by the AMI standard (CTLE_DCgain (Usage In) (Type Float) (Format Value -3)
(Description "CTLE DC gain in dB"))
(CTLE_RealPoles
• Model_Specific parameters are invented by model (0 (Usage In) (Type Tap) (Format Value -1.25e+08)
developers at their own discretion without restriction on (Description "CTLE poles 0 in Hz"))
(1 (Usage In) (Type Tap) (Format Value -5e+08)
parameter number or name (Description "CTLE poles 1 in Hz"))
)
(CTLE_RealZeros
(0 (Usage In) (Type Tap) (Format Value -8.75e+07)
(Description "CTLE zeros 0 in Hz"))
)
)

77
AMI_Init
• Input:
• Parameter values (written in a string argument)
• Channel impulse response

• Output: modified impulse response that includes effects of gain and equalization
• AMI_Init must be called before simulation. The function performs
• Model initialization
• Optimization on gain, equalizer, etc. based on input impulse response

78
AMI_GetWave
• Data flow block
• Input: signal waveform
• Output:
• Signal waveform
• Rx model can also return clock times recovered by CDR
clock times
• Input and output waveforms are differential signals
• AMI_GetWave models Tx/Rx behaviors including gain, equalizer and CDR

79
AMI Simulation Methodology
• Assumptions
• The analog channel (AC), which comprises Tx analog, channel and Rx analog, is LTI
• Tx algorithmic (DLL) output impedance is zero
• Rx algorithmic (DLL) input impedance is infinite

• Simulation approach
• The analog channel is represented by an impulse response
• Analog channel output (i.e., Rx DLL input) = Tx DLL output ∗ analog channel impulse response
• Two simulation modes: bit-by-bit and statistical

Analog channel (AC) impulse response

Tx Rx
Tx algorithmic Analog Analog Rx algorithmic
(DLL) (IBIS) (IBIS) (DLL)

clock times

80
Comparison Between Bit-by-bit and Statistical Simulations

Number of BER accuracy Simulation ISI Tx and Rx Adaptation Optimization Compression

bits low bound speed AGC & EQ in AMI_Init
Bit-by-bit 1~100M 10−6~10−8 ~1M bits/min Yes Yes Yes Yes Yes
w/o extrapolation
Statistical Infinite 10−∞ Completes in Yes Yes No Yes No
mins

(cont’d)
Rx CDR Tx jitter and Rx jitter Rx noise Crosstalk Application
amplification
Bit-by-bit Yes Yes Yes Yes Yes Final accurate analysis and verification

Statistical No Yes Yes Yes Yes Quick optimization of linear EQ

81
ADS AMI Model Builder

• Channel Simulator loads 3rd party AMI models

• If model not available, user can build models in ADS (Wizard driven AMI Model Builder)

82
ADS AMI Model Builder Function Blocks
• FFE, CTLE, DFE, AGC, Gain, CDR, SSC, RLM, SNDR

83
Feed Forward Equalizer (FFE) Model
• Tx uses FFE to compensate downstream channel loss

3-tap FFE example

Without FFE With FFE

84
Continuous Time Linear Equalizer (CTLE) Model
• Rx uses CTLE to compensate channel loss

2-pole 1-zero CTLE example

𝑠 + 𝜔𝑝1 𝐴𝐷𝐶
𝐻 𝑠 = 𝜔𝑝2
(𝑠 + 𝜔𝑝1 )(𝑠 + 𝜔𝑝2 )

Without CTLE With CTLE

85
Decision Feedback Equalizer (DFE) Model
• Rx uses DFE to cancel ISI post-cursors
• DFE is adaptive

Without DFE With DFE DFE adaptation

C3
C2

C1

86
Clock Data Recovery (CDR) Model
• In SerDes channels clock is embedded in data signal and recovered by CDR in Rx
• CDR tracks and cancels low frequency jitter

CDR jitter transfer function

Without CDR With CDR

87
Nonlinear Gain Model
• Gain compression can be modeled by the hyperbolic tangent function

𝑥
𝑦 = 𝛼 ∙ tanh
𝛼

Without compression With compression

88
Advanced Tx Model: PAM Level Mismatch Ratio (RLM)
PAM4 example
1/2

1/6

-1/6

-1/2

Without RLM With RLM

89
Advanced Tx Model: PAM Signal-to-Noise-and-Distortion Ratio (SNDR)
2
𝑝𝑚𝑎𝑥
𝑆𝑁𝐷𝑅 = 10𝑙𝑜𝑔10
𝜎𝑒2 + 𝜎𝑛2
• 𝑝𝑚𝑎𝑥 : maximum Tx output signal amplitude
• 𝜎𝑒 : RMS of Tx output nonlinear distortion
• 𝜎𝑛 : RMS of Tx output noise

Without Tx noise With 12dB Tx noise

PAM4 example
90
Advanced Tx Model: Spread Spectrum Clocking (SSC)
SSC is applied in USB to reduce EMI

Frequency vs time in Tx AMI_GetWave output signal

Date rate: 10 Gbps

SSC down spread rate: 30 kHz
SSC down spread range: 0.4%

91
Starting Tx_AMI and Rx_AMI with AMI Model Builder
ADS2023 Update 1

• Easier and efficient AMI workflow from ADS2023 Update 1

• “Double click pops” up a new dialog and links the AMI modeler
Double-Click
• Same use-model with an existing AMI models

92
PCIe Typical Workflow
With PCIe Solution Kit

• Build the channel with PCIe Reference Channels

• Evaluate the system design with the generic transmitters and receivers (Tx_Diff & Rx_Diff)
• Build the transmitter and receiver AMI models with PCIe AMI Modeler, and replace the
generic Tx and Rx with them
• Evaluate the system with the custom Tx and Rx AMI models
• Or replace the generic Tx and Rx models with the spec-based AMI models
• Evaluate the system performance if it meets the specification

• PCIe Solution Kit :

• PCIe Reference Channels, PCIe AMI Modeler for PCIe G5 , and Spec-Based AMI Models for G5
and G6
93
PCIe Gen5 Reference Channel
Easy drop-in PCIe Gen5 channel models

• Provides validated PCIe Gen5 reference channel models

• Add-In-Card, CBB/CLB, Connector, and Package models

• With visual aid for an easier model selection

Add-In-Card CBB/CLB Connector Package

94
New PCIe Gen6 Reference Channel
A I C , C B B / C L B , C O N N E C T O R , PA C K A G E M O D E L S

• Provides PCIe Gen6 reference channel models ( Single-Lane and 6-Lane models)
• Add-In-Card, CBB/CLB, Connector, and Package models

• Visual aid for a model selection

Add-In-Card CBB/CLB Connector Package

95
New PCIe Gen6 CTLE Presets
Latest Generation CTLE Presets added

• PCIe Gen6 CTLE transfer function

• PCIe Gen6 CTLE presets

96
 Don’t have AMI model for PCIe Gen6? No problem! You
PCIe Gen5 & Gen6 AMI Modeler can build your own AMI models easily and quickly!

P A M 4 M O D U L AT I O N A N D W E I G H T E D S U M O F D F E T A P S
Memory Interface AMI Modeler

• Builds PCIe G6 PAM4 AMI Models for Tx and Rx

• Supports weighted sum of DFE taps
• Wizard driven model generation workflow PCIe AMI Modeler USB AMI Modeler

CTLE AGC
.ami
Comp DFE CDR .dll or .so
Build .ibs
.conf (re-usable)

Tx Model Tab

97
Example – PCIe G5 Rx AMI Model

CTLE with 7 presets

DFE with h1/h0 limit

98
PCIe 5.0: End to End Simulation with spec-based PCIe 5.0 models

99
PCIe 6.0: End-to-End Simulation with spec-based models

100
PCIe 6.0 Simulation vs. Measurement Correlation

• PCIe 6.0 DesignWare® PHY simulation

101
PCIe 6.0 Simulation vs. Measurement Correlation

ADS2022U2 Silicon Eye

Synopsys
DesignWare®
PCIe 6.0 PHY IP

102
 Physical Layer- Physical Layer- Physical Layer- Physical Layer- Protocol Layer Test
System Simulation Interconnect Design Transmitter Test Receiver Test

1
ADS Design Software ADS Design Software
M8040A High Performance BERT
P5551A PCIe 5.0 Exerciser

0 UXR-Series Real-Time w/ integrated CDR + M8054A

Oscilloscopes Interference Source
3

N1000A DCA-X/TDR
SIPro/PIPro PCI Express TX Electrical Substitute PCIe BASE Channel
compliance software P5552A PCIe 5.0 Analyzer
board

N5227B PNA w/ PLTS FLEX-PLL TX-PLL Phase Jitter N5991 PCIe RX Test software
Simulation to Measurement Measurement SW
Correlation P5563A Test Backplane

Complete system simulation Deep protocol analysis capability with

Verify PCIe compliant channels UXR-Series & Z-Series Comprehensive RX Testing with M8000
from pre-layout analysis to post-layout root complex and endpoint emulation*
and return loss compliance Real-Time Oscilloscopes BERT Series
extraction

*Protocol 6.0 and CXL will begin shipping103

in 2023 with
an upgrade path from PCIe 5.0 to PCIe 6.0 platforms.
 Don’t have AMI model for USB for PAM3 ? No problem!
You can build your own AMI models easily and quickly!
USB AMI Modeler

Memory Interface AMI Modeler

• Builds USB for PAM3 AMI Models for Tx and Rx

• Wizard driven model generation workflow

PCIe AMI Modeler USB for PAM3 AMI Modeler

.ami
.dll or .so
Build .ibs
Tx or Rx (PAM3)
CTLE AGC Comp DFE CDR .conf (re-usable)

104
 Don’t have AMI model for USB, either PAM3 and NRZ? No problem!
You can build your own AMI models easily and quickly!
USB NRZ AMI Modeler
N R Z M O D U L AT I O N & S P R E A D S P E C T R U M C L O C K I N G
Memory Interface AMI Modeler

• Builds USB NRZ AMI Models for Tx and Rx

• Wizard driven model generation workflow
PCIe AMI Modeler USB AMI Modeler

CTLE
.ami
.dll or .so
Tx or Rx (PAM3+NRZ) Build .ibs
AGC Comp DFE CDR .conf (re-usable)
SSC for Tx

105
New USB Reference Channel
Host PCB, Cable, and Device PCB models

• Provides USB reference channel modeled at Nyquist Freq for Insertion Loss
• Host PCB, Cable, and Device PCB

• Visual aid for a model selection

Host PCB Cable Device PCB

106
USB4 Gen3, 20 Gbps
PathWave ADS Testbench – Spec Compliant
TX/RX Model, Spec Channel Model

© Keysight Technologies 2022 107

USB4 Gen2, 10 Gbps
PathWave ADS Testbench – Spec Compliant
TX/RX Model, Spec Channel Model

© Keysight Technologies 2022 108

USB4 Gen3, 20 Gbps
PathWave ADS Testbench, Synopsys DesignWare® USB4 PHY IP IBIS-AMI model

109
USB4 G3n3, 20 Gbps: Measurements on TP3
Hardware Configuration

• The DUT transmitter was configured to output

PRBS31 on all lanes with SSC turned on.
• Preset used: P2 (Pre-shoot: 0dB and De-emphasis: -
3.6dB).
• Material used:
• Synopsys DesignWare® USB4 PHY IP Board
• Apple Thunderbolt 3 (USB-C) Cable (0.8m)
• USB4 CIO Receptacle TPA WilderTech (Part No. 600-
1191-200) (TX0_N/P)
• USB4 TypeC ISI Card A 1.5 RevA
• 2.92mm to SMP Coax Cables (p/n 415-0080-008)
• 200mm BullsEye to BullsEye Loopback Cable (NR-RSP-
218114-01-BEYE)

• The cables from the test fixture to the scope were

de-embedded.

110
Simulation to Measurement Correlation

ADS2022U2 Infiniium UXR Oscilloscope

Synopsys
DesignWare®
USB4 PHY

111
Keysight Type-C Solutions Matrix
Design Simulation, Protocol Decode, Live Link Debug, USB-PD, RF, Channel Characterization, SBU, USB, Thunderbolt, DisplayPort

Physical Layer Transmitter Test Interconnect Test Receiver Test

System Simulation Active Cable Test Return Loss Test Active Cable Test

Automated Automated
Standards Test Standards Test
Software E5080B ENA with S96011A Software
Enhanced TDR software
ADS Design Software

UXR M8000 J-BERT

Infiniium <200fs RMS
Scope NRZ/PAM-X
<1mV RMS SSC
<25fs RMS Jitter, CMI, DMI

SIPro/PIPro

Cable/Connector RX Test fixture

TX Test Fixture Test Fixture

Active/Passive
Cable Tx
Simulation to measurement Tx
correlation Rx

112
 Don’t have AMI model for Ethernet? No problem! You
can build your own AMI models easily and quickly!
Ethernet AMI Modeler
NRZ Modulation & Spread Spectrum clocking
Memory Interface AMI Modeler
• Builds PAM4 Ethernet AMI Models for Tx and Rx
• Wizard driven model generation workflow

PCIe AMI Modeler Ethernet AMI Modeler

CDR .ami
Tx or Rx (PAM4) CTLE .dll or .so
FFE DFE
Build .ibs
AGC Comp
DFE .conf (re-usable)

Tx Model Tab

113
Tx_Waveform_AMI
• Application: pass measured signal at the Rx input to the Rx AMI model to calculate Rx post-
equalization signal, which can not be measured directly due to the lack of access to the signal
• Challenges:
• Rx AMI_Init requires upstream impulse response as input
• Init-only Rx model does not have GetWave to process waveform

• Solution: Tx_Waveform_AMI

114
Tx_Waveform_AMI (cont’d)
• Load the measured waveform file and the corresponding bit (decoder) file into the Tx_Waveform_AMI
component
• Based on the waveform and the bit sequence ADS solves the impulse response and passes it into the
Rx AMI_Init
• If the Rx has GetWave, the measured waveform is passed into the Rx GetWave to calculate the Rx
output waveform and clock times
• If the Rx is Init-only model, the impulse response returned by the Rx AMI_Init is convolved with the bit
sequence to calculate the Rx output waveform
• No restriction on the bit pattern of the waveform
• Waveform and bit files do not need to start or end at the same bit
Measured signal at Rx input After Rx CTLE

115
Tx_Waveform_AMI (cont’d)
Package effect
• Since the waveform is measured at Rx package pins, the Rx package effect needs to be included.
• If the Rx model has package model, connect Rx_AMI directly to Tx_Waveform_AMI

• If the Rx model does not have package model, place the package model between Rx_AMI and
Tx_Waveform_AMI

• Turn on Include channel effect in Tx_Waveform_AMI. The package effect will be applied to the impulse
response input to the Rx AMI_Init and to the measured waveform input to the Rx GetWave
116
Demo

117
Thank you