Ultralow Power Energy Harvester PMUs

with MPPT and Charge Management

Data Sheet ADP5091/ADP5092
FEATURES TYPICAL APPLICATION CIRCUIT
Boost regulator with maximum power point tracking (MPPT) REG_D0
ADP5091 LLD TO MCU
with dynamic sensing or no sensing mode REG_D1 REG_OUT
FROM MCU
Hysteresis mode for best ultralight load efficiency VID HYSTERESIS REG_FB
Operating quiescent current of SYS pin (VIN > VCBP ≥ VMINOP): 510 nA REGULATOR
AND LDO
PIN
Sleeping quiescent current of SYS pin (VCBP < VMINOP): 390 nA SW
PGOOD TO MCU

COLD START SYS SYSTEM

Input voltage operating range: 0.08 V to 3.3 V VIN CHARGE PUMP LOAD

Fast cold start from 380 mV (typical) with charge pump

Programmable shutdown point on MINOP pin based on the MPPT BAT
+ RECHARGEABLE
BATTERY OR
input open circuit voltage (OCV) CBP
MPPT BOOST
CONTROL REGULATOR –
SUPERCAP

150 mA regulated output from 1.5 V to 3.6 V REF

Battery terminal charging threshold (2.2 V to 5.2 V) to

MINOP CHARGE CONTROL
support charging storage elements AND
POWER PATH
SETSD
SETPG
Optional BACK_UP power path management MANAGEMENT

Radio frequency (RF) transmission conducive to shutting FROM MCU DIS_SW SETHYST

down the switcher temporarily via microcontroller unit BACK_UP

SETBK
TERM
(MCU) communication OPTIONAL +
PRIMARY – AGND PGND

14145-001
BATTERY

APPLICATIONS
Photovoltaic (PV) cell energy harvesting Figure 1.
Thermoelectric generators (TEGs) energy harvesting
Industrial monitoring
Self powered wireless sensor devices
Portable and wearable devices with energy harvesting

GENERAL DESCRIPTION
The ADP5091/ADP5092 are intelligent, integrated energy As a low light indicator for a microprocessor, the LLD pin of the
harvesting, ultralow power management unit (PMU) solutions ADP5091 is the MINOP comparator output. However, the
that convert dc power from PV cells or TEGs. These devices charge REG_GOOD flag of the ADP5092 monitors the REG_OUT
storage elements such as rechargeable Li-Ion batteries, thin film voltage. In addition, the DIS_SW pin can temporarily shut down
batteries, super capacitors, or conventional capacitors, and the boost regulator and is RF transmission friendly.
power up small electronic devices and battery free systems. The charging control function of the ADP5091/ADP5092 protects
The ADP5091/ADP5092 provide efficient conversion of the the rechargeable energy storage, which is achieved by monitoring
harvested limited power from a 6 µW to 600 mW range with the battery voltage with the programmable charging termination
submicrowatt operation losses. With the internal cold start circuit, voltage and the shutdown discharging voltage. In addition, a
the regulator can start operating at an input voltage as low as programmable PGOOD flag monitors the SYS voltage.
380 mV. After cold startup, the regulator is functional at an An optional primary cell battery can be connected and managed
input voltage range of 0.08 V to 3.3 V. An additional 150 mA by an integrated power path management control block that is
regulated output can be programmed by an external resistor programmable to switch the power source from the energy
divider or the VID pin. harvester, rechargeable battery, and primary cell battery.
The MPPT control keeps the input voltage ripple in a fixed range to The ADP5091/ADP5092 are available in a 24-lead LFCSP and
maintain stable dc-to-dc boost conversion. The dynamic sensing are rated for a −40°C to +125°C temperature range.
mode and no sensing mode, both programming regulation points
of the input voltage, allow extraction of the highest possible energy
from the harvester. A programmable minimum operation
threshold enables boost shutdown during a low input condition.

Rev. A Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
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Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADP5091/ADP5092 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Regulated Output Configuration ............................................. 17
Applications ....................................................................................... 1 REG_GOOD (ADP5092 Only) ................................................ 18
Typical Application Circuit ............................................................. 1 Energy Storage Charge Management ...................................... 18
General Description ......................................................................... 1 Backup Storage Path................................................................... 18
Revision History ............................................................................... 2 Backup and BAT Selection Threshold ..................................... 19
Detailed Functional Block Diagram .............................................. 3 Battery Overcharging Protection ............................................. 19
Specifications..................................................................................... 4 Battery Discharging Protection ................................................ 19
Regulated Output Specifications ................................................ 6 Power Good (PGOOD) ............................................................. 20
Absolute Maximum Ratings ............................................................ 7 Power Path Working Flow......................................................... 20
Thermal Resistance ...................................................................... 7 Current-Limit and Short-Circuit Protection.............................. 20
ESD Caution .................................................................................. 7 Thermal Shutdown .................................................................... 21
Pin Configurations and Function Descriptions ........................... 8 Applications Information .............................................................. 23
Typical Performance Characteristics ........................................... 10 Energy Harvester Selection ....................................................... 23
Theory of Operation ...................................................................... 16 Energy Storage Element Selection ........................................... 23
Fast Cold Start-Up Circuit (VSYS < VSYS_TH, VIN > VIN_COLD) ... 16 Inductor Selection ...................................................................... 23
Main Boost Regulator (VBAT_TERM > VSYS > VSYS_TH) ..................... 16 Capacitor Selection .................................................................... 24
VIN Open Circuit and MPPT .................................................. 16 Layout and Assembly Considerations ..................................... 24
Minimum Operation Threshold Function ............................. 17 Typical Application Circuits ..................................................... 25
Disabling Boost ........................................................................... 17 Factory Programmable Options ................................................... 27
Regulated Output Working Mode ............................................ 17 Outline Dimensions ....................................................................... 28
REG_D0 and REG_D1 .............................................................. 17 Ordering Guide .......................................................................... 28

REVISION HISTORY
5/2017—Rev. 0 to Rev. A
Changes to Figure 2 .......................................................................... 3
Changes to Figure 7, Figure 10, Figure 7 Caption, and Figure 10
Caption ............................................................................................. 10
Changes to Figure 11 and Figure 11 Caption ............................. 11
Changed CP-24-10 to CP-24-14 .................................. Throughout
Updated Outline Dimensions ....................................................... 28
Changes to Ordering Guide .......................................................... 28

7/2016—Revision 0: Initial Version

Rev. A | Page 2 of 28
Data Sheet ADP5091/ADP5092

DETAILED FUNCTIONAL BLOCK DIAGRAM

ADP5091/ADP5092

SYS
LDO
CSYS RSYS
REG_SWITCHES
REG_OUT BACK_UP
+
–
REG_FB
BACK_UP BK
REG_D0 SWITCHES BACK_UP
HYSTERESIS CONTROL
REG_D1 REGULATOR SYS SWITCH
AND LDO
VID BAT SWITCHES
PHOTOVOLTAIC L
CELL SW BAT
+
+ HS SD
–
– CIN BAT
VIN COLD START
CHARGE PUMP LS BK
REF
ROC2 SYS

MPPT
MPPT CONTROLLER TERM_REF
SETSD
ROC1 EN_BST CHARGE SD
CBP CONTROL
BOOST AND
CONTROLLER POWER PATH PGOOD
MANAGEMENT PG
MINOP SETPG
PG
SETHYST
DIS_SW PG
CLK

BK
VINT_REF SETBK
LLD (ADP5091)

REG_GOOD (ADP5092) TERM_REF TERM

TERM
CONTROL
BIAS REFERENCE VREF
2R
AND OSCILLATOR CLK
R

PGND AGND BAT

14145-040
Figure 2. Detailed Functional Block Diagram

Rev. A | Page 3 of 28
ADP5091/ADP5092 Data Sheet

SPECIFICATIONS
Voltage input (VIN) = 1.2 V, VSYS = VBAT = 3 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical
specifications, unless otherwise noted. External components include the following: inductance (L) = 22 µH, input capacitance (CIN) = 4.7 µF,
and CSYS = 4.7 µF.

Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
QUIESCENT CURRENT
Operating Quiescent Current of SYS Pin IQ_SYS REG_D0 = low, REG_D1 = low 510 1000 nA
(VIN > VCBP ≥ VMINOP)
REG_D0 = high, REG_D1 = low 650 1150 nA
REG_D0 = low, REG_D1 = high 750 1290 nA
REG_D0 = high, REG_D1 = high 760 1300 nA
Sleeping Quiescent Current of SYS Pin IIQ_SLEEP_SYS REG_D0 = low, REG_D1 = low 390 880 nA
(VCBP < VMINOP)
COLD START CIRCUIT
Minimum Input Voltage for Cold Start VIN_COLD VSYS = 0 V, 0°C < TA < 85°C 380 500 mV
Minimum Input Power for Cold Start PIN_COLD 6 µW
End of Cold Start Operation
Threshold VSYS_TH 1.73 1.87 2.00 V
Hysteresis VSYS_HYS 95 mV
BOOST REGULATOR
Input Voltage Operating Range VIN Cold start completed 0.08 3.3 V
Input Power Operating Range PIN Cold start completed, VIN = 3 V 600 mW
Start Charging BAT Threshold on SYS VSYS_CHG 2.00 2.19 2.35 V
Start Charging BAT Hysteresis on SYS VSYS_CHG_HYS 150 mV
Input Peak Current IIN_PEAK Factory trim, 1 bit, Option 0 200 250 mA
Option 1 300 mA
Low-Side Switch On Resistance RLS_DS_ON Pin to pin measurement 0.44 0.6 Ω
High-Side Switch On Resistance RHS_DS_ON Pin to pin measurement 0.85 1.2 Ω
SYS Switch On Resistance RSYS_DS_ON 0.32 0.70 Ω
DIS_SW Voltage
High VDIS_SW_HIGH 1 V
Low VDIS_SW_LOW 0.5 V
DIS_SW Delay tDIS_SW_DELAY 1 µs
VIN CONTROL AND MINOP
VIN Open Circuit Voltage
Default Sampling Cycle tOCV_CYCLE Factory trim, 2 bit (4 sec, 8 sec, 16 sec, 16 sec
32 sec)
Sampling Time tOCV_SAMPL 256 ms
MINOP Bias Current IMINOP 1.58 2.00 2.45 µA
MINOP Operation Voltage Threshold VMINOP_DSM 1.5 V
of Dynamic MPPT Sensing Mode
MPPT Bias Current of MPPT No IMPPT 1.7 2.0 2.3 µA
Sensing Mode
LLD (ADP5091 Only)
Pull-Up Resistor 12 17 kΩ
Pull-Down Resistor 12 17 kΩ
High Voltage VLLD_IH VREG_OUT V
Leakage Current at CBP Pin ICBP_LEAK 10 2000 pA

Rev. A | Page 4 of 28
Data Sheet ADP5091/ADP5092
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
ENERGY STORAGE MANAGEMENT
Internal Reference Voltage VINT_REF 0.955 1.011 1.067 V
Battery Stop Discharging
Threshold VSETSD 2.0 VBAT_TERM V
Hysteresis Resistor RSETSD_HYS 80 115 160 kΩ
Battery Terminal Charging
Threshold VBAT_TERM 2.2 5.2 V
Hysteresis VBAT_TERM_HYS 3 3.1 %
PGOOD Rising Threshold at SYS Pin VSYS_PG VSETSD VBAT_TERM V
PGOOD Pull-Up Resistor 11.6 17.0 kΩ
PGOOD Pull-Down Resistor 11.6 17.0 kΩ
PGOOD High Voltage VPGOOD_HIGH VSYS V
Battery Switches On Resistance RBAT_SW_ON Pin to pin measurement 0.59 0.85 Ω
Battery Source Current IBAT 1 A
Leakage Current at BAT Pin IBAT_LEAK VBAT = 2 V, VSETSD = 2.2 V, VSYS = 2 V 22 50 nA
VBAT = 3.3 V, VSETSD = 2.2 V, VSYS = 0 V 3.5 35 nA
BACK_UP POWER PATH
Turning Off BACK_UP Switch
Threshold on BAT VSETBK 2.0 VBAT_TERM V
Hysteresis Resistor RSETBK_HYS 80 115 160 kΩ
BACK_UP Switches On Resistance 0.85 1.20 Ω
BACK_UP and BAT Comparator VSYS ≥ VSYS_TH
Offset VBKP_OFFSET 158 190 271 mV
Hysteresis VBAT_HYS 68 75 108 mV
BACK_UP Current Capability IBKP VSYS < VSYS_TH 250 µA
Leakage Current at BACK_UP Pin IBKP_LEAK VBACK_UP = VSYS = VBAT = 3 V 16 40 nA
THERMAL SHUTDOWN
Threshold TSHDN VSYS ≥ VSYS_TH 142 °C
Hysteresis THYS 15 °C

Rev. A | Page 5 of 28
ADP5091/ADP5092 Data Sheet
REGULATED OUTPUT SPECIFICATIONS
VIN = 1.2 V, VSYS = VBAT = 3 V, VREG_OUT = 2 V, L = 22 µH, CIN = 4.7 µF, CSYS = 4.7 µF, CREG_OUT = 4.7 µF, TJ = −40°C to +125°C for
minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.

Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
REGULATED OUTPUT
Output Options by VID Control VREG_OUT 1.5 3.6 V
Rating Current IREG_OUT VREG_OUT = 1.5 V to 3.6 V 150 mA
REG_OUT Pull-Down Resistance RREG_OUT 235 Ω
REG_OUT IN BOOST MODE
REG_OUT Wake Threshold VREG_WAKE 1.008 × 1.027 × 1.048 × V
VREG_OUT VREG_OUT VREG_OUT
REG_OUT Wake Threshold VREG_WAKE_HYS 1 %
Hysteresis
Adjustable REG_OUT Wake VADJ_REG_WAKE 1.008 1.028 1.048 V
Threshold
Adjustable REG_OUT Sleep VADJ_REG_SLEEP 1.018 1.038 1.058 V
Threshold
High-Side Switches On Resistance RBST_DS_ON 1.63 2.15 Ω
Current-Limit Threshold of Boost IREG_BST_LIM 100 155 mA
Mode
REG_OUT IN LOW DROPOUT (LDO)
MODE
REG_OUT Accuracy VREG_LDO 0 µA < IOUT < 150 mA, VSYS = (VREG_OUT + 0.5 V) −3.5 +3.5 %
Adjustable REG_OUT Accuracy VREG_LDO_ADJ IOUT = 1 mA 0.999 1.015 1.028 V
0 µA < IOUT < 150 mA, VSYS = (VREG_OUT + 0.5 V) 0.985 1.015 1.045 V
REG_OUT Dropout VREG_DROP IOUT = 150 mA 200 mV
Current-Limit Threshold of LDO IREG_LIM VSYS ≥ VSYS_TH 200 260 mA
Mode
Output Noise OUTNOISE 10 Hz to 100 kHz 700 µV rms
Power Supply Rejection Ratio PSRR 100 Hz 60 dB
1 kHz 40 dB
REG_D0 and REG_D1
Input Logic
High VREG_DX_IH 1.2 V
Low VREG_DX_IL 0.4 V
Input Leakage Current IREG_DX_LEAK 20 nA
REG_GOOD (ADP5092 ONLY)
Rising Threshold VREG_GOOD 89.5 92.5 95.7 %
Hysteresis VREG_GOOD_HYS 2 %
Pull-Up Resistor 11.6 17 kΩ
Pull-Down Resistor 11.6 17 kΩ
High Voltage VREG_GOOD_IH VREG_OUT V

Rev. A | Page 6 of 28
Data Sheet ADP5091/ADP5092

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE
Table 3.
Parameter Rating θJA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
VIN, MPPT, CBP, MINOP −0.3 V to +3.6 V
DIS_SW, TERM, SETPG, SETSD, SETBK, −0.3 V to +6.0 V Table 4.
PGOOD, SETHYST, REF, REG_D0, VID,
Package Type θJA θJC Unit
REG_D1, LLD, REG_GOOD to AGND
24-Lead LFCSP 58.7 36 °C/W
SW, SYS, BAT, BACK_UP, REG_OUT, REG_FB −0.3 V to +6.0 V
to PGND
PGND to AGND −0.3 V to +0.3 V
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. A | Page 7 of 28
ADP5091/ADP5092 Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

24 REG_D0
23 REG_D1

24 REG_D0
23 REG_D1
22 DIS_SW

22 DIS_SW
19 PGOOD

19 PGOOD
21 MINOP

21 MINOP
20 VID
20 VID
REF 1 18 BACK_UP REF 1 18 BACK_UP
SETSD 2 17 BAT SETSD 2 17 BAT
SETBK 3 ADP5091 16 SYS SETBK 3 ADP5092 16 SYS
TERM 4 TOP VIEW 15 REG_FB TERM 4 TOP VIEW 15 REG_FB
(Not to Scale) (Not to Scale)
SETPG 5 14 REG_OUT SETPG 5 14 REG_OUT
SETHYST 6 13 SW SETHYST 6 13 SW

MPPT 9
VIN 10
REG_GOOD 11
PGND 12
CBP 8
AGND 7
MPPT 9
VIN 10
LLD 11
PGND 12
CBP 8
AGND 7

14145-002

NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.

14145-003
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.

Figure 3. ADP5091 Pin Configuration Figure 4. ADP5092 Pin Configuration

Table 5. Pin Function Descriptions

Pin No. 1
ADP5091 ADP5092 Mnemonic Description
1 1 REF Internal Voltage Reference Monitoring Node for the SETSD, SETPG, SETBK, and TERM Pins.
2 2 SETSD Shutdown Setting. The SETSD pin sets the shutdown discharging voltage based on the BAT pin
voltage level.
3 3 SETBK BACK_UP Disabled Threshold Monitoring BAT Voltage Setting. Connect the SETBK pin to the AGND
pin without the BACK_UP storage element.
4 4 TERM Termination Charging Voltage. This pin sets the termination charging voltage based on the BAT pin
voltage level.
5 5 SETPG Power-Good Rising Threshold Monitoring SYS Node Voltage Level Setting.
6 6 SETHYST PGOOD Falling Hysteresis Setting. Connect a resistor between SETPG and SETHYST to program the
PGOOD falling hysteresis.
7 7 AGND Analog Ground.
8 8 CBP Capacitor Bypass. This pin samples and holds the maximum power point level. Connect a 10 nF
capacitor from the CBP pin to the AGND pin. When the MPPT pin is disabled, tie the CBP pin to an
external reference that is lower than the VIN pin.
9 9 MPPT Maximum Power Point Tracking. This pin sets the maximum power point ratio for the different
energy harvesters with a resistor divider. In no sensing mode, place a resistor through AGND to set
the MPPT voltage. The typical current value is 2.0 µA.
10 10 VIN Input Supply from Energy Harvester Source. Connect at least a 10 µF capacitor as close as possible
between VIN and PGND.
11 N/A LLD Low Light Density Indicator to Microcontroller for the ADP5091. LLD pulls high at the MINOP voltage
higher than the CBP voltage.
N/A 11 REG_GOOD Regulated Output Power Good for the ADP5092.
12 12 PGND Power Ground.
13 13 SW Switching Node for the Inductive Boost Regulator with a Connection to an External Inductor.
Connect a 22 µH inductor between SW and VIN.
14 14 REG_OUT Regulated Output. Connect at least a 4.7 µF capacitor as close as possible between REG_OUT and PGND.
15 15 REG_FB Regulated Output Feedback Voltage Sense Input. The fixed output connects this pin to REG_OUT.
The adjustable output connects this pin to a resistor divider from REG_OUT.
16 16 SYS Output Supply to System Load. Connect at least a 4.7 µF capacitor as close as possible between SYS
and PGND.
17 17 BAT SYS Output Supply Storage. This pin places the rechargeable battery or super capacitor as a storage
for the SYS output supply.
18 18 BACK_UP Optional Input Supply from the Backup Primary Battery Cell.

Rev. A | Page 8 of 28
Data Sheet ADP5091/ADP5092
Pin No. 1
ADP5091 ADP5092 Mnemonic Description
19 19 PGOOD Output Signal to Microcontroller. This pin maintains a pulled high level when SYS is higher than the
SETPG threshold.
20 20 VID Voltage Configuration Pin for REG_OUT. This pin sets up to eight different regulated outputs tied
low through a resistor to AGND. The output configuration details are in Table 7.
21 21 MINOP Minimum Operating Power. Place a resistor on MINOP to set the minimum operating input voltage
level. The boost regulator starts switching when the CBP voltage exceeds the MINOP voltage. When
the MINOP pin is floating, the IC operates in no sensing mode with a fixed MPPT level. Connect this
pin through AGND to disable the MINOP function.
22 22 DIS_SW Control Signal from Microcontroller or RF Transceiver to Stop Switching Boost Charger.
23 23 REG_D1 Regulated Output Working Mode Set D1. Enable LDO mode by pulling this pin high.
24 24 REG_D0 Regulated Output Working Mode Set D0. Enable boost mode by pulling this pin high.
EPAD Exposed Pad. The exposed pad must be connected to AGND.
1
N/A means not applicable.

Rev. A | Page 9 of 28
ADP5091/ADP5092 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

VBAT_TERM = 3.5 V, VSYS_PG = 2.8 V, VSETSD = 2.4 V, MPPT (OCV) = 80%, L = 22 μH, CIN = 10 μF, CSYS = 4.7 μF, CREG_OUT = 10 μF, CCBP = 10 nF.
90 100

80 90

70
80

60

EFFICIENCY (%)
EFFICIENCY (%)

70
50
60
40
50
30
40
20 SYS = 2V SYS = 2V
SYS = 3V SYS = 3V
10 30

14145-007
14145-004
SYS = 5V SYS = 5V

0 20
0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0
INPUT VOLTAGE (V) INPUT VOLTAGE (V)

Figure 5. Efficiency vs. Input Voltage, IIN = 10 μA Figure 8. Efficiency vs. Input Voltage, IIN = 100 μA

100 90

90 80

70
80
60
EFFICIENCY (%)
EFFICIENCY (%)

70
50
60
40
50
30

40
20 SYS = 2V
SYS = 2V
SYS = 3V SYS = 3V
30 10

14145-008
14145-005

SYS = 5V SYS = 5V

20 0
0 0.5 1.0 1.5 2.0 2.5 3.0 0.01 0.10 1 10
INPUT VOLTAGE (V) INPUT CURRENT (mA)

Figure 6. Efficiency vs. Input Voltage, IIN = 10 mA Figure 9. Efficiency vs. Input Current, VIN = 0.2 V

90 90

80 80

70 70
EFFICIENCY (%)

EFFICIENCY (%)

60 60

SYS = 2V SYS = 2V
50 SYS = 3V 50 SYS = 3V
SYS = 5V SYS = 5V
40 40

30 30

20 20
14145-100

14145-101

0.01 0.1 1 10 100 0.01 0.1 1 10 100

INPUT VOLTAGE (V) INPUT VOLTAGE (V)
Figure 7. Efficiency vs. Input Voltage, VIN = 0.5 V Figure 10. Efficiency vs. Input Voltage, VIN = 1 V

Rev. A | Page 10 of 28
Data Sheet ADP5091/ADP5092
100 100

90
95
80
90
70

EFFICIENCY (%)
EFFICIENCY (%)

85 60

80 50

40
75
30
70 SYS = 3V
SYS = 5V 20
SYS = 3V

14145-013
65 10
SYS = 5V
0
60 .05 0.5 5 50

14145-102
0.01 0.1 1 10 100
INPUT CURRENT (mA)
INPUT VOLTAGE (V)

Figure 11. Efficiency vs. Input Voltage, VIN = 2 V Figure 14. Efficiency vs. Input Current, VIN = 0.5 V, VREG_OUT = 2 V,
IREG_OUT = 10 µA

100 1400

90
1200
80

QUIESCENT CURRENT (nA)

70 1000
EFFICIENCY (%)

60
800
50
600
40

30 400
TA = –40°C
20 TA = +25°C
200 TA = +85°C
SYS = 3V

14145-014
14145-011

10
SYS = 5V TA = +125°C
0 0
.02 0.2 2 20 2.0 2.5 3.0 3.5 4.0 4.5 5.0
INPUT CURRENT (mA) SYS VOLTAGE (V)

Figure 12. Efficiency vs. Input Current, VIN = 1 V, VREG_OUT = 2 V, IREG_OUT = 10 µA Figure 15. Quiescent Current vs. SYS Voltage, VMINOP ≤ VCBP

1600 1200

1400
1000
QUIESCENT CURRENT (nA)

QUIESCENT CURRENT (nA)

1200 TA = –40°C
TA = +25°C
800
1000 TA = +85°C
TA = +125°C
800 600

600
400
400 TA = –40°C
TA = +25°C
TA = +85°C 200
200
14145-012

14145-015

TA = +125°C

0 0
2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0
SYS VOLTAGE (V) SYS VOLTAGE (V)

Figure 13. Quiescent Current vs. SYS Voltage, VREG_D0 = VREG_D1 = VSYS, VMINOP ≤ VCBP Figure 16. Quiescent Current vs. SYS Voltage, VMINOP > VCBP

Rev. A | Page 11 of 28
ADP5091/ADP5092 Data Sheet
120 60

TA = –40°C TA = –40°C
TA = +25°C TA = +25°C
BACK_UP LEAKAGE CURRENT (nA)

100 50
TA = +85°C TA = +85°C

BAT LEAKAGE CURRENT (nA)

TA = +125°C TA = +125°C
80 40

60 30

40 20

20 10

14145-016

14145-019
0 0
2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2
BACK_UP VOLTAGE (V) BAT VOLTAGE (V)

Figure 17. BACK_UP Leakage Current vs. BACK_UP Voltage Figure 20. BAT Leakage Current vs. BAT Voltage

VIN VIN
1 1

BAT
SYS

BAT
SYS

2 2
SW SW

4 4
14145-017

14145-020
CH1 1.00V BW CH2 1.00V BW M40.0ms A CH2 1.00V CH1 1.00V BW CH2 1.00V BW M100ms A CH2 1.00V
CH3 1.00V BW CH4 2.00V BW CH3 1.00V BW CH4 2.00V BW

Figure 18. Startup with 100 µF Battery, VBAT > VSETSD Figure 21. Startup with Empty 100 µF Capacitor

VIN

VIN
1
CH3: BAT (AC)

3 1
SYS
CH2: SYS (AC)

BAT

3
SW
PGOOD
4 4
14145-018

14145-021

CH1 1.00V BW CH2 50.0mV BW M20.0ms A CH3 5.00mV CH1 500mV BW CH2 1.00V BW M40.0ms A CH4 1.00V
CH3 50.0mV BW CH4 2.00V BW T 80.0000µs CH3 1.00V BW CH4 2.00V BW

Figure 19. Output Ripple of TERM Function with 100 µA Load Figure 22. PGOOD Function Waveform

Rev. A | Page 12 of 28
Data Sheet ADP5091/ADP5092

VIN

BAT VIN
1

BAT BACK_UP
SYS
3
SW
SYS

4 3

14145-025
14145-022
CH1 500mV BW CH2 1.00V BW M10.0ms A CH2 2.00V CH1 500mV BW CH2 1.00V BW M2.00s A CH2 2.12V
CH3 1.00V BW CH4 2.00V BW T –80.0000µs CH3 1.00V BW CH4 1.00V BW

Figure 23. Battery Protection Function Waveform Figure 26. BACK_UP Function, VBAT < VSETBK, VBACK_UP < VBAT

VIN VIN
1 1

BAT
BACK_UP BACK_UP
BAT

CH2: SYS
SYS

3
4 3
14145-023

14145-026
CH1 500mV BW CH2 1.00V BW M2.00s A CH2 2.12V CH1 500mV BW CH2 1.00V BW M2.00s A CH2 2.12V
CH3 1.00V BW CH4 2.00V BW CH3 1.00V BW CH4 1.00V BW

Figure 24. Backup Function, VBAT < VSETBK, VBACK_UP > VBAT Figure 27. BACK_UP Function, VBAT > VSETBK, VBACK_UP > VBAT

VIN
VIN

SYS SYS
1 1
BAT

DIS_SW
3 3
SW
2 SW

4 4
14145-024

14145-027

CH1 500mV BW CH2 2.00V BW M40.0µs A CH4 2.00V CH1 500mV CH2 1.00V M100ms A CH1 880mV
CH3 2.00V BW CH4 2.00V BW T 996.400µs CH3 2.00V CH4 1.00V

Figure 25. Main Boost Pulse Frequency Modulation (PFM) Waveform with Figure 28. DIS_SW Function Waveform
200 µA Load

Rev. A | Page 13 of 28
ADP5091/ADP5092 Data Sheet

VIN VIN

SYS
1 1 SYS
BAT

BAT
SW 2

2 3 SW

3 4

14145-028

14145-031
CH1 500mV BW CH2 1.00V BW M4.00s A CH2 2.12V CH1 500mV BW CH2 2.00V B M4.00s A CH2 2.04V
W
CH3 1.00V BW CH4 2.00V BW CH3 2.00V BW CH4 5.00V BW

Figure 29. MPPT No Sensing Mode, RMPPT = 400 kΩ Figure 32. MPPT Dynamic Sensing Mode

VIN

SYS VIN
LLD

1 1

MINOP MINOP

3 2

2
SW SW
4 4
14145-029

14145-032
CH1 500mV BW CH2 1.00V B M100ms A CH1 780mV CH1 500mV BW CH2 1.00V B M400ms A CH1 780mV
W W
CH3 500mV BW CH4 2.00V BW CH3 500mV BW CH4 2.00V BW

Figure 30. MINOP Function Figure 33. LLD Function

VIN

SYS
VIN
1 1
REG_OUT (AC)

3
SYS
REG_OUT
BAT
3 2 SW

4 4
14145-030

14145-033

CH1 500mV BW CH2 1.00V B M400ms A CH4 220mV CH1 500mV BW CH2 1.00V BW M400µs A CH3 2.00V
W
CH3 1.00V BW CH4 2.00V BW CH3 20.0mV BW CH4 2.00V BW T 0.0000s

Figure 31. REG_OUT Start (Hybrid Mode) Figure 34. REG_OUT Ripple (Boost Mode)

Rev. A | Page 14 of 28
Data Sheet ADP5091/ADP5092

SYS

REG_OUT (AC)

VIN
3

REG_OUT
4 2
REG_GOOD
LOAD CURRENT
2

14145-037
14145-033
CH1 500mV CH2 2.00V M200ms A CH2 1.68V CH1 50.0mV B
W CH2 10.0mAΩ BW A CH2 –129mA
CH3 1.00V CH4 2.00V M1.00ms T 0.0000s

Figure 35. REG_GOOD Function Figure 38. REG_OUT Load Transient (Hybrid), IREG_OUT from 10 µA to 10 mA

1200

1000

REG_OUT RMS NOISE (µV)

REG_OUT (AC)

800
1

600

ILOAD = 0mA
ILOAD = 1mA
400
ILOAD = 10mA
2 ILOAD = 150mA
LOAD CURRENT
200

14145-038
14145-035

0
CH1 50.0mV B
W CH2 50.0mAΩ BW A CH1 –36.0mV 10 100 1k 10k 100k 1M 10M
M1.00µs T 0.0000s FREQUENCY (Hz)

Figure 36. REG_OUT Load Transient (LDO), IREG_OUT from 10 µA to 50 mA Figure 39. REG_OUT RMS Noise vs. Frequency

1 0
ILOAD = 0mA
100m
ILOAD = 1mA –10 ILOAD = 0mA
REG_OUT NOISE DENSITY (µV/Hz)

ILOAD = 10mA
10m ILOAD = 1mA
ILOAD = 150mA ILOAD = 10mA
–20
1m ILOAD = 150mA
–30
100µ
PSRR (dB)

10µ –40

1µ
–50
100n
–60
10n
–70
14145-036

14145-039

1n

100p –80
10 100 1k 10k 100k 1M 10M 10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 37. REG_OUT Noise Density vs. Frequency at Various Current Loads (ILOAD) Figure 40. Power Supply Rejection Ratio (PSRR) vs. Frequency

Rev. A | Page 15 of 28
ADP5091/ADP5092 Data Sheet

THEORY OF OPERATION
The ADP5091/ADP5092 are intelligent, integrated energy MAIN BOOST REGULATOR (VBAT_TERM > VSYS > VSYS_TH)
harvesting, ultralow power management solutions that include The switching mode synchronous boost regulator, with an external
a cold start-up circuit, one synchronous main boost controller, inductor connected between the VIN and the SW pins, operates
and one regulated output hybrid controller with integrated in pulse frequency modulation (PFM) mode, transferring energy
switches, a charging controller with integrated switches, and stored in the input capacitor to the energy storage connected to
backup power path switches. The main boost controller converts the BAT pin. The MPPT control loop regulates the VIN voltage
maximum power from low voltage, high impedance dc sources, at the level sampled at the MPPT pin and stored at the capacitor
such as PV cells, TEGs, and piezoelectric modules, to store energy through the CBP and the AGND pins. To maintain the high
in a rechargeable battery or capacitor with storage protection efficiency of the regulator across a wide input power range, the
and provides power to the load. Another regulated output with current sense circuitry employs an internal dither peak current
automatic hysteresis boost/LDO mode, or pure LDO mode, is limit to control the inductor current.
optimized to provide high efficiency across low output currents
(10 μA), see Figure 14) to high currents of 200 mA. The ADP5091/ The main boost regulator operation reaches an asynchronous
ADP5092 can also control an additional power path from a mode via the energy storage controller if the BAT pin voltage is
primary battery cell to the system. An external signal can less than the battery terminal charging threshold programmed at
temporarily stop the two boost circuits to prevent interference the SETSD pin, or stops switching if the BAT pin voltage is
with RF transmission. more than the battery overcharging threshold programmed at
the TERM pin. The boost regulator disables when the voltage
FAST COLD START-UP CIRCUIT (VSYS < VSYS_TH, on the CBP pin decreases to the threshold set by the resistor at
VIN > VIN_COLD) the MINOP pin. In addition, the boost is periodically stopped
The fast cold start-up circuit extracts energy available at the by an open voltage sampling circuit and can also be temporary
VIN pin and charges only the capacitors at the SYS pin up to disabled by driving the DIS_SW pin high.
VSYS_TH above which the main boost regulator and charge controller VIN OPEN CIRCUIT AND MPPT
start working. The efficient boost regulator charges storage By floating the MINOP pin, the MPPT no sensing mode can
elements on the BAT pin when the SYS voltage is more than operate on a fixed MPPT voltage. The MPPT pin, with a 2.0 μA
the internal BAT charging threshold (VSYS_CHG). When the SYS (typical) bias current through a resistor, sets the MPPT voltage,
voltage is less than the internal BAT charging threshold with a which is the boost input regulation reference.
hysteresis, it stops charging the BAT pin and restarts charging
the SYS pin to ensure that it does not enter cold startup. Figure 41 When the MINOP pin voltage is set lower than VMINOP_DSM
shows the fast cold start-up sequence. through a resistor to AGND, the ADP5091/ADP5092 operate in
MPPT dynamic sensing mode. The boost input regulation
The cold start-up circuit is required when the VIN pin is more reference is the open circuit voltage at the VIN pin scaled to a ratio
than the minimum input voltage for the cold start (VIN_COLD), programmed by the resistor divider at the MPPT pin. To keep
and the energy storage voltage at the SYS pin is less than the end the VIN voltage operating at the maximum power points available
of the cold start operation threshold (VSYS_TH). To complete the from the energy harvester at the input of the ADP5091/ADP5092,
cold startup, the energy harvester must supply sufficient power periodically sample the MPPT voltage and store it in the capacitor
(see the Energy Harvester Selection section). The cold startup, connected to the CBP pin. The reference voltage refreshes every
with much lower efficiency compared to the main boost regulator, 16 sec (default value) by periodically disabling the boost regulator
achieves a short start-up time, creating a low shutdown current for 256 ms (default value) and by sampling the ratio of the open
from the system load enabled by the PGOOD signal. To bypass circuit voltage when the BAT voltage level exceeds the SETSD
the cold startup, place a primary battery at the BACK_UP pin rising threshold. The factory bit can program the sampling
(see the Backup Storage Path section). cycle. Set the reference voltage by
VSETSD  ROC1 
VMPPT  VIN Open Circuit   (1)
VSYS_CHG R R 
VSYS_CHG_HYS  OC1 OC2 
where:
VSYS_TH
FAST VIN (Open Circuit) is the input open circuit voltage (VIN_OCV) of
COLD
START the input voltage.
See Figure 2 for ROC1 and ROC2.
0V SYS BAT
14145-041

LOW HIGH EFFICIENCY

EFFICIENCY

Figure 41. Fast Cold Start-Up Sequence

Rev. A | Page 16 of 28
Data Sheet ADP5091/ADP5092
The typical MPPT ratio depends on the type of harvester. For In LDO mode, the output generates power from the SYS pin
example, it is 0.7 to 0.85 for PV cells, and 0.5 for TEGs. The with at least a small 4.7 µF ceramic output capacitor. Using new
sampling OCV rate is adjustable depending on the previously innovative design techniques, the LDO provides ultralow quiescent
sampled OCV level. To disable the MPPT function, leave the current and superior transient performance for digital and RF
MPPT pin floating and set the CBP pin to an external voltage applications, and supports noise sensitive applications.
reference lower than the VIN voltage. In hybrid mode, the VIN and SYS pins both extract energy to
MINIMUM OPERATION THRESHOLD FUNCTION the REG_OUT pin. When the load power is lower than the input
By setting the MINOP pin voltage lower than the MINOP power, the regulator exits LDO mode and obtains the energy
operation voltage range of the dynamic MPPT sensing mode only from the input side.
(VMINOP_DSM) through a resistor to AGND, the minimum operation REG_D0 AND REG_D1
threshold function can disable the main boost regulator to prevent The REG_D0 and REG_D1 pins allow flexible configuration of
discharging the storage element when the energy generated by the the working mode of the regulated output. Table 6 details the
harvester is less than the system consumption. When the voltage working mode configuration set by these two pins.
of the CBP pin decreases to the threshold set by the resistor at
the MINOP pin, the boost regulator stops switching. The Table 6. Regulated Output Working Mode Configuration
typical MINOP bias current is 2.00 µA. The minimum operation Working Mode REG_D0 REG_D1
threshold function disables the MPPT function to achieve the Boost Disable Low Not applicable
sleeping quiescent current of 390 nA (typical). Disable this Boost Enable High Not applicable
function by connecting the MINOP pin to the AGND pin. LDO Disable Not applicable Low
The low light density (LLD) indicator (ADP5091 only) is the LDO Enable Not applicable High
MINOP comparator output that signals the microprocessor to
REGULATED OUTPUT CONFIGURATION
calculate the cycle with insufficient input energy in a certain
period. The 150 mA regulated output of the ADP5091/ADP5092 is
available in eight fixed output voltage options ranging from
DISABLING BOOST 1.5 V to 3.6 V by connecting one resistor through the VID pin
For noise or electromagnetic interference (EMI) sensitive to the AGND pin. Table 7 shows the output voltage options set by
applications, pull the DIS_SW pin high to stop the boost the VID pin.
switcher temporarily to prevent interference with RF circuits.
Pull the DIS_SW pin low to resume the boost switching. The Table 7. Output Voltage Options Set by the VID Pin
transition delay is 1 µs (typical). VID Configuration Output Voltage Set by the VID Pin
Short to Ground Programmed with external resistors
REGULATED OUTPUT WORKING MODE Floating VOUT = 2.5 V
The 150 mA regulated output of the ADP5091/ADP5092 not RVID = 7 kΩ VOUT = 1.5 V
only operates in the hysteresis boost mode or the LDO mode RVID = 14 kΩ VOUT = 1.8 V
but also operates in the hybrid mode in which the regulator can RVID = 27.7 kΩ VOUT = 3.6 V
smoothly transition between these two modes automatically. RVID = 55.6 kΩ VOUT = 3.3 V
After the BAT voltage exceeds the SETSD threshold or the SYS RVID = 111 kΩ VOUT = 2.0 V
voltage is greater than SETPG threshold, the regulator can be RVID = 221 kΩ VOUT = 3.0 V
enabled. RVID = 442 kΩ VOUT = 2.8 V
In hysteresis boost mode, the boost regulator in the ADP5091/ The external resistor divider or the VID pin can program the
ADP5092 charges the output voltage slightly higher than its regulated output. The ratio of the two external resistors sets the
preset output voltage. When the output voltage increases until adjustable output voltage range of 1.5 V to 3.6 V, as shown in
the output sense signal exceeds the hysteresis comparator upper Figure 47. The device acts as a servo to the output to maintain
threshold (the sleep threshold), the regulator enters sleep mode. In the voltage at the REG_FB pin at 1.0 V referenced to ground.
sleep mode, to allow a low quiescent current as well as high The current in R1 is then equal to 1.0 V/R2, and the current in
efficiency performance, the low-side and high-side switches R1 is the current in R2 plus the REG_FB pin bias current.
and a majority of the circuitry are disabled. Calculate the output voltage by
During sleep mode, the output capacitor supplies the energy into VOUT = 1.02 V × (1 + R1/R2) (2)
the load, the output voltage decreases until it falls below the
where:
hysteresis comparator lower threshold (the wake threshold),
VOUT = VREG_OUT.
and the boost regulator wakes up and generates the pulse-width
See Figure 47 for R1 and R2.
modulation (PWM) pulses to charge the output again. The
hysteresis mode allows the regulator to act as the keep alive To minimize quiescent current, it is recommended to use large
power supply. resistance values for R1 and R2.
Rev. A | Page 17 of 28
ADP5091/ADP5092 Data Sheet
REG_GOOD (ADP5092 ONLY) BACKUP STORAGE PATH
A logic high on the REG_GOOD pin indicates that the REG_OUT The ADP5091/ADP5092 provide an optional backup storage
voltage is above 92.5% (typical) of its nominal output for a delay energy path, an integrated backup controller, and two back to
time greater than approximately 2 ms. The logic high level on back power switches between the BACK_UP pin and the SYS
REG_GOOD is equal to the REG_OUT voltage, and the logic low pin. When the system operates at a condition where the harvested
level is ground. When the REG_OUT voltage falls below a 2% and stored energy is periodically insufficient, attach a backup
hysteresis (typical) of the rising threshold, the REG_GOOD pin energy storage element to the BACK_UP pin.
goes low. The logic high level has about 11.6 kΩ internally in The backup controller enables when the SYS voltage exceeds the
series to limit the available current. end of the cold start operation threshold (VSYS_TH). Before the BAT
ENERGY STORAGE CHARGE MANAGEMENT voltage lowers the SETBK threshold, the backup switches turn
Energy storage is connected to the BAT pin. The storage can be off. While the BAT voltage is less than the SETBK threshold, the
a rechargeable battery, super capacitor, or 100 µF or larger switches status depends on the voltage level of the BACK_UP pin
capacitor. The energy storage controller manages the charging and the BAT pin. The internal BACK_UP_Mx and BACK_UP
and discharging operations, monitors the SYS pin voltage, and control circuit automatically determine the BACK_UP switches
asserts the PGOOD signal high when it is above the threshold (BACK_UP_M1 and BACK_UP_M2) on/off status and selects
programmed at the SETPG pin. the high voltage terminal as the power source of SYS. The 190 mV
(typical) comparator input offset of the BAT pin prevents the
When the BAT pin voltage exceeds the battery terminal charging input source and the BAT pin from charging the BACK_UP pin
threshold programmed at the TERM pin, the boost operation (see Figure 44).
terminates to prevent battery overcharging. The battery terminal
charging threshold is programmable from 2.2 V to 5.2 V. When In addition, the backup storage element can bypass the cold
the BAT voltage drops below the battery stop charging threshold startup with inrush current protection circuitry. Nevertheless,
level programmed at the SETSD pin, the switches between the the current capability is only 250 µA (typical) when plugging in
BAT pin and the SYS pin are turned off to prevent a deep, destruc- the backup battery before completing the cold start. It is recom-
tive battery discharge, and the boost operates in asynchronous mended to restrict the system load current from the SYS pin to
mode. Although there is no current limit at the SYS and the ensure that the power path can enter normal operation status.
BAT pins, it is recommended to limit the system load current Table 9 explains the power path working state. For long-term
to lower than 1000 mA. The large system load current generates a store mode, disconnect the backup storage element and then
droop between the SYS pin and the rechargeable battery at the discharge SYS to ground.
BAT pin, with consideration given to the resistance of the SYS
switch, the BAT switch, and the rechargeable battery internal
resistance.
When no input source is attached, discharge the SYS pin to
ground before attaching a storage element to the BAT pin.
After hot plugging a charged storage element, release the SYS pin
because a SYS voltage that is less than the end of the cold start
operation threshold (VSYS_TH) results in the BAT switch remaining
off to protect the storage element until the SYS voltage reaches
VSYS_TH. The BAT switches remaining off can also be described
as store mode, a state with the lowest leakage (3.5 nA typical)
that allows a long store period without discharging the storage
element on BAT.

Rev. A | Page 18 of 28
Data Sheet ADP5091/ADP5092
BACKUP AND BAT SELECTION THRESHOLD BATTERY OVERCHARGING PROTECTION
To determine when to enable the BACK_UP function, the switch To prevent rechargeable batteries from being overcharged and
threshold on the BAT pin must be set by using external resistors at damaged, the battery terminal charging threshold (VBAT_TERM) must
SETBK pin. When the BAT voltage is lower than the SETBK be set by using external resistors. Figure 42 shows the VBAT_TERM
threshold, the internal BACK_UP_Mx control circuit automatically rising threshold voltage given by Equation 6.
selects the high voltage terminal as the SYS power source. Figure 42
3  R 
shows the VSETBK falling threshold voltage given by Equation 3. VBAT_TERM   VINT _ REF  1  TERM1  (6)
2  
 R  (3)  RTERM2 
VSETBK  VINT _ REF  1  BK1 
 RBK2  Considering the quiescent current consumption, the sum of the
resistors must be more than 6 MΩ, that is,
The ADP5091/ADP5092 have an internal resistor, RSETBK_HYS =
115 kΩ (typical), to program the hysteresis, given by RTERM1 + RTERM2 ≥ 6 MΩ (7)
Equation 4. The battery terminal charging threshold is given by VBAT_TERM_HYS,
RSETBK_HYS which is internally set to the battery terminal charging threshold
VSETBK_HYS  VSETBK  (4)
minus an internal hysteresis voltage denoted by VBAT_TERM_HYS.
RE
When the voltage at the battery exceeds the VBAT_TERM threshold,
where RE is the equivalent resistor of the four external the main boost regulator disables. The main boost starts again
configuration resistor dividers. when the battery voltage falls below the VBAT_TERM_HYS level. When
Considering the quiescent current consumption, the sum of the input energy is excessive, the VBAT pin voltage ripples between
resistors that comprise the resistor divider (RSETBK_HYS, RBK1, and the VBAT_TERM and the VBAT_TERM_HYS levels.
RBK2) must be greater than 6 MΩ, that is, BATTERY DISCHARGING PROTECTION
RSETBK_HYS + RBK1 + RBK2 > 6 MΩ (5) To prevent rechargeable batteries from being deeply discharged
The equivalent resistor of the four external configuration resistor and damaged, the battery stop discharging threshold (VSETSD)
dividers (RE) is equivalent to the paralleling value of the three must be set by using external resistors. Figure 42 shows the
resistor dividers. VSETSD falling threshold voltage given by Equation 8.
 R  (8)
TERM_REF VSETSD  V INT _ REF  1  SD1 
 R SD2 
BK
The ADP5091/ADP5092 have an internal resistor, RSETSD_HYS =
BAT
115 kΩ (typical), to program the hysteresis, given by Equation 9.
RSETBK_HYS
REF RSETSD_HYS
SD
VSETSD_HYS  VSETSD  (9)
BAT RE
RSD1 RPG1 RBK1 RTERM1
RSETSD_HYS
Considering the quiescent current consumption, the sum of the
SETSD
SD
resistors that comprise the resistor divider (RSETSD_HYS, RSD1, and
RSD2) must be more than 6 MΩ, that is,
PG
PGOOD
RSETSD_HYS + RSD1 + RSD2 ≥ 6 MΩ (10)
PG
SETPG
PG
The equivalent resistor of the three external configuration
RPG_HYST
SETHYST resistor dividers (RE) is equivalent to the paralleling value of the
PG three resistor dividers.
BK
VINT_REF SETBK

TERM_REF TERM
TRM TERM
CONTROL
2R RSD2 RPG2 RBK2 RTERM2

R
14145-042

BAT

Figure 42. ADP5091/ADP5092 Program Paramater Setting

Rev. A | Page 19 of 28
ADP5091/ADP5092 Data Sheet
POWER GOOD (PGOOD) POWER PATH WORKING FLOW
The ADP5091/ADP5092 allow users to set a programmable Figure 44 shows the power switches structure when the backup
PGOOD voltage threshold, which indicates that the SYS voltage primary battery is used. During the cold start, when a primary
is at an acceptable level. It must be set by using external resistors. battery connects to the BACK_UP pin, the S1 switch turns on.
Figure 42 shows the VSETPG falling threshold voltage given by The primary battery with the Diode D1 forward voltage drop
Equation 11. can be the SYS power source.

  After completing the cold start, if the BAT voltage is above the
RPG1
VSETPG _ FALLING = VINT _ REF 1 +  (11) SETBK falling threshold, the BACK_UP switches remain off.
 R +R 
 PG2 PG _ HYST  When the BAT voltage is lower than the SETBK falling threshold,
The SETHYST pin can program the hysteresis with an external the backup control automatically selects the high voltage terminal
resistor (RPG_HYST) given by Equation 12. as the SYS power source as long as the SYS voltage is more than
VSYS_CHG. The backup control also prevents the BACK_UP
 R + RPG _ HYST  primary battery from charging the BAT pin. Meanwhile, the BAT
VSETPG _ RISING = VINT _ REF 1 + PG1  (12)
 RPG2 
  offset of the comparator prevents the input source from
Considering the quiescent current consumption, the sum of the charging the BACK_UP primary battery. Table 9 shows the
resistors that comprise the power-good resistor divider power path of the working state.
(RPG_HYST, RPG1, and RPG2) must be more than 6 MΩ, that is, S1
D1

RPG_HYST + RPG1 + RPG2 ≥ 6 MΩ

BACK_UP_M1 BACK_UP
The logic high level on PGOOD is equal to the SYS voltage and +
the logic low level is ground. The logic high level has approximately –
BACK_UP_M2
11.6 kΩ (typical) internally in series to limit the available current. SYS
The VSETPG_FALLING threshold must be greater than the VSETSD
threshold. SYS SWITCH

For the best operation of the system, use PGOOD to enable the
SW HS BAT_M1 BAT_M2 BAT
system load or to turn on an ultralow power load switch or to BSTO +
drive an external positive channel field effect transistor (PFET) LS –
between SYS and the system load via an inverter to determine GATE GATE DRIVER

14145-044
DRIVER
when the system load can be connected or removed (see Figure 48).
Table 8 shows programming threshold resistor examples Figure 44. ADP5091/ADP5092 Power Switches Structure
corresponding to various voltages with a 10 MΩ resistor divider. CURRENT-LIMIT AND SHORT-CIRCUIT PROTECTION
Figure 43 shows various threshold voltages states.
The boost regulator and regulated output in hysteresis boost mode
MAXIMUM DEVICE
RATING VOLTAGE in the ADP5091/ADP5092 includes current-limit protection
MAIN BOOST
TURN OFF MAIN BOOST
CHARGER OFF circuitry to limit the amount of positive current flowing through
the low-side boost switch. The boost regulator current-limit
VBAT_TERM
protection circuitry is a cycle-by-cycle, three-level peak current-
VBAT_TERM_HYS
limit protection with a third level of 200 mA (typical), and the
PGOOD BECOMES HIGH
regulated output current-limit protection circuitry is 100 mA
(typical). In LDO mode, the current-limit protection is designed
INCREASING SYS VOLTAGE

VSETPG_RISING
VSETPG_FALLING to limit the current when the output load reaches 260 mA
MAIN BOOST
MAIN BOOST IN CHARGER ON (typical). When the output load exceeds 260 mA, the output
SYNCHRONOUS MODE
TURN ON SWITCH BETWEEN voltage reduces to maintain a constant current limit.
BSTO AND BAT
VSETSD_HYS Although there is no current limit at the SYS and the BAT pins,
VSYS_CHG
VSETSD it is recommended to limit the system load current to lower
CHARGING BATTERY than 1000 mA. The total resistance of the SYS switch and the
VSYS_CHG_HYS
BAT switch (1.03 Ω, typical) generates a voltage drop when the
TURN ON MAIN BOOST IN
system load sinks a large current from BAT. It is also necessary
ASYNCHRONOUS MODE to consider the internal resistance of the storage elements
VSYS_TH VSYS_TH connected to the BAT pin.
14145-043

COLD STARTUP
ENABLE CHIP
0V

Figure 43. ADP5091/ADP5092 Various Threshold Voltages States (See

Equation 8 and Equation 9)
Rev. A | Page 20 of 28
Data Sheet ADP5091/ADP5092
THERMAL SHUTDOWN included, allowing the ADP5091/ADP5092 to return to operation
In the event that the ADP5091/ADP5092 junction temperature when the on-chip temperature drops to less than 127°C. When
rises above 142°C, the thermal shutdown circuit turns off the exiting thermal shutdown, the boost and the energy storage
switch between the BAT pin and the SYS pin to prevent the controller resume their functions.
damage of the energy storage at a high ambient temperature. In
addition, the boost operation terminates. A 15°C hysteresis is
Table 8. Programming Threshold Resistors (See Figure 42)
Voltage Threshold (V) RBK1, RSD1, and RPG1 (MΩ) RBK2, RSD2, and RPG2 (MΩ) RTERM1 (MΩ) RTERM2 (MΩ)
2 5 5 Not applicable Not applicable
2.1 5.23 4.75 Not applicable Not applicable
2.2 5.49 4.53 3.2 6.81
2.3 5.62 4.32 3.48 6.49
2.4 5.9 4.12 3.74 6.2
2.5 6.04 4 4 6.04
2.6 6.19 3.83 4.22 5.76
2.7 6.34 3.74 4.42 5.6
2.8 6.49 3.57 4.64 5.36
2.9 6.6 3.48 4.87 5.23
3 6.65 3.32 5 5
3.1 6.8 3.24 5.11 4.87
3.2 6.81 3.09 5.36 4.7
3.3 6.98 3.01 5.49 4.53
3.4 6.98 2.94 5.6 4.42
3.5 7.15 2.87 5.76 4.3
3.6 7.15 2.8 5.9 4.12
3.7 7.32 2.7 5.9 4.02
3.8 7.32 2.61 6.04 3.92
3.9 7.5 2.55 6.19 3.83
4 7.5 2.5 6.2 3.74
4.1 7.5 2.43 6.34 3.65
4.2 7.68 2.37 6.49 3.57
4.3 7.68 2.32 6.49 3.48
4.4 7.68 2.26 6.6 3.4
4.5 7.87 2.21 6.65 3.32
4.6 7.87 2.15 6.8 3.24
4.7 7.87 2.15 6.81 3.2
4.8 7.87 2.1 6.81 3.09
4.9 7.87 2.05 6.98 3.09
5 8.06 2 6.98 3
5.1 8.06 1.96 6.98 2.94
5.2 8.06 1.91 7.15 2.87

Rev. A | Page 21 of 28
ADP5091/ADP5092 Data Sheet
Table 9. Power Path Working State (See Figure 44)
Backup Battery Power Condition 1 Main Boost BAT_M1 BAT_M2 SYS Switch BACK_UP_M1 BACK_UP_M2
Without VSYS_CHG > VSYS > VSYS_TH, Asynchronous Off Off On Off Off
VSETSD > VBAT
VSYS > VSYS_CHG, VSETSD > VBAT Asynchronous On Off On Off Off
VBAT_TERM > VBAT = VSYS > VSETSD Synchronous On On On Off Off
VSYS > VSYS_TH, VBAT > VBAT_TERM Disabled On On On Off Off
With VSYS_CHG > VSYS > VSYS_TH, Asynchronous Off Off On Off Off
VSETSD > VBAT
VSYS > VSYS_CHG, VSETSD > VBAT, Asynchronous On Off Off On On
VBACK_UP > VBAT
VSYS > VSYS_TH, VBAT > VSETSD, Synchronous On On On Off Off
VBAT > VSETBK
VSYS > VSYS_TH, VBAT > VSETSD, Synchronous On On Off On On
VBAT < VSETBK, VBACK_UP > VBAT
VSYS < VSYS_TH Disabled Off Off On Off Off
1
VBACK_UP is the voltage on the BACK_UP pin, and VSETBK is the threshold of the SETBK pin.

Rev. A | Page 22 of 28
Data Sheet ADP5091/ADP5092

APPLICATIONS INFORMATION
The ADP5091/ADP5092 extract the energy from the VIN pin Table 10. Recommended Solar Cells
to charge the SYS and the BAT pins. This process occurs in Vendor Device Type
three stages: cold start, asynchronous boost, and synchronous
Alta Devices GaAs
boost. This section describes the procedures for selecting the
Fujikura Dye sensitized solar cell
external components to maintain the energy transmission
Gcell Dye sensitized solar cell
system with the layout and assembly considerations.
ElectricFilm Dye sensitized solar cell
ENERGY HARVESTER SELECTION
The energy harvester input source must provide a minimum level ENERGY STORAGE ELEMENT SELECTION
of power for cold start, asynchronous boost, and synchronous To protect the storage element from overcharging or overdis-
boost. To estimate the minimum input power required to charging, the storage element must be connected to the BAT pin
complete the cold start using the following equation: and the system load tied to the SYS pin. The ADP5091/ADP5092
VIN × IIN × ηCOLD > VSYS_TH × ISYS_LOAD (13) support many types of storage elements, such as rechargeable
batteries, super capacitors, and conventional capacitors. A
where:
storage element with a 100 µF equivalent capacitance is required
VIN is clamped to VIN_COLD = 380 mV (typical), which indicates
to filter the pulse currents of the PFM switching converter. The
the minimum input voltage for cold start.
storage element capacity must provide the entire system load
IIN is the input current.
when the input source is no longer generating power.
ηCOLD is the cold start efficiency, which is about 5% to 7%.
(VSYS_TH is the end of cold start operation. If there is a high pulse current or the storage element has
ISYS_LOAD is the system load current of the SYS pin. Minimizing significant impedance, it may be necessary to increase the SYS
the system load accelerates the cold start. Programming the capacitor from the 4.7 µF minimum, or add additional capacitance
PGOOD threshold to enable the system load current is to the BAT pin to prevent a droop in the SYS voltage. Note that
recommended. increasing the SYS capacitor causes the boost regulator to operate
in the less efficient cold start stage for a longer period at startup.
After the ADP5091/ADP5092 complete the cold start, the MPPT
If the application is unable to accept the longer cold start time,
function enables. To meet the average system load current, the
place the additional capacitor parallel to the storage element. See
input source must provide the boost regulator with enough power
the Capacitor Selection section for more information.
to fully charge the storage element while the system is in low
power or sleep mode. To estimate the power required by the INDUCTOR SELECTION
system, use the following equation: The boost regulator needs an appropriate inductor for proper
VIN × IIN × ηBOOST > VBAT_TERM × (ISTR_LEAK + ISYS_LOAD) (14) operation. The inductor saturation current must be at least 30%
higher than the expected peak inductor currents, as well as a
where:
low series resistance (DCR) to maintain high efficiency. The
VIN is regulated to the MPPT pin voltage (MPPT ratio × OCV).
boost regulator internal control circuitry is designed to optimize
IIN is the input current.
the efficiency and control the switching behavior with a nominal
ηBOOST is the boost regulator efficiency. See Figure 5 through
inductance of 22 µH ± 20%. Table 11 lists some of the
Figure 12 in the Typical Performance Characteristics section for
recommended inductors.
more information.
VBAT_TERM is the battery terminal charging threshold (see Table 1).
ISTR_LEAK is the storage element leakage current at the BAT pin.
ISYS_LOAD is the average system load current of the SYS pin.

Table 11. Recommended Inductors

Vendor Device No. L (µH) ISAT (A)1 IRMS (A)2 DCR (mΩ)
Würth Elektronik 74437324220 22 2 1 470
744042220 22 0.6 0.88 255
Coilcraft LPS4018-223M 22 0.8 0.65 360
1
ISAT is the dc current that causes the 20% inductance drop from its value without current.
2
IRMS is the current that causes a 20°C rise from a 25°C ambient temperature.

Rev. A | Page 23 of 28
ADP5091/ADP5092 Data Sheet
CAPACITOR SELECTION influences the effectiveness of MPPT. When the IC junction
Low leakage capacitors are required for ultralow power temperature exceeds 85°C, a larger capacitance is beneficial to
applications that are sensitive to the leakage current. Any the effectiveness of MPPT, and for a higher CPB pin leakage
leakage from the capacitors reduces efficiency, increases the current. It is recommended to keep the same RC time constant
quiescent current, and degrades the MPPT effectiveness. of the MPPT resistors and CBP capacitor (up to 22 µF) as shown
in the typical application circuit in Figure 45. Considering the
Input Capacitor time constant of the MPPT resistor divide and the CBP capacitor, a
A capacitor (CIN) connected to the VIN pin and the PGND pin low leakage X7R or C0G 10 nF ceramic capacitor is recommended.
stores energy from the input source. For the energy harvester,
LAYOUT AND ASSEMBLY CONSIDERATIONS
capacitive behavior dominates the source impedance. Scale the
input capacitor according to the value of the output capacitance Carefully consider the printed circuit board (PCB) layout
of the energy harvester; a minimum of 10 µF is recommended. during the design of the switching power supply, especially at
high peak currents and high switching frequency. Therefore, it
For the primary battery application, a larger capacitance helps
is recommended to use wide and short traces for the main power
to reduce the input voltage ripple and keeps the source current
path and the power ground paths. Place the input capacitors,
stable to extend the battery life.
output capacitors, inductor, and storage elements as close as
SYS Capacitor possible to the IC. It is most important for the boost regulator to
The ADP5091/ADP5092 require two capacitors to be connected minimize the power path from output to ground. Therefore,
between the SYS pin and the PGND pin. Connect a low ESR place the output capacitor as close as possible between the SYS
ceramic capacitor of at least 4.7 µF parallel to a high frequency, pin and the PGND pin. Keep a minimum power path from the
0.1 µF bypass capacitor. Connect the bypass capacitor as close as input capacitor to the inductor from the VIN pin to the PGND
possible between SYS and PGND. pin. Place the input capacitor as close as possible between the
VIN pin and the PGND pin, and place the inductor close to the
REG_OUT Capacitor
VIN pin and the SW pin. It is best to use vias and bottom traces
The ADP5091/ADP5092 regulated output is designed for for connecting the inductors to their respective pins. To minimize
operation with small, space-saving ceramic capacitors but noise pickup by the high impedance threshold setting nodes
functions with the most commonly used capacitors as long as (REF, TERM, SETBK, SETSD, and SETPG), place the external
care is taken with regard to the effective series resistance (ESR) resistors close to the IC with short traces.
value. The ESR of the output capacitor affects stability of the
The CBP capacitor must hold the MPPT voltage for 16 sec,
LDO control loop. A minimum capacitance of 4.7 µF with an
because any leakage can degrade the MPPT effectiveness. During
ESR of 1 Ω or less is recommended to ensure stability of the
board assembly and cleaning, contaminants such as solder flux
regulated output. Transient response to changes in load current
and residue may form parasitic resistance to ground, especially
is also affected by output capacitance. Using a larger value of
in humid environments with fast airflow. Contamination can
output capacitance improves the transient response of the
significantly degrade the voltage regulation and change threshold
regulated output to large changes in load current.
levels set by the external resistors. Therefore, it is recommended
CBP Capacitor that no ground planes be poured near the CBP capacitor or the
The operation of the MPPT pin depends on the sampled value threshold setting resistors. In addition, carefully clean the boards. If
of the OCV. The voltage stored on the CBP capacitor regulates possible, clean ionic contamination with deionized water for the
to the VIN pin. This capacitor is sensitive to leakage because the CBP capacitor and the threshold setting resistors.
holding period is around 16 sec. As the capacitor voltage drops
due to leakage, the VIN regulation voltage also drops and

Rev. A | Page 24 of 28
Data Sheet ADP5091/ADP5092
TYPICAL APPLICATION CIRCUITS
VID LLD TO MCU
111kΩ 2V
REG_OUT SENSOR
10µF
REG_D0 REG_FB
FROM MCU
REG_D1 PGOOD
SOLAR 22µH
HARVESTER SYS
SW
4.7µF
VIN
10µF
4.7MΩ BAT +
MPPT
–
18MΩ
CBP PA-5R0H224
10nF MCU
ADP5091 0.22F
(ALWAYS ON)
REF

BACK_UP SETSD
CR2032 + SETPG
3V DIS_SW
225mAh –
MINOP ADF7024
SETHYST (Rx/Tx)
150kΩ SETBK

TERM
AGND PGND

14145-045
Figure 45. ADP5091-Based Energy Harvester Wireless Sensor Application with PV Cell as the Harvesting Energy Source (Trony 0.7 V, 60 μA, Alta Devices 0.72 V, 42 μA,
Gcell 1.1 V, 100 μA), Cooper Bussmann Super Capacitor PA-5R0H224 as the Harvested Energy Storage, and Panasonic Primary Li-Ion Coin Cell CR2032 as the Backup
Battery

VID LLD TO MCU

111kΩ 2V
REG_OUT
10µF
FROM MCU REG_D0 REG_FB
THERMOELECTRIC
GENERATOR REG_D1 PGOOD
22µH
SYS
SW
4.7µF
+ 10µF VIN
BAT +
MPPT
–
250kΩ
CBP PA-5R0H224
10nF ADP5091 0.22F

REF

BACK_UP SETSD
CR2032 + SETPG
3V DIS_SW
225mAh –
MINOP SETHYST
SETBK

TERM
AGND PGND
14145-046

Figure 46. ADP5091-Based Energy Harvester Circuit with a Thermoelectric Generator as the Harvesting Energy Source, Cooper Bussmann Super Capacitor
PA-5R0H224 as the Harvested Energy Storage, and Panasonic Primary Li-Ion Coin Cell CR2032 as the Backup Battery

Rev. A | Page 25 of 28
ADP5091/ADP5092 Data Sheet
VID LLD TO MCU
2V
REG_OUT
R1 10MΩ 10µF
REG_D0 REG_FB
FROM MCU R2 10MΩ
REG_D1
PIEZOELECTRIC PGOOD
HARVESTER 22µH
SYS
SW
4.7µF
VIN
10MΩ BAT +
10µF MPPT
–
10MΩ
CBP PA-5R0H224
10nF ADP5091 0.22F

REF

BACK_UP SETSD
CR2032 + SETPG
3V DIS_SW
225mAh –
MINOP SETHYST
200kΩ SETBK

TERM
AGND PGND

14145-047
Figure 47. ADP5091-Based Energy Harvester Circuit with a Piezoelectric Generator as the Harvesting Energy Source, Cooper Bussmann Super Capacitor PA-5R0H224
as the Harvested Energy Storage, and Panasonic Primary Li-Ion Coin Cell CR2032 as the Backup Battery

VID REG_GOOD
111kΩ 2V
REG_OUT
1µF
REG_D0 REG_FB
FROM MCU
REG_D1 SYSTEM
SYS LOAD
22µH
4.7µF
SW SYS
TRANSFORMER
VIN PGOOD
AC 6.34MΩ
10µF MPPT BAT +
14.7MΩ –
CBP
10nF PA-5R0H224
ADP5092 0.22F
REF

BACK_UP SETSD
CR2032 + SETPG
3V DIS_SW
225mAh –
MINOP SETHYST
20kΩ SETBK

TERM
AGND PGND
14145-048

Figure 48. ADP5092 AC Input Source and PGOOD Function Determines the Time to Enable the System Load

Rev. A | Page 26 of 28
Data Sheet ADP5091/ADP5092

FACTORY PROGRAMMABLE OPTIONS

To order a device with options other than the default options, Table 13. VIN Open Circuit Voltage Sampling Cycle Options
contact a local Analog Devices, Inc., sales or distribution Option Description
representative.
Option 0 4 sec
Table 12. Input Current-Limit Options Option 1 8 sec
Option Description Option 2 16 sec (default)
Option 0 200 mA (default) Option 3 32 sec
Option 1 300 mA

Rev. A | Page 27 of 28
ADP5091/ADP5092 Data Sheet

OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
4.10 0.30
4.00 SQ 0.25
PIN 1 3.90 0.20
INDICATOR PIN 1
INDIC ATOR AREA OPTIONS
19 24
(SEE DETAIL A)
18 1

0.50
BSC 2.44
EXPOSED
PAD 2.30 SQ
2.16

13 6

0.50 12 7
0.20 MIN
TOP VIEW BOTTOM VIEW
0.40
0.30
0.80 FOR PROPER CONNECTION OF
0.75 THE EXPOSED PAD, REFER TO
0.05 MAX THE PIN CONFIGURATION AND
0.70
0.02 NOM FUNCTION DESCRIPTIONS
COPLANARITY SECTION OF THIS DATA SHEET.
SEATING 0.08
PLANE 0.203 REF

03-09-2017-B
PKG-003994/5111

COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8

Figure 49. 24-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-14)
Dimensions shown in millimeters

ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADP5091ACPZ-1-R7 −40°C to + 125°C 24-Lead Lead Frame Chip Scale Package [LFCSP], 200 mA Input CP-24-14
Peak Current
ADP5091ACPZ-2-R7 −40°C to + 125°C 24-Lead Lead Frame Chip Scale Package [LFCSP], 300 mA Input CP-24-14
Peak Current
ADP5092ACPZ-1-R7 −40°C to + 125°C 24-Lead Lead Frame Chip Scale Package [LFCSP], 200 mA Input CP-24-14
Peak Current
ADP5091-1-EVALZ Evaluation Board
ADP5091-2-EVALZ Evaluation Board with Solar Harvester and Super Capacitor
ADP5092-1-EVALZ Evaluation Board
1
Z = RoHS Compliant Part.

©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D14145-0-5/17(A)

Rev. A | Page 28 of 28