Department of Electrical Engineering
Faculty Member: MS RAFIA AHMAD Dated: 04-FEB-2025
Semester: 2ND Section: BSDS-02-A
Group No.:
EE-221: Digital Logic Design
Lab 2: Introduction to Verilog
PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO7
Name Reg. No Viva / Lab Analysis Modern Ethics and Individual Total
Performance of data in Tool Usage Safety and Team marks
Lab Report Work Obtained
5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks
Anas Norani 501231
Hanan Majeed 519166
Mujtaba Umar 510196
Shehryar 520299
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Lab2: Introduction to Verilog, Gate-level/Behavioral Modeling and Hardware
Implementation of Basic Logic Circuit
This Lab has been divided into two parts.
In first part you will be introduced to Verilog and Gate-Level Modeling.
The next part is the hardware implementation of a Boolean function given to you.
Objectives:
Understand HDL and compare it with normal programming languages.
Simulate Basic Gates using Verilog with ModelSim
Write stimulus using Verilog
Derive algebraic expression for a Boolean function from the given schematics.
Hardware Implementation of Logic Circuit
Lab Instructions
This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-lab viva session.
The lab report will be uploaded on LMS before scheduled lab date. Each group to upload
completed lab report on LMS for grading.
The students failing to complete Pre-lab will not be allowed to attend lab session.
The students will start lab task and demonstrate design steps separately for step-wise
evaluation (teacher/lab engineer will sign each step after ascertaining functional verification).
Any report submitted without teacher/lab engineer signatures will not be accepted.
Remember that a neat logic diagram with pins numbered and nicely patched circuit will
simplify trouble-shooting/fault diagnostic process.
After completion of lab, the students are expected to unwire the circuit and deposit back
components to lab staff.
The students will complete lab task within the prescribed time and submit complete report to
lab engineer before leaving the lab.
There will be a viva session after demonstration for which students will be graded individually.
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Pre-Lab Tasks (0.5)
1. Read the manual Getting Started with Verilog and answer the following questions: (Handwritten)
a) What does HDL stand for? What are its two standard versions?
b) Give the different levels of abstraction in Verilog HDL
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Lab Tasks (9.5)
Lab Task 1 (3)
Model and simulate the basic gates i.e. NOT, AND & OR in Verilog (Gate level) using Modelsim. Compare
the simulation waveform results with truth table in the space given below.
AND GATE
Code (SS & Text)
Text Screen shot
module AND_gate( Y,A,B);
input A,B;
output Y;
and mine(Y,A,B); // AND
operation
endmodule
module test_AND_gate;
reg a, b;
wire y;
AND_gate OUT( y,a, b);
initial
begin
// Test inputs
a = 0; b = 0; #10;
a = 0; b = 1; #10;
a = 1; b = 0; #10;
a = 1; b = 1; #10;
end
endmodule
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Output Waveform:
OR GATE
Code (SS & Text)
Text Screen Shot
module OR_gate( Y,A,B);
input A,B;
output Y;
or mine(Y,A,B); // AND operation
endmodule
module test_OR_gate;
reg a, b;
wire y;
OR_gate OUT( y,a, b);
initial
begin
// Test inputs
a = 0; b = 0; #10;
a = 0; b = 1; #10;
a = 1; b = 0; #10;
a = 1; b = 1; #10;
end
endmodule
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Output Waveform
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NOT GATE
Code (SS & Text)
Text Screen Shot
module NOT_gate(A, Y);
input A;
output Y;
not MINE(Y, A); // NOT operation
endmodule
module test_NOT_gate;
reg a;
wire y;
NOT_gate OUT(a, y);
initial begin
a = 0; #10;
a = 1; #10;
end
endmodule
Output Waveform
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Lab Task 2 (3)
a. Write the Verilog Code using Gate Level modeling for the following circuit. List the code for design as
well as stimulus below.
b. Simulate below circuit on Proteus and perform it on hardware.
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Verilog Code (SS + Text) & Output Waveform
Text Screen Shot
module circuit (
input a,
input b,
output sum,
output carry
);
xor(sum, a, b);
and(carry, a, b);
endmodule
module
half_adder_tb;
reg a, b;
wire sum, carry;
half_adder uut (
.a(a),
.b(b),
.sum(sum),
.carry(carry)
);
initial begin
a = 0; b = 0;
#10;
a = 0; b = 1;
#10;
a = 1; b = 0;
#10;
a = 1; b = 1;
#10;
end
initial begin
$monitor("Time =
%0t | a = %b, b =
%b | sum = %b,
carry = %b", $time,
a, b, sum, carry);
end
endmodule
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Proteus Simulation (SS for all 4 inputs)
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Hardware (SS for all 4 input
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Lab Task 3 (1.5)
Label each gate output in the above circuit and derive algebraic expressions for SUM and Carry Out. Fill in
the following truth table and determine the function performed by the circuit.
Truth Table:
A B Sum Carry Out
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
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Derivation for algebraic expressions & determining function:
SUM:
The SUM is the output of the XOR gate.
Algebraic expression:
(Where ⊕ represents the XOR operation.)
SUM=a⊕b
Carry Out:
The Carry Out is the output of the AND gate.
Algebraic expression:
(Where ⋅⋅ represents the AND operation.)
Carry Out=a⋅b
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Lab Task 4 (2)
After determining the function performed by the circuit given in Lab Task 2, write the Verilog description of
the circuit in dataflow. Comment on the two different modeling levels you used to model the same circuit.
(Paste snapshots of the codes and stimuluses below)
Code (SS + Text)
Text Screen Shot
module
half_adder_dataflow (
input a,
input b,
output sum,
output carry
);
assign sum = a ^ b; //
XOR operation for sum
assign carry = a & b; //
AND operation for carry
endmodule
module
half_adder_dataflow_tb;
reg a, b;
wire sum, carry;
half_adder_dataflow
uut (
.a(a),
.b(b),
.sum(sum),
.carry(carry)
);
initial begin
a = 0; b = 0;
#10;
a = 0; b = 1;
#10;
a = 1; b = 0;
#10;
a = 1; b = 1;
#10;
end
initial begin
$monitor("Time =
%0t | a = %b, b = %b |
sum = %b, carry = %b",
$time, a, b, sum, carry);
end
endmodule
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Comparison of Gate-Level and Dataflow Modeling
1. Gate-Level Modeling
Description: In gate-level modeling, the circuit is described using basic logic gates
(e.g., and, or, xor, etc.). The connections between gates are explicitly defined.
Code Example:
xor(sum, a, b); // XOR gate for sum
and(carry, a, b); // AND gate for carry
Advantages:
o Closely resembles the physical implementation of the circuit.
o Useful for low-level design and optimization.
Disadvantages:
o Verbose and less intuitive for complex circuits.
o Requires explicit instantiation of gates.
2.Dataflow Modeling
Description: In dataflow modeling, the circuit is described using continuous assignments
(assign statements) that represent the flow of data. The focus is on the relationships between
inputs and outputs rather than the specific gates.
Code Example:
assign sum = a ^ b; // XOR operation for sum
assign carry = a & b; // AND operation for carry
Advantages:
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o More concise and easier to read for complex circuits.
o Focuses on the functionality rather than the implementation details.
Disadvantages:
o Less control over the actual hardware implementation.
o May not be suitable for low-level optimization.
Observations/ Conclusion:
Gate-Level Modeling is closer to the actual hardware implementation and is
useful for low-level design.
Dataflow Modeling is more abstract and focuses on the functionality, making it
easier to write and understand for complex designs.
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