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 ANALOG
CIRCUITS
and DEVICES

© 2003 by CRC Press LLC

 ANALOG
CIRCUITS
and DEVICES
Editor-in-Chief
Wai-Kai Chen

C RC P R E S S
Boca Raton London New York Washington, D.C.

© 2003 by CRC Press LLC

 Library of Congress Cataloging-in-Publication Data

Catalog record is available from the Library of Congress

This book contains information obtained from authentic and highly regarded sources. Reprinted material is quoted with
permission, and sources are indicated. A wide variety of references are listed. Reasonable efforts have been made to publish
reliable data and information, but the authors and the publisher cannot assume responsibility for the validity of all materials
or for the consequences of their use.

Neither this book nor any part may be reproduced or transmitted in any form or by any means, electronic or mechanical,
including photocopying, microfilming, and recording, or by any information storage or retrieval system, without prior
permission in writing from the publisher.

All rights reserved. Authorization to photocopy items for internal or personal use, or the personal or internal use of specific
clients, may be granted by CRC Press LLC, provided that $1.50 per page photocopied is paid directly to Copyright Clearance
Center, 222 Rosewood Drive, Danvers, MA 01923 USA The fee code for users of the Transactional Reporting Service is
ISBN 0-8493-1736-3/03/$0.00+$1.50. The fee is subject to change without notice. For organizations that have been granted
a photocopy license by the CCC, a separate system of payment has been arranged.

The consent of CRC Press LLC does not extend to copying for general distribution, for promotion, for creating new works,
or for resale. Specific permission must be obtained in writing from CRC Press LLC for such copying.

Direct all inquiries to CRC Press LLC, 2000 N.W. Corporate Blvd., Boca Raton, Florida 33431.

Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used only for
identification and explanation, without intent to infringe.

Visit the CRC Press Web site at www.crcpress.com

The material included here first appeared in The VLSI Handbook (CRC Press, 2000), Wai-Kai Chen, editor.
© 2003 by CRC Press LLC

No claim to original U.S. Government works

International Standard Book Number 0-8493-1736-3
Printed in the United States of America 1 2 3 4 5 6 7 8 9 0
Printed on acid-free paper

© 2003 by CRC Press LLC

 Preface

The purpose of Analog Circuits and Devices is to provide, in a single volume, a comprehensive reference
covering the broad spectrum of devices and their models, amplifiers, analog circuits and filters, and
compound semiconductor digital integrated circuit technology. The book has been written and developed
for practicing electrical engineers in industry, government, and academia. The goal is to provide the most
up-to-date information in the field.
Over the years, the fundamentals of the field have evolved to include a wide range of topics and a
broad range of practice. To encompass such a wide range of knowledge, the book focuses on the key
concepts, models, and equations that enable the design engineer to analyze, design, and predict the
behavior of large-scale systems. While design formulas and tables are listed, emphasis is placed on the
key concepts and theories underlying the processes.
The book stresses fundamental theory behind professional applications. In order to do so, the text is
reinforced with frequent examples. Extensive development of theory and details of proofs have been
omitted. The reader is assumed to have a certain degree of sophistication and experience. However, brief
reviews of theories, principles, and mathematics of some subject areas are given.
The compilation of this book would not have been possible without the dedication and efforts of John
Choma, Jr., Rolf Schaumann, Bang-Sup Song, Stephen I. Long, and, most of all, the contributing authors.
I wish to thank them all.

Wai-Kai Chen
Editor-in-Chief

© 2003 by CRC Press LLC

 Editor-in-Chief

Wai-Kai Chen is Professor and Head Emeritus of the Department of

Electrical Engineering and Computer Science at the University of
Illinois at Chicago. He is now serving as Academic Vice President at
International Technological University. He received his B.S. and M.S.
in electrical engineering at Ohio University, where he was later rec-
ognized as a Distinguished Professor. He earned his Ph.D. in electrical
engineering at University of Illinois at Urbana/Champaign.
Professor Chen has extensive experience in education and industry
and is very active professionally in the fields of circuits and systems.
He has served as visiting professor at Purdue University, University
of Hawaii at Manoa, and Chuo University in Tokyo, Japan. He was
editor of the IEEE Transactions on Circuits and Systems, Series I and
II, president of the IEEE Circuits and Systems Society, and is the
founding editor and editor-in-chief of the Journal of Circuits, Systems
and Computers. He received the Lester R. Ford Award from the Math-
ematical Association of America, the Alexander von Humboldt Award from Germany, the JSPS Fellowship
Award from Japan Society for the Promotion of Science, the Ohio University Alumni Medal of Merit for
Distinguished Achievement in Engineering Education, the Senior University Scholar Award and the 2000
Faculty Research Award from the University of Illinois at Chicago, and the Distinguished Alumnus Award
from the University of Illinois at Urbana/Champaign. He is the recipient of the Golden Jubilee Medal,
the Education Award, and the Meritorious Service Award from IEEE Circuits and Systems Society, and the
Third Millennium Medal from the IEEE. He has also received more than a dozen honorary professorship
awards from major institutions in China.
A fellow of the Institute of Electrical and Electronics Engineers and the American Association for the
Advancement of Science, Professor Chen is widely known in the profession for his Applied Graph Theory
(North-Holland), Theory and Design of Broadband Matching Networks (Pergamon Press), Active Network
and Feedback Amplifier Theory (McGraw-Hill), Linear Networks and Systems (Brooks/Cole), Passive and
Active Filters: Theory and Implements (John Wiley), Theory of Nets: Flows in Networks (Wiley-Interscience),
and The VLSI Handbook and The Circuits and Filters Handbook (CRC Press).

vii

© 2003 by CRC Press LLC

 Contributors

R. Jacob Baker Donald B. Estreich

University of Idaho Hewlett-Parkard Company
Boise, Idaho Santa Rosa, California

Andrea Baschirotto John W. Fattaruso

Università di Pavia Texas Instruments, Incorporated
Pavia, Italy Dallas, Texas

Marc Borremans Mohammed Ismail

Katholieke Universiteit Leuven The Ohio State University
Leuven-Heverlee, Belgium Columbus, Ohio

Charles E. Chang Johan Janssens

Conexant Systems, Inc. Katholieke Universiteit Leuven
Newbury Park, California Leuven-Heverlee, Belgium

David J. Comer John M. Khoury

Brigham Young University Lucent Technologies
Provo, Utah Murray Hill, New Jersey

Donald T. Comer Thomas H. Lee

Brigham Young University Stanford University
Provo, Utah Stanford, California

Bram De Muer Harry W. Li

Katholieke Universiteit Leaven University of Idaho
Leuven-Heverlee, Belgium Moscow, Idaho

Geert A. De Veirman Chi-Hung Lin

Silicon Systems, Inc. The Ohio State University
Tustin, California Columbus, Ohio

Maria del MarHershenson Stephen I. Long

Stanford University University of California
Stanford, California Santa Barbara, California

ix

© 2003 by CRC Press LLC

Sunderarajan S. Mohan Meera Venkataraman
Stanford University Troika Networks, Inc.
Stanford, California Calabasas Hills, California

Alison Payne Chorng-kuang Wang

Imperial College National Taiwan University
University of London Taipei, Taiwan
London, England
R.F. Wassenaar
Hirad Samavati University of Twente
Stanford University Enschede, The Netherlands
Stanford, California
Louis A. Williams, III
Bang-Sup Song Texas Instruments, Inc.
University of California Dallas, Texas
La Jolla, California
Min-shueh Yuan
Michiel Steyaert National Taiwan University
Katholieke Universiteit Leuven Taipei, Taiwan
Leuven-Heverlee, Belgium
C. Patrick Yue
Donald C. Thelen Stanford University
Analog Interfaces Stanford, California
Bozeman, Montana

Chris Toumazou
Imperial College
University of London
London, England

© 2003 by CRC Press LLC

 Contents

1 Bipolar Junction Transistor (BJT) Circuits David J. Comer and Donald T. Comer
1.1 Introduction .........................................................................................................................1-1
1.2 Physical Characteristics and Properties of the BJT ..............................................................1-2
1.3 Basic Operation of the BJT....................................................................................................1-2
1.4 Use of the BJT as an Amplifier .............................................................................................1-5
1.5 Representing the Major BJT Effects by an Electronic Model ..............................................1-6
1.6 Other Physical Effects in the BJT .........................................................................................1-6
1.7 More Accurate BJT Models ..................................................................................................1-8
1.8 Heterojunction Bipolar Junction Transistors ......................................................................1-8
1.9 Integrated Circuit Biasing Using Current Mirrors ..............................................................1-9
1.10 The Basic BJT Switch ..........................................................................................................1-14
1.11 High-Speed BJT Switching .................................................................................................1-16
1.12 Simple Logic Gates ..............................................................................................................1-19
1.13 Emitter-Coupled Logic .......................................................................................................1-19

2 RF Passive IC Components Thomas H. Lee, Maria del MarHershenson,

Sunderarajan S. Mohan, Hirad Samavati, and C. Patrick Yue
2.1 Introduction .........................................................................................................................2-1
2.2 Fractal Capacitors .................................................................................................................2-1
2.3 Spiral Inductors ....................................................................................................................2-8
2.4 On-Chip Transformers .......................................................................................................2-14

3 CMOS Amplifier Design Harry W. Li, R. Jacob Baker, and Donald C. Thelen
3.1 Introduction ..........................................................................................................................3-1
3.2 Biasing Circuits .....................................................................................................................3-7
3.3 Amplifiers ...........................................................................................................................3-15

4 Bipolar Amplifier Design Geert A. De Veirman

4.1 Introduction .........................................................................................................................4-1
4.2 Single-Transistor Amplifiers ................................................................................................4-1
4.3 Differential Amplifiers ........................................................................................................4-22
4.4 Output Stages ......................................................................................................................4-40
4.5 Bias Reference .....................................................................................................................4-45
4.6 Operational Amplifiers .......................................................................................................4-49
4.7 Conclusion ..........................................................................................................................4-56

xi

© 2003 by CRC Press LLC

 5 High-Frequency Amplifiers Chris Toumazou and Alison Payne
5.1 Introduction .........................................................................................................................5-1
5.2 The Current Feedback Op-Amp ..........................................................................................5-2
5.3 RF Low-Noise Amplifiers ...................................................................................................5-12
5.4 Optical Low-Noise Preamplifiers .......................................................................................5-18
5.5 Fundamentals of RF Power Amplifier Design ...................................................................5-24
5.6 Applications of High-Q Resonators in IF-Sampling Receiver Architectures ....................5-29
5.7 Log-Domain Processing .....................................................................................................5-36

6 Operational Transconductance Amplifiers R.F. Wassenaar, Mohammed Ismail, and

Chi-Hung Lin
6.1 Introduction .........................................................................................................................6-1
6.2 Noise Behavior of the OTA ..................................................................................................6-1
6.3 An OTA with an Improved Output Swing ..........................................................................6-4
6.4 OTAs with High Drive Capability.........................................................................................6-6
6.5 Common-Mode Feedback .................................................................................................6-14
6.6 Filter Applications with Low-Voltage OTAs ......................................................................6-16

7 Nyquist-Rate ADC and DAC Bang-Sup Song

7.1 Introduction ..........................................................................................................................7-1
7.2 ADC Design Arts ...................................................................................................................7-5
7.3 ADC Architectures ................................................................................................................7-7
7.4 ADC Design Considerations ...............................................................................................7-18
7.5 DAC Design Arts .................................................................................................................7-22
7.6 DAC Architectures ..............................................................................................................7-23
7.7 DAC Design Considerations ...............................................................................................7-27

8 Oversampled Analog-to-Digital and Digital-to-Analog Converters

John W. Fattaruso and Louis A. Williams, III
8.1 Introduction ..........................................................................................................................8-1
8.2 Basic Theory of Operation ....................................................................................................8-2
8.3 Alternative Sigma-Delta Architectures ...............................................................................8-14
8.4 Filtering for Sigma-Delta Modulators.................................................................................8-19
8.5 Circuit Building Blocks .......................................................................................................8-21
8.6 Practical Design Issues.........................................................................................................8-30
8.7 Summary..............................................................................................................................8-36

9 RF Communication Circuits Michiel Steyaert, Marc Borremans, Johan Janssens, and

Bram De Muer
9.1 Introduction ..........................................................................................................................9-1
9.2 Technology ............................................................................................................................9-2
9.3 The Receiver ..........................................................................................................................9-4
9.4 The Synthesizer....................................................................................................................9-12
9.5 The Transmitter...................................................................................................................9-17

xii

© 2003 by CRC Press LLC

 9.6 Toward Fully Integrated Transceivers.................................................................................9-25
9.7 Conclusions .........................................................................................................................9-25

10 PLL Circuits Min-shueh Yuan and Chorng-kuang Wang

10.1 Introduction ........................................................................................................................10-1
10.2 PLL Techniques ...................................................................................................................10-2
10.3 Building Blocks of the PLL Circuit....................................................................................10-18
10.4 PLL Applications ...............................................................................................................10-22

11 Continuous-Time Filters John M. Khoury

11.1 Introduction ........................................................................................................................11-1
11.2 State-Variable Synthesis Techniques...................................................................................11-2
11.3 Realization of VLSI Integrators...........................................................................................11-9
11.4 Filter Tuning Circuits ........................................................................................................11-25
11.5 Conclusion.........................................................................................................................11-30

12 Switched-Capacitor Filters Andrea Baschirotto

12.1 Introduction ........................................................................................................................12-1
12.2 Sampled-Data Analog Filters...............................................................................................12-2
12.3 The Principle of the SC Technique .....................................................................................12-4
12.4 First-Order SC Stages ..........................................................................................................12-6
12.5 Second-Order SC Circuit ....................................................................................................12-9
12.6 Implementation Aspects....................................................................................................12-14
12.7 Performance Limitations...................................................................................................12-18
12.8 Compensation Technique (Performance Improvements) ...............................................12-22
12.9 Advanced SC Filter Solutions............................................................................................12-27

13 Materials Stephen I. Long

13.1 Introduction ........................................................................................................................13-1
13.2 Compound Semiconductor Materials ................................................................................13-1
13.3 Why III-V Semiconductors?................................................................................................13-2
13.4 Heterojunctions...................................................................................................................13-3

14 Compound Semiconductor Devices for Digital Circuits Donald B. Estreich

14.1 Introduction ........................................................................................................................14-1
14.2 Unifying Principle for Active Devices: Charge Control Principle......................................14-1
14.3 Comparing Unipolar and Bipolar Transistors....................................................................14-6
14.4 Typical Device Structures..................................................................................................14-13

15 Logic Design Principles and Examples Stephen I. Long

15.1 Introduction ........................................................................................................................15-1
15.2 Static Logic Design ..............................................................................................................15-1
15.3 Transient Analysis and Design for Very-High-Speed Logic...............................................15-8

xiii

© 2003 by CRC Press LLC

16 Logic Design Examples Charles E. Chang, Meera Venkataraman, and Stephen I. Long
16.1 Design of MESFET and HEMT Logic Circuits ...................................................................16-1
16.2 HBT Logic Design Examples.............................................................................................16-10

xiv

© 2003 by CRC Press LLC

 1
Bipolar Junction
Transistor (BJT) Circuits

1.1 Introduction ........................................................................1-1

1.2 Physical Characteristics and Properties of the BJT ..........1-2
1.3 Basic Operation of the BJT ................................................1-2
1.4 Use of the BJT as an Amplifier ..........................................1-5
1.5 Representing the Major BJT Effects
by an Electronic Model.......................................................1-6
1.6 Other Physical Effects in the BJT.......................................1-6
Ohmic Effects • Base-Width Modulation (Early
Effect) • Reactive Effects
1.7 More Accurate BJT Models ................................................1-8
1.8 Heterojunction Bipolar Junction Transistors ....................1-8
1.9 Integrated Circuit Biasing Using Current Mirrors ...........1-9
Current Source Operating Voltage Range • Current Mirror
Analysis • Current Mirror with Reduced Error • The Wilson
Current Mirror
1.10 The Basic BJT Switch ........................................................1-14
1.11 High-Speed BJT Switching ...............................................1-16
Overall Transient Response
David J. Comer 1.12 Simple Logic Gates............................................................1-19
Donald T. Comer 1.13 Emitter-Coupled Logic .....................................................1-19
Brigham Young University A Closer Look at the Differential Stage

1.1 Introduction
The bipolar junction transistor (or BJT) was the workhorse of the electronics industry from the 1950s
through the 1990s. This device was responsible for enabling the computer age as well as the modern era
of communications. Although early systems that demonstrated the feasibility of electronic computers
used the vacuum tube, the element was too unreliable for dependable, long-lasting computers. The
invention of the BJT in 19471 and the rapid improvement in this device led to the development of highly
reliable electronic computers and modern communication systems.
Integrated circuits, based on the BJT, became commercially available in the mid-1960s and further
improved the dependability of the computer and other electronic systems while reducing the size and
cost of the overall system. Ultimately, the microprocessor chip was developed in the early 1970s and the
age of small, capable, personal computers was ushered in. While the metal-oxide-semiconductor (or
MOS) device is now more prominent than the BJT in the personal computer arena, the BJT is still
important in larger high-speed computers. This device also continues to be important in communication
systems and power control systems.

1-1

© 2003 by CRC Press LLC

1-2 Analog Circuits and Devices

Because of the continued improvement in BJT performance and the development of the heterojunction
BJT, this device remains very important in the electronics field, even as the MOS device becomes more
significant.

1.2 Physical Characteristics and Properties of the BJT

Although present BJT technology is used to make both discrete component devices as well as integrated
circuit chips, the basic construction techniques are similar in both cases, with primary differences arising
in size and packaging. The following description is provided for the BJT constructed as integrated circuit
devices on a silicon substrate. These devices are referred to as “junction-isolated” devices.
The cross-sectional view of a BJT is shown in Fig. 1.1.2
This device can occupy a surface area of less than 1000 mm2. There are three physical regions comprising
the BJT. These are the emitter, the base, and the collector. The thickness of the base region between
emitter and collector can be a small fraction of a micron, while the overall vertical dimension of a device
may be a few microns.
Thousands of such devices can be fabricated within a silicon wafer. They may be interconnected on
the wafer using metal deposition techniques to form a system such as a microprocessor chip or they may
be separated into thousands of individual BJTs, each mounted in its own case. The photolithographic
methods that make it possible to simultaneously construct thousands of BJTs have led to continually
decreasing size and cost of the BJT.
Electronic devices, such as the BJT, are governed by current–voltage relationships that are typically
nonlinear and rather complex. In general, it is difficult to analyze devices that obey nonlinear equations,
much less develop design methods for circuits that include these devices. The basic concept of modeling
an electronic device is to replace the device in the circuit with linear components that approximate the
voltage–current characteristics of the device. A model can then be defined as a collection of simple
components or elements used to represent a more complex electronic device. Once the device is replaced
in the circuit by the model, well-known circuit analysis methods can be applied.
There are generally several different models for a given device. One may be more accurate than others,
another may be simpler than others, another may model the dc voltage–current characteristics of the
device, while still another may model the ac characteristics of the device.
Models are developed to be used for manual analysis or to be used by a computer. In general, the
models for manual analysis are simpler and less accurate, while the computer models are more complex
and more accurate. Essentially, all models for manual analysis and most models for the computer include
only linear elements. Nonlinear elements are included in some computer models, but increase the
computation times involved in circuit simulation over the times in simulation of linear models.

1.3 Basic Operation of the BJT

In order to understand the origin of the elements used to model the BJT, we will discuss a simplified
version of the device as shown in Fig. 1.2. The device shown is an npn device that consists of a p-doped

FIGURE 1.1 An integrated npn BJT.

© 2003 by CRC Press LLC

Bipolar Junction Transistor (BJT) Circuits 1-3

FIGURE 1.2 Distribution of electrons in the active region.

material interfacing on opposite sides to n-doped material. A pnp device can be created using an n-doped
central region with p-doped interfacing regions. Since the npn type of BJT is more popular in present
construction processes, the following discussion will center on this device.
The geometry of the device implied in Fig. 1.2 is physically more like the earlier alloy transistor. This
geometry is also capable of modeling the modern BJT (Fig. 1.1) as the theory applies almost equally well
to both geometries. Normally, some sort of load would appear in either the collector or emitter circuit;
however, this is not important to the initial discussion of BJT operation.
The circuit of Fig. 1.2 is in the active region, that is, the emitter–base junction is forward-biased, while
the collector–base junction is reverse-biased. The current flow is controlled by the profile of electrons in
the p-type base region. It is proportional to the slope or gradient of the free electron density in the base
region. The well-known diffusion equation can be expressed as:3

dn qD n An ( 0 )
I = qD n A ------ = – ------------------------
- (1.1)
dx W

where q is the electronic charge, Dn is the diffusion constant for electrons, A is the cross-sectional area
of the base region, W is the width or thickness of the base region, and n(0) is the density of electrons at
the left edge of the base region. The negative sign reflects the fact that conventional current flow is
opposite to the flow of the electrons.
The concentration of electrons at the left edge of the base region is given by:

qV BE § kT
n ( 0 ) = n bo e (1.2)

where q is the charge on an electron, k is Boltzmann’s constant, T is the absolute temperature, and nbo
is the equilibrium concentration of electrons in the base region. While nbo is a small number, n(0) can

© 2003 by CRC Press LLC

1-4 Analog Circuits and Devices

be large for values of applied base to emitter voltages of 0.6 to 0.7 V. At room temperature, this equation
can be written as:

V BE § 0.026
n ( 0 ) = n bo e (1.3)

In Fig. 1.2, the voltage VEB = –VBE.

A component of hole current also flows across the base–emitter junction from base to emitter. This
component is rendered negligible compared to the electron component by doping the emitter region
much more heavily than the base region.
As the concentration of electrons at the left edge of the base region increases, the gradient increases
and the current flow across the base region increases. The density of electrons at x = 0 can be controlled
by the voltage applied from emitter to base. Thus, this voltage controls the current flowing through the
base region. In fact, the density of electrons varies exponentially with the applied voltage from emitter
to base, resulting in an exponential variation of current with voltage.
The reservoir of electrons in the emitter region is unaffected by the applied emitter-to-base voltage as
this voltage drops across the emitter–base depletion region. This applied voltage lowers the junction
voltage as it opposes the built-in barrier voltage of the junction. This leads to the increase in electrons
flowing from emitter to base.
The electrons injected into the base region represent electrons that were originally in the emitter. As
these electrons leave the emitter, they are replaced by electrons from the voltage source, VEB. This current
is called emitter current and its value is determined by the voltage applied to the junction. Of course,
conventional current flows in the opposite direction to the electron flow.
The emitter electrons flow through the emitter, across the emitter–base depletion region, and into
the base region. These electrons continue across the base region, across the collector–base depletion
region, and through the collector. If no electrons were “lost” in the base region and if the hole flow
from base to emitter were negligible, the current flow through the emitter would equal that through
the collector. Unfortunately, there is some recombination of carriers in the base region. When electrons
are injected into the base region from the emitter, space charge neutrality is upset, pulling holes into
the base region from the base terminal. These holes restore space charge neutrality if they take on the
same density throughout the base as the electrons. Some of these holes recombine with the free
electrons in the base and the net flow of recombined holes into the base region leads to a small, but
finite, value of base current. The electrons that recombine in the base region reduce the total electron
flow to the collector. Because the base region is very narrow, only a small percentage of electrons
traversing the base region recombine and the emitter current is reduced by a small percentage as it
becomes collector current.
In a typical low-power BJT, the collector current might be 0.995IE. The current gain from emitter to
collector, IC /IE, is called a and is a function of the construction process for the BJT. Using Kirchhoff ’s
current law, the base current is found to equal the emitter current minus the collector current. This gives:

I B = I E – I C = ( 1 – a )I E (1.4)

If a = 0.995, then IB = 0.005IE. Base current is very small compared to emitter or collector current. A
parameter b is defined as the ratio of collector current to base current resulting in:

a
b = ------------ (1.5)
1–a

This parameter represents the current gain from base to collector and can be quite high. For the value
of a cited earlier, the value of b is 199.

© 2003 by CRC Press LLC

Bipolar Junction Transistor (BJT) Circuits 1-5

1.4 Use of the BJT as an Amplifier

Figure 1.3 shows a simple configuration of a BJT amplifier. This circuit is known as the common emitter
configuration.
A voltage source is not typically used to forward-bias the base–emitter junction in an actual circuit,
but we will assume that VBB is used for this purpose. A value of VBB or VBE near 0.6 to 0.7 V would be
appropriate for this situation. The collector supply would be a large voltage, such as 12 V. We will assume
that the value of VBB sets the dc emitter current to a value of 1 mA for this circuit. The collector current
entering the BJT will be slightly less than 1 mA, but we will ignore this difference and assume that IC =
1 mA also. With a 4-kW collector resistance, a 4-V drop will appear across RC , leading to a dc output
voltage of 8 V. The distribution of electrons across the base region for the steady-state or quiescent
conditions is shown by the solid line of Fig. 1.3(a).
If a small ac voltage now appears in series with VBB, the injected electron density at the left side
of the base region will be modulated. Since this density varies exponentially with the applied voltage
(see Eq. 1.2), a small ac voltage can cause considerable changes in density. The dashed lines in Fig.
1.3(a) show the distributions at the positive and negative peak voltages. The collector current may
change from its quiescent level of 1 mA to a maximum of 1.1 mA as ein reaches its positive peak, and
to a minimum of 0.9 mA when ein reaches its negative peak. The output collector voltage will drop
to a minimum value of 7.6 V as the collector current peaks at 1.1 mA, and will reach a maximum
voltage of 8.4 V as the collector current drops to 0.9 mA. The peak-to-peak ac output voltage is then
0.8 V. The peak-to-peak value of ein to cause this change might be 5 mV, giving a voltage gain of A
= –0.8/0.005 = –160. The negative sign occurs because when ein increases, the collector current
increases, but the collector voltage decreases. This represents a phase inversion in the amplifier of
Fig. 1.3.
In summary, a small change in base-to-emitter voltage causes a large change in emitter current. This
current is channeled across the collector, through the load resistance, and can develop a larger incremental
voltage across this resistance.

FIGURE 1.3 A BJT amplifier.

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1-6 Analog Circuits and Devices

FIGURE 1.4 Large-signal model of the BJT.

1.5 Representing the Major BJT Effects by an Electronic Model

The two major effects of the BJT in the active region are the diode characteristics of the base–emitter
junction and the collector current that is proportional to the emitter current. These effects can be modeled
by the circuit of Fig. 1.4.
The simple diode equation represents the relationship between applied emitter-to-base voltage and
emitter current. This equation can be written as

qV BE § kT
IE = I1 ( e – 1) (1.6)

where q is the charge on an electron, k is Boltzmann’s constant, T is the absolute temperature of the
diode, and I1 is a constant at a given temperature that depends on the doping and geometry of the emitter-
base junction.
The collector current is generated by a dependent current source of value IC = aIE.
A small-signal model based on the large-signal model of Fig. 1.4 is shown in Fig. 1.5. In this case, the
resistance, rd, is the dynamic resistance of the emitter-base diode and is given by:

kT
r d = ------- (1.7)
qI E

where IE is the dc emitter current.

1.6 Other Physical Effects in the BJT

The preceding section pertains to the basic operation of the BJT in the dc and midband frequency range.
Several other effects must be included to model the BJT with more accuracy. These effects will now be
described.

Ohmic Effects
The metal connections to the semiconductor regions exhibit some ohmic resistance. The emitter contact
resistance and collector contact resistance is often in the ohm range and does not affect the BJT operation
in most applications. The base region is very narrow and offers little area for a metal contact. Furthermore,
because this region is narrow and only lightly doped compared to the emitter, the ohmic resistance of
the base region itself is rather high. The total resistance between the contact and the intrinsic base region
can be 100 to 200 W. This resistance can become significant in determining the behavior of the BJT,
especially at higher frequencies.

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Bipolar Junction Transistor (BJT) Circuits 1-7

FIGURE 1.5 A small-signal model of the BJT.

Base-Width Modulation (Early Effect)

The widths of the depletion regions are functions of the applied voltages. The collector voltage generally
exhibits the largest voltage change and, as this voltage changes, so also does the collector–base depletion
region width. As the depletion layer extends further into the base region, the slope of the electron
distribution in the base region becomes greater since the width of the base region is decreased. A slightly
steeper slope leads to slightly more collector current. As reverse-bias decreases, the base width becomes
greater and the current decreases. This effect is called base-width modulation and can be expressed in
terms of the Early voltage,4 VA, by the expression:

V CEˆ
I C = bI B Ê 1 + -------
- (1.8)
Ë VA ¯

The Early voltage will be constant for a given device and is typically in the range of 60 to 100 V.

Reactive Effects
Changing the voltages across the depletion regions results in a corresponding change in charge. This
leads to an effective capacitance since

dQ
C = ------- (1.9)
dV

This depletion region capacitance is a function of voltage applied to the junction and can be written as:4

C Jo
C dr = --------------------------
m
(1.10)
( f – V app )

where CJo is the junction capacitance at zero bias, f is the built-in junction barrier voltage, Vapp is the
applied junction voltage, and m is a constant. For modern BJTs, m is near 0.33. The applied junction
voltage has a positive sign for a forward-bias and a negative sign for a reverse-bias. The depletion region
capacitance is often called the junction capacitance.
An increase in forward base–emitter voltage results in a higher density of electrons injected into the
base region. The charge distribution in the base region changes with this voltage change, and this leads
to a capacitance called the diffusion capacitance. This capacitance is a function of the emitter current and
can be written as:

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1-8 Analog Circuits and Devices

CD = k2 IE (1.11)

where k2 is a constant for a given device.

1.7 More Accurate BJT Models

Figure 1.6 shows a large-signal BJT model used in some versions of the popular simulation program
known as SPICE.5 The equations for the parameters are listed in other texts5 and will not be given here.
Figure 1.7 shows a small-signal SPICE model5 often called the hybrid-p equivalent circuit. The capaci-
tance, Cp, accounts for the diffusion capacitance and the emitter–base junction capacitance. The collec-
tor–base junction capacitance is designated Cm. The resistance, rp, is equal to (b + 1)rd. The transductance,
gm, is given by:

a
g m = ---- (1.12)
rd

The impedance, ro, is related to the Early voltage by:

V
r o = -----A- (1.13)
IC

RB, RE, and RC are the base, emitter, and collector resistances, respectively. For hand analysis, the ohmic
resistances RE and RC are neglected along with CCS, the collector-to-substrate capacitance.

1.8 Heterojunction Bipolar Junction Transistors

In an npn device, all electrons injected from emitter to base are collected by the collector, except for a
small number that recombine in the base region. The holes injected from base to emitter contribute to

FIGURE 1.6 A more accurate large-signal model of the BJT.

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Bipolar Junction Transistor (BJT) Circuits 1-9

FIGURE 1.7 The hybrid-p small-signal model for the BJT.

emitter junction current, but do not contribute to collector current. This hole component of the emitter
current must be minimized to achieve a near-unity current gain from emitter to collector. As a approaches
unity, the current gain from base to collector, b, becomes larger.
In order to produce high-b BJTs, the emitter region must be doped much more heavily than the base
region, as explained earlier. While this approach allows the value of b to reach several hundred, it also
leads to some effects that limit the frequency of operation of the BJT. The lightly doped base region
causes higher values of base resistance, as well as emitter–base junction capacitance. Both of these effects
are minimized in the heterojunction BJT (or HBJT). This device uses a different material for the base
region than that used for the emitter and collector regions. One popular choice of materials is silicon
for the emitter and collector regions, and a silicon/germanium material for the base region.6 The difference
in energy gap between the silicon emitter material and the silicon/germanium base material results in
an asymmetric barrier to current flow across the junction. The barrier for electron injection from emitter
to base is smaller than the barrier for hole injection from base to emitter. The base can then be doped
more heavily than a conventional BJT to achieve lower base resistance, but the hole flow across the
junction remains negligible due to the higher barrier voltage. The emitter of the HBJT can be doped
more lightly to lower the junction capacitance. Large values of b are still possible in the HBJT while
minimizing frequency limitations. Current gain-bandwidth figures exceeding 60 GHz have been achieved
with present industrial HBJTs.
From the standpoint of analysis, the SPICE models for the HBJT are structurally identical to those of
the BJT. The difference is in the parameter values.

1.9 Integrated Circuit Biasing Using Current Mirrors

Differential stages are very important in integrated circuit amplifier design. These stages require a constant
dc current for proper bias. A simple bias scheme for differential BJT stages will now be discussed.
The diode-biased current sink or current mirror of Fig. 1.8 is a popular method of creating a constant-
current bias for differential stages.
The concept of the current mirror was developed specifically for analog integrated circuit biasing and
is a good example of a circuit that takes advantage of the excellent matching characteristics that are
possible in integrated circuits. In the circuit of Fig. 1.8, the current I2 is intended to be equal to or “mirror”
the value of I1. Current mirrors can be designed to serve as sinks or sources.

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1-10 Analog Circuits and Devices

FIGURE 1.8 Current mirror bias stage.

The general function of the current mirror is to reproduce or mirror the input or reference current
to the output, while allowing the output voltage to assume any value within some specified range. The
current mirror can also be designed to generate an output current that equals the input current multiplied
by a scale factor K. The output current can be expressed as a function of input current as:

I O = KI IN (1.14)

where K can be equal to, less than, or greater than unity. This constant can be established accurately by
relative device sizes and will not vary with temperature.
Figure 1.9 shows a multiple output current source where all of the output currents are referenced to
the input current. Several amplifier stages can be biased with this multiple output current mirror.

Current Source Operating Voltage Range

Figure 1.10 shows an ideal or theoretical current sink in (a) and a practical sink in (b). The voltage at
node A in the theoretical sink can be tied to any potential above or below ground without affecting the
value of I. On the other hand, the practical circuit of Fig. 1.10(b) requires that the transistor remain in
the active region to provide a current of:

V B – V BE
I = a -------------------
-
R (1.15)

This requires that the collector voltage exceed the voltage VB at all times. The upper limit on this voltage
is determined by the breakdown voltage of the transistor. The output voltage must then satisfy:

V B < V C < ( V B + BV CE ) (1.16)

where BVCE is the breakdown voltage from collector to emitter of the transistor. This voltage range over
which the current source operates is called the output voltage compliance range or the output compliance.

© 2003 by CRC Press LLC

Bipolar Junction Transistor (BJT) Circuits 1-11

FIGURE 1.9 Multiple output current mirror.

FIGURE 1.10 Current sink circuits: (a) ideal sink, (b) practical sink.

Current Mirror Analysis

The current mirror is again shown in Fig. 1.11. If devices Q1 and Q2 are assumed to be matched devices,
we can write:

V BE § V T
I E1 = I E2 = I EO e (1.17)

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1-12 Analog Circuits and Devices

FIGURE 1.11 Circuit for current mirror analysis.

where VT = kT/q, IEO = AJEO , A is the emitter area of the two devices, and JEO is the current density of
the emitters. The base currents for each device will also be identical and can be expressed as:

I EO VBE § VT
I B1 = I B2 = -----------
-e (1.18)
b+1

Device Q1 operates in the active region, but near saturation by virtue of the collector–base connection.
This configuration is called a diode-connected transistor. Since the collector-to-emitter voltage is very
small, the collector current for device Q1 is given by Eq. 1.8, assuming VCE = 0. This gives:

b V §V
I C1 = bI B1 ª ------------I EO e BE T (1.19)
b+1

The device Q2 does not have the constraint that VCE ª 0 as device Q1 has. The collector voltage for Q2
will be determined by the external circuit that connects to this collector. Thus, the collector current for
this device is:

V C2ˆ
I C2 = bI B2 Ê 1 + -------
- (1.20)
Ë VA ¯

where VA is the Early voltage. In effect, the output stage has an output impedance given by Eq. 1.13. The
current mirror more closely approximates a current source as the output impedance becomes larger.
If we limit the voltage VC2 to small values relative to the Early voltage, IC2 is approximately equal to
IC1. For integrated circuit designs, the voltage required at the output of the current mirror is generally
small, making this approximation valid.
The input current to the mirror is larger than the collector current and is:

I IN = I C1 + 2I B (1.21)

Since IOUT = IC2 = IC1 = bIB, we can write Eq. 1.21 as:

I IN = bI B + 2I B = ( b + 2 )I B (1.22)

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Bipolar Junction Transistor (BJT) Circuits 1-13

Relating IIN to IOUT results in:

b I IN
I OUT = ------------I IN = ------------------
- (1.23)
b+2 1+2§b

For typical values of b, these two currents are essentially equal. Thus, a desired bias current, IOUT , is
generated by creating the desired value of IIN. The current IIN is normally established by connecting a
resistance R1 to a voltage source VCC to set IIN to:

V CC – V BE
I IN = ----------------------
- (1.24)
R1

Control of collector/bias current for Q2 is then accomplished by choosing proper values of VCC and R1.
Figure 1.12 shows a multiple-output current mirror.
It can be shown that the output current for each identical device in Fig. 1.12 is:

I IN
I O = ----------------------- (1.25)
1+N +1
-------------
b

where N is the number of output devices.

The current sinks can be turned into current sources by using pnp transistors and a power supply of
opposite polarity. The output devices can also be scaled in area to make IOUT larger or smaller than IIN.

Current Mirror with Reduced Error

The difference between output current in a multiple-output current mirror and the input current can
become quite large if N is large. One simple method of avoiding this problem is to use an emitter follower
to drive the bases of all devices in the mirror, as shown in Fig. 1.13.
The emitter follower, Q0, has a current gain from base to collector of b + 1, reducing the difference
between IO and IIN to:

N+1
I IN – I O = -------------I B (1.26)
b+1

FIGURE 1.12 Multiple-output current mirror.

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1-14 Analog Circuits and Devices

FIGURE 1.13 Improved multiple output current mirror.

The output current for each device is:

I IN
I O = ------------------------------ (1.27)
N+1
1 + -------------------- -
b(b + 1)

The Wilson Current Mirror

In the simple current mirrors discussed, it was assumed that the collector voltage of the output stage was
small compared to the Early voltage. When this is untrue, the output current will not remain constant,
but will increase as output voltage (VCE) increases. In other words, the output compliance range is limited
with these circuits due to the finite output impedance of the BJT.
A modification of the improved output current mirror of Fig. 1.13 was proposed by Wilson7 and is
illustrated in Fig. 1.14.
The Wilson current mirror is connected such that VCB2 = 0 and VBE1 = VBE0. Both Q1 and Q2 now
operate with a near-zero collector–emitter bias although the collector of Q0 might feed into a high-voltage
point. It can be shown that the output impedance of the Wilson mirror is increased by a factor of b/2
over the simple mirror. This higher impedance translates into a higher output compliance. This circuit
also reduces the difference between input and output current by means of the emitter follower stage.

1.10 The Basic BJT Switch

In digital circuits, the BJT is used as a switch to generate one of only two possible output voltage levels,
depending on the input voltage level. Each voltage level is associated with one of the binary digits, 0 or
1. Typically, the high voltage level may fall between 2.8 V and 5 V while the low voltage level may fall
between 0 V and 0.8 V.
Logic circuits are based on BJT stages that are either in cutoff with both junctions reverse-biased or
in a conducting mode with the emitter–base junction forward-biased. When the BJT is “on” or conducting
emitter current, it can be in the active region or the saturation region. If it is in the saturation region,
the collector–base region is also forward-biased.
The three possible regions of operation are summarized in Table 1.1.
The BJT very closely approximates certain switch configurations. For example, when the switch of Fig.
1.15(a) is open, no current flows through the resistor and the output voltage is +12 V. Closing the switch

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Bipolar Junction Transistor (BJT) Circuits 1-15

FIGURE 1.14 Wilson current mirror.

TABLE 1.1 Regions of Operation

Region Cutoff Active Saturation

C–B bias Reverse Reverse Forward

E–B bias Reverse Forward Forward

causes the output voltage to drop to zero volts and a current of 12/R flows through the resistance. When
the base voltage of the BJT of Fig. 1.15(b) is negative, the device is cut off and no collector current flows.
The output voltage is +12 V, just as in the case of the open switch. If a large enough current is now driven
into the base to saturate the BJT, the output voltage becomes very small, ranging from 20 mV to 500
mV, depending on the BJT used. The saturated state corresponds closely to the closed switch. During
the time that the BJT switches from cutoff to saturation, the active region equivalent circuit applies. For
high-speed switching of this circuit, appropriate reactive effects must be considered. For low-speed
switching, these reactive effects can be neglected.
Saturation occurs in the basic switching circuit of Fig. 1.15(b) when the entire power supply voltage
drops across the load resistance. No voltage, or perhaps a few tenths of volts, then appears from collector
to emitter. This occurs when the base current exceeds the value

V CC – V CE ( sat )
I B ( sat ) = ------------------------------
- (1.28)
bR L

When a transistor switch is driven into saturation, the collector–base junction becomes forward-
biased. This situation results in the electron distribution across the base region shown in Fig. 1.16.
The forward-bias of the collector–base junction leads to a non zero concentration of electrons in
the base that is unnecessary to support the gradient of carriers across this region. When the input
signal to the base switches to a lower level to either turn the device off or decrease the current
flow, the excess charge must be removed from the base region before the current can begin to
decrease.

© 2003 by CRC Press LLC

1-16 Analog Circuits and Devices

FIGURE 1.15 The BJT as a switch: (a) open switch, (b) closed switch.

FIGURE 1.16 Electron distribution in the base region of a saturated BJT.

1.11 High-Speed BJT Switching

There are three major effects that extend switching times in a BJT:
1. The depletion-region or junction capacitances are responsible for delay time when the BJT is in
the cutoff region.
2. The diffusion capacitance and the Miller-effect capacitance are responsible for the rise and fall
times of the BJT as it switches through the active region.
3. The storage time constant accounts for the time taken to remove the excess charge from the base
region before the BJT can switch from the saturation region to the active region.

© 2003 by CRC Press LLC

Bipolar Junction Transistor (BJT) Circuits 1-17

FIGURE 1.17 A simple switching circuit.

There are other second-order effects that are generally negligible compared to the previously listed
time lags.
Since the transistor is generally operating as a large-signal device, the parameters such as junction
capacitance or diffusion capacitance will vary as the BJT switches. One approach to the evaluation of
time constants is to calculate an average value of capacitance over the voltage swing that takes place.Not
only is this method used in hand calculations, but most computer simulation programs use average
values to speed calculations.

Overall Transient Response

Before discussing the individual BJT switching times, it is helpful to consider the response of a common-
emitter switch to a rectangular waveform. Figure 1.17 shows a typical circuit using an npn transistor.
A rectangular input pulse and the corresponding output are shown in Fig. 1.18. In many switching
circuits, the BJT must switch from its “off ” state to saturation and later return to the “off ” state. In this
case, the delay time, rise time, saturation storage time, and fall time must be considered in that order to
find the overall switching time.
The total waveform is made up of five sections: delay time, rise time, on time, storage time, and fall
time. The following list summarizes these points and serves as a guide for future reference:

td¢ = Passive delay time; time interval between application of forward base drive and start of collector-
current response.
td = Total delay time; time interval between application of forward base drive and the point at which
IC has reached 10% of the final value.
tr = Rise time; 10- to 90-% rise time of IC waveform.
ts¢ = Saturation storage time; time interval between removal of forward base drive and start of IC decrease.
ts = Total storage time; time interval between removal of forward base drive and point at which IC =
0.9IC(sat).
tf = Fall time; 90- to 10-% fall time of IC waveform
Ton = Total turn-on time; time interval between application of base drive and point at which IC has
reached 90% of its final value.

© 2003 by CRC Press LLC

1-18 Analog Circuits and Devices

FIGURE 1.18 Input and output waveforms.

Toff = Total turn-off time; time interval between removal of forward base drive and point at which IC
has dropped to 10% of its value during on time.
Not all applications will require evaluation of each of these switching times. For instance, if the base
drive is insufficient to saturate the transistor, ts will be zero. If the transistor never leaves the active region,
the delay time will also be zero.
The factors involved in calculating the switching times are summarized in the following paragraphs.8
The passive delay time is found from:

E on + E off ˆ
t¢d = t d ln Ê ---------------------------
- (1.29)
Ë E on – V BE ( on )¯

where td is the product of the charging resistance and the average value of the two junction capacitances.
The active region time constant is a function of the diffusion capacitance, the collector–base junction
capacitance, the transconductance, and the charging resistance. This time constant will be denoted by t.
If the transistor never enters saturation, the rise time is calculated from the well-known formula:

t r = 2.2t (1.30)

If the BJT is driven into saturation, the rise time is found from:8

K – 0.1
t r = t ln Ê -----------------ˆ (1.31)
Ë K – 0.9¯

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Bipolar Junction Transistor (BJT) Circuits 1-19

where K is the overdrive factor or the ratio of forward base current drive to the value needed for saturation.
The rise time for the case where K is large can be much smaller than the rise time for the nonsaturating
case (K < 1). Unfortunately, the saturation storage time increases for large values of K.
The saturation storage time is given by:

I B1 – I B2 ˆ
t¢s = t s ln Ê -----------------------
- (1.32)
Ë I B ( sat ) – I B2¯

where ts is the storage time constant, IB1 is the forward base current before switching, and IB2 is the
current after switching and must be less than IB(sat). The saturation storage time can slow the overall
switching time significantly. The higher speed logic gates utilize circuits that avoid the saturation region
for the BJTs that make up the gate.

1.12 Simple Logic Gates

Although the resistor-transistor-logic (RTL) family has not been used since the late 1960s, it demonstrates
the concept of a simple logic gate. Figure 1.19 shows a four-input RTL NOR gate.
If all four inputs are at the lower voltage level (e.g., 0 V), there is no conducting path from output to
ground. No voltage will drop across RL, and the output voltage will equal VCC. If any or all of the inputs
move to the higher voltage level (e.g., 4 V), any BJT with base connected to the higher voltage level will
saturate, pulling the output voltage down to a few tenths of a volt. If positive logic is used, with the high
voltage level corresponding to binary “1” and the low voltage level to binary “0,” the gate performs the
NOR function. Other logic functions can easily be constructed in the RTL family.
Over the years, the performance of logic gates has been improved by different basic configurations.
RTL logic was improved by diode-transistor-logic (DTL). Then, transistor-transistor-logic (TTL) became
very prominent. This family is still popular in the small-scale integration (SSI) and medium-scale
integration (MSI) areas, but CMOS circuits have essentially replaced TTL in large-scale integration (LSI)
and very-large-scale integration (VLSI) applications.
One popular family that is still prominent in very high-speed computer work is the emitter-coupled
logic (ECL) family. While CMOS packs many more circuits into a given area than ECL, the frequency
performance of ECL leads to its popularity in supercomputer applications.

1.13 Emitter-Coupled Logic

Emitter-coupled logic (ECL) was developed in the mid-1960s and remains the fastest silicon logic circuit
available. Present ECL families offer propagation delays in the range of 0.2 ns.9 The two major disadvan-
tages of ECL are: (1) resistors which require a great deal of IC chip area, must be used in each gate, and.
(2) the power dissipation of an ECL gate is rather high. These two shortcomings limit the usage of ECL
in VLSI systems. Instead, this family has been used for years in larger supercomputers that can afford
space and power to achieve higher speeds.
The high speeds obtained with ECL are primarily based on two factors. No device in an ECL gate is
ever driven into the saturation region and, thus, saturation storage time is never involved as devices
switch from one state to another. The second factor is that required voltage swings are not large. Voltage
excursions necessary to change an input from the low logic level to the high logic level are minimal.
Although noise margins are lower than other logic families, switching times are reduced in this way.
Figure 1.20 shows an older ECL gate with two separate outputs. For positive logic, X is the OR output
while Y is the NOR output.
Often, the positive supply voltage is taken as 0 V and VEE as –5 V due to noise considerations. The
diodes and emitter follower Q5 establish a temperature-compensated base reference for Q4. When inputs
A, B, and C are less than the voltage VB, Q4 conducts while Q1, Q2, and Q3 are cut off. If any one of the

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1-20 Analog Circuits and Devices

FIGURE 1.19 A four-input RTL NOR gate.

FIGURE 1.20 An ECL logic gate.

inputs is switched to the 1 level, which exceeds VB, the transistor turns on and pulls the emitter of Q4
positive enough to cut this transistor off. Under this condition, output Y goes negative while X goes
positive. The relatively large resistor common to the emitters of Q1, Q2, Q3, and Q4 prevents these

© 2003 by CRC Press LLC

Bipolar Junction Transistor (BJT) Circuits 1-21

transistors from saturating. In fact, with nominal logic levels of –1.9 V and –1.1 V, the current through
the emitter resistance is approximately equal before and after switching takes place. Thus, only the current
path changes as the circuit switches. This type of operation is sometimes called current mode switching.
Although the output stages are emitter followers, they conduct reasonable currents for both logic level
outputs and, therefore, minimize the asymmetrical output impedance problem.
In an actual ECL gate, the emitter follower load resistors are not fabricated on the chip. The newer
version of the gate replaces the emitter resistance of the differential stage with a current source, and
replaces the bias voltage circuit with a regulated voltage circuit.

A Closer Look at the Differential Stage

Figure 1.21 shows a simple differential stage similar to the input stage of an ECL gate.2 Both transistors
are biased by a current source, IT , called the tail current. The two input signals e1 and e2 make up a
differential input signal defined as:

ed = e1 – e2 (1.33)

This differential voltage can be expressed as the difference between the base–emitter junction voltages as:

e d = V BE1 – V BE2 (1.34)

The collector currents can be written in terms of the base–emitter voltages as:

V BE1 § V T V BE1 § V T
I C1 = aI EO e ª I EO e (1.35)

V BE2 § V T V BE2 § V T
I C2 = aI EO e ª I EO e (1.36)

where matched devices are assumed.

A differential output current can be defined as the difference of the collector currents, or

I d = I C1 – I C2 (1.37)

Since the tail current is IT = IC1 + IC2, taking the ratio of Id to IT gives:

I I C1 – I C2
----d = ------------------
- (1.38)
IT I C1 + I C2

Since VBE1 = ed + VBE2, we can substitute this value for VBE1 into Eq. 1.35 to write:

( e d + V BE2 ) § V T e § V T V BE2 § V T
I C1 = I EO e = I EO e d e (1.39)

Substituting Eqs. 1.36 and 1.39 into Eq. 1.38 results in:

e §V
I ed
e d T – 1- = tanh --------
----d = -------------------- - (1.40)
IT e
ed § VT
+1 2V T

or

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1-22 Analog Circuits and Devices

FIGURE 1.21 A simple differential stage similar to an ECL input stage.

ed
I d = I T tanh --------
- (1.41)
2V T

This differential current is graphed in Fig. 1.22.

When ed is zero, the differential current is also zero, implying equal values of collector currents in the
two devices. As ed increases, so also does Id until ed exceeds 4VT , at which time Id has reached a constant
value of IT . From the definition of differential current, this means that IC1 equals IT while IC2 is zero. As
the differential input voltage goes negative, the differential current approaches –IT as the voltage reaches
–4VT . In this case, IC2 = IT while IC1 goes to zero.
The implication here is that the differential stage can move from a balanced condition with IC1 = IC2
to a condition of one device fully off and the other fully on with an input voltage change of around 100
mV or 4VT . This demonstrates that a total voltage change of about 200 mV at the input can cause an
ECL gate to change states. This small voltage change contributes to smaller switching times for ECL logic.

FIGURE 1.22 Differential output current as a function of differential input voltage.

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Bipolar Junction Transistor (BJT) Circuits 1-23

FIGURE 1.23 Differential input stage with current mirror load.

The ability of a differential pair to convert a small change in differential base voltage to a large change
in collector voltage also makes it a useful building block for analog amplifiers. In fact, a differential pair
with a pnp transistor current mirror load, as illustrated in Fig. 1.23, is widely used as an input stage for
integrated circuit op-amps.

References
1. Brittain, J. E. (Ed.), Turning Points in American Electrical History, IEEE Press, New York, 1977, Sec.
II-D.
2. Comer, D. T., Introduction to Mixed Signal VLSI, Array Publishing, New York, 1994, Ch. 7.
3. Sedra, A. S. and Smith, K. C., Microelectronic Circuits, 4th ed., Oxford University Press, New York,
1998, Ch. 4.
4. Gray, P. R. and Meyer, R. G., Analysis and Design of Analog Integrated Circuits, 3rd ed., John Wiley
& Sons, Inc., New York, 1993, Ch. 1.
5. Vladimirescu, A., The Spice Book, John Wiley & Sons, Inc., New York, 1994, Ch. 3.
6. Streetman, B. G., Solid State Electronic Devices, 4th ed., Prentice-Hall, Englewood Cliffs, NJ, 1995,
Ch. 7.
7. Wilson, G. R., “A monolithic junction FET - NPN operational amplifier,” IEEE J. Solid-State Circuits,
Vol. SC-3, pp. 341-348, Dec. 1968.
8. Comer, D. J., Modern Electronic Circuit Design, Addison-Wesley, Reading, MA, 1977, Ch. 8.
9. Motorola Technical Staff, High Performance ECL Data, Motorola, Inc., Phoenix, AZ, 1993, Ch. 3.

© 2003 by CRC Press LLC

 2
RF Passive IC
Components

2.1 Introduction ........................................................................2-1

2.2 Fractal Capacitors................................................................2-1
Lateral Flux Capacitors • Fractals • Fractal Capacitor
Thomas H. Lee Structures
Maria del MarHershenson 2.3 Spiral Inductors...................................................................2-8
Understanding Substrate Effects • Simple, Accurate
Sunderarajan S. Mohan Expressions for Planar Spiral Inductances
Hirad Samavati 2.4 On-Chip Transformers .....................................................2-14
C. Patrick Yue Monolithic Transformer Realizations • Analytical
Stanford University Transformer Models

2.1 Introduction
Passive energy storage elements are widely used in radio-frequency (RF) circuits. Although their imped-
ance behavior often can be mimicked by compact active circuitry, it remains true that passive elements
offer the largest dynamic range and the lowest power consumption. Hence, the highest performance will
always be obtained with passive inductors and capacitors. Unfortunately, standard integrated circuit
technology has not evolved with a focus on providing good passive elements. This chapter describes the
limited palette of options available, as well as means to make the most use out of what is available.

2.2 Fractal Capacitors

Of capacitors, the most commonly used are parallel-plate and MOS structures. Because of the thin gate
oxides now in use, capacitors made out of MOSFETs have the highest capacitance density of any standard
IC option, with a typical value of approximately 7 fF/mm2 for a gate oxide thickness of 5 nm. A drawback,
however, is that the capacitance is voltage dependent. The applied potential must be well in excess of a
threshold voltage in order to remain substantially constant. The relatively low breakdown voltage (on
the order of 0.5 V/nm of oxide) also imposes an unwelcome constraint on allowable signal amplitudes.
An additional drawback is the effective series resistance of such structures, due to the MOS channel
resistance. This resistance is particularly objectionable at radio frequencies, since the impedance of the
combination may be dominated by this resistive portion.
Capacitors that are free of bias restrictions (and that have much lower series resistance) may be formed
out of two (or more) layers of standard interconnect metal. Such parallel-plate capacitors are quite linear
and possess high breakdown voltage, but generally offer capacitance density two orders of magnitude
lower than the MOSFET structure. This inferior density is the consequence of a conscious and continuing
effort by technologists to keep low the capacitance between interconnect layers. Indeed, the vertical
spacing between such layers generally does not scale from generation to generation. As a result, the

2-1

© 2003 by CRC Press LLC

2-2 Analog Circuits and Devices

disparity between MOSFET capacitance density and that of the parallel-plate structure continues to grow
as technology scales.
A secondary consequence of the low density is an objectionably high capacitance between the bottom
plate of the capacitor and the substrate. This bottom-plate capacitance is often a large fraction of the
main capacitance. Needless to say, this level of parasitic capacitance is highly undesirable.
In many circuits, capacitors can occupy considerable area, and an area-efficient capacitor is therefore
highly desirable. Recently, a high-density capacitor structure using lateral fringing and fractal geometries
has been introduced.1 It requires no additional processing steps, and so it can be built in standard digital
processes. The linearity of this structure is similar to that of the conventional parallel-plate capacitor.
Furthermore, the bottom-plate parasitic capacitance of the structure is small, which makes it appealing
for many circuit applications. In addition, unlike conventional metal-to-metal capacitors, the density of
a fractal capacitor increases with scaling.

Lateral Flux Capacitors

Figure 2.1(a) shows a lateral flux capacitor. In this capacitor, the two terminals of the device are built
using a single layer of metal, unlike a vertical flux capacitor, where two different metal layers must be
used. As process technologies continue to scale, lateral fringing becomes more important. The lateral
spacing of the metal layers, s, shrinks with scaling, yet the thickness of the metal layers, t, and the vertical
spacing of the metal layers, tox, stay relatively constant. This means that structures utilizing lateral flux
enjoy a significant improvement with process scaling, unlike conventional structures that depend on
vertical flux. Figure 2.1(b) shows a scaled lateral flux capacitor. It is obvious that the capacitance of the
structure of Fig. 2.1(b) is larger than that of Fig. 2.1(a).
Lateral flux can be used to increase the total capacitance obtained in a given area. Figure 2.2(a) is a
standard parallel-plate capacitor. In Fig. 2.2(b), the plates are broken into cross-connected sections.2 As
can be seen, a higher capacitance density can be achieved by using lateral flux as well as vertical flux. To
emphasize that the metal layers are cross connected, the two terminals of the capacitors in Fig. 2.2(b)
are identified with two different shadings. The idea can be extended to multiple metal layers as well.
Figure 2.3 shows the ratio of metal thickness to minimum lateral spacing, t/s, vs. channel length for
various technologies.3–5 The trend suggests that lateral flux will have a crucial role in the design of
capacitors in future technologies.

FIGURE 2.1 Effect of scaling on lateral flux capacitors: (a) before scaling and (b) after scaling.

© 2003 by CRC Press LLC

RF Passive IC Components 2-3

FIGURE 2.2 Vertical flux vs. lateral flux: (a) standard parallel-plate structure, and (b) cross-connected metal layers.

Trend
Data points

FIGURE 2.3 Ratio of metal thickness to horizontal metal spacing vs. technology (channel length).

The increase in capacitance due to fringing is proportional to the periphery of the structure; therefore,
structures with large periphery per unit area are desirable. Methods for increasing this periphery are the
subject of the following sections.

Fractals
A fractal is a mathematical abstract.6 Some fractals are visualizations of mathematical formulas, while others
are the result of the repeated application of an algorithm, or a rule, to a seed. Many natural phenomena can
be described by fractals. Examples include the shapes of mountain ranges, clouds, coastlines, etc.
Some ideal fractals have finite area but infinite perimeter. The concept can be better understood with
the help of an example. Koch islands are a family of fractals first introduced as a crude model for the
shape of a coastline. The construction of a Koch curve begins with an initiator, as shown in the example
of Fig. 2.4(a). A square is a simple initiator with M = 4 sides. The construction continues by replacing
each segment of the initiator with a curve called a generator, an example of which is shown in Fig. 2.4(b)
that has N = 8 segments. The size of each segment of the generator is r = 1 § 4 of the initiator. By
recursively replacing each segment of the resulting curve with the generator, a fractal border is formed.
The first step of this process is depicted in Fig. 2.4(c). The total area occupied remains constant throughout
the succession of stages because of the particular shape of the generator. A more complicated Koch island
can be seen in Fig. 2.5. The associated initiator of this fractal has four sides and its generator has 32
segments. It can be noted that the curve is self similar, that is, each section of it looks like the entire
fractal. As we zoom in on Fig. 2.5, more detail becomes visible, and this is the essence of a fractal.

© 2003 by CRC Press LLC

2-4 Analog Circuits and Devices

FIGURE 2.4 Construction of a Koch curve: (a) an initiator, (b) a generator, and (c) first step of the process.

FIGURE 2.5 A Koch island with M = 4, N = 32, and r = 1/8.

Fractal dimension, D, is a mathematical concept that is a measure of the complexity of a fractal. The
dimension of a flat curve is a number between 1 and 2, which is given by

log ( N )
D = ----------------- (2.1)
1
log Ê ---ˆ
Ë r¯

where N is the number of segments of the generator and r is the ratio of the generator segment size to
the initiator segment size. The dimension of a fractal curve is not restricted to integer values, hence the
term “fractal.” In particular, it exceeds 1, which is the intuitive dimension of curves. A curve that has a
high degree of complexity, or D, fills out a two-dimensional flat surface more efficiently. The fractal in
Fig. 2.4(c) has a dimension of 1.5, whereas for the border line of Fig.2.5, D = 1.667 .
For the general case where the initiator has M sides, the periphery of the initiator is proportional to
the square root of the area:

P0 = k ◊ A (2.2)

where k is a proportionality constant that depends on the geometry of the initiator. For example, for a
square initiator, k = 4; and for an equilateral triangle, k = 2 ◊ 4 27 . After n successive applications of
the generation rule, the total periphery is

© 2003 by CRC Press LLC

RF Passive IC Components 2-5

n
P = k A ◊ ( Nr ) (2.3)

and the minimum feature size (the resolution) is

k A n
l = ----------- ◊ r (2.4)
M
Eliminating n from Eqs. 2.3 and 2.4 and combining the result with Eq. 2.1, we have

D D
k - (------------
A)
P = ------------
D–1
◊ D–1 (2.5)
M l

Equation 2.5 demonstrates the dependence of the periphery on parameters such as the area and the
resolution of the fractal border. It can be seen from Eq. 2.5 that as l tends toward zero, the periphery
goes to infinity; therefore, it is possible to generate fractal structures with very large perimeters in any
given area. However, the total periphery of a fractal curve is limited by the attainable resolution in practical
realizations.

Fractal Capacitor Structures

The final shape of a fractal can be tailored to almost any form. The flexibility arises from the fact that a
wide variety of geometries can be used as the initiator and generator. It is also possible to use different
generators during each step. This is an advantage for integrated circuits where flexibility in the shape of
the layout is desired.
Figure 2.6 is a three-dimensional representation of a fractal capacitor. This capacitor uses only one
metal layer with a fractal border. For a better visualization of the overall picture, the terminals of this
square-shaped capacitor have been identified using two different shadings. As was discussed before,
multiple cross-connected metal layers may be used to improve capacitance density further.
One advantage of using lateral flux capacitors in general, and fractal capacitors in particular, is the
reduction of the bottom-plate capacitance. This reduction is due to two reasons. First, the higher density
of the fractal capacitor (compared to a standard parallel-plate structure) results in a smaller area. Second,
some of the field lines originating from one of the bottom plates terminate on the adjacent plate, instead
of the substrate, which further reduces the bottom-plate capacitance as shown in Fig. 2.7. Because of this

FIGURE 2.6 3-D representation of a fractal capacitor using a single metal layer.

© 2003 by CRC Press LLC

2-6 Analog Circuits and Devices

property, some portion of the parasitic bottom-plate capacitor is converted into the more useful plate-
to-plate capacitance.
The capacitance per unit area of a fractal structure depends on the dimension of the fractal. To improve
the density of the layout, fractals with large dimensions should be used. The concept of fractal dimension
is demonstrated in Fig. 2.8. The structure in Fig. 2.8(a) has a lower dimension compared to the one in
Fig. 2.8(b), so the density (capacitance per unit area) of the latter is higher.
To demonstrate the dependence of capacitance density on dimension and lateral spacing of the metal
layers, a first-order electromagnetic simulation was performed on two families of fractal structures. In
Fig. 2.9, the boost factor is plotted vs. horizontal spacing of the metal layers. The boost factor is defined
as the ratio of the total capacitance of the fractal structure to the capacitance of a standard parallel-plate
structure with the same area. The solid line corresponds to a family of fractals with a moderate fractal

FIGURE 2.7 Reduction of the bottom-plate parasitic capacitance.

FIGURE 2.8 Fractal dimension of (a) is smaller than (b).

© 2003 by CRC Press LLC

RF Passive IC Components 2-7

FIGURE 2.9 Boost factor vs. lateral spacing.

dimension of 1.63, while the dashed line represents another family of fractals with D = 1.80 , which is
a relatively large value for the dimension. In this first-order simulation, it is assumed that the vertical
spacing and the thickness of the metal layers are kept constant at a 0.8-mm level. As can be seen in Fig.
2.9, the amount of boost is a strong function of the fractal dimension as well as scaling.
In addition to the capacitance density, the quality factor, Q, is important in RF applications. Here, the
degradation in quality factor is minimal because the fractal structure automatically limits the length of
the thin metal sections to a few microns, keeping the series resistance reasonably small. For applications
that require low series resistance, lower dimension fractals may be used. Fractals thus add one more
degree of freedom to the design of capacitors, allowing the capacitance density to be traded for a lower
series resistance.
In current IC technologies, there is usually tighter control over the lateral spacing of metal layers
compared to the vertical thickness of the oxide layers, from wafer to wafer and across the same wafer.
Lateral flux capacitors shift the burden of matching away from oxide thickness to lithography. Therefore,
by using lateral flux, matching characteristics can improve. Furthermore, the pseudo-random nature of
the structure can also compensate, to some extent, the effects of non-uniformity of the etching process.
To achieve accurate ratio matching, multiple copies of a unit cell should be used, as is standard practice
in high-precision analog circuit design.
Another simple way of increasing capacitance density is to use an interdigitated capacitor depicted in
Fig. 2.10.2,7 One disadvantage of such a structure compared to fractals is its inherent parasitic inductance.
Most of the fractal geometries randomize the direction of the current flow and thus reduce the effective
series inductance; whereas for interdigitated capacitors, the current flow is in the same direction for all
the parallel stubs. In addition, fractals usually have lots of rough edges that accumulate electrostatic
energy more efficiently compared to interdigitated capacitors, causing a boost in capacitance (generally
of the order of 15%). Furthermore, interdigitated structures are more vulnerable to non-uniformity of
the etching process. However, the relative simplicity of the interdigitated capacitor does make it useful
in some applications.
The woven structure shown in Fig. 2.11 may also be used to achieve high capacitance density. The
vertical lines are in metal-2 and horizontal lines are in metal-1. The two terminals of the capacitor
are identified using different shades. Compared to an interdigitated capacitor, a woven structure has
much less inherent series inductance. The current flowing in different directions results in a higher
self-resonant frequency. In addition, the series resistance contributed by vias is smaller than that of
an interdigitated capacitor, because cross-connecting the metal layers can be done with greater ease.
However, the capacitance density of a woven structure is smaller compared to an interdigitated
capacitor with the same metal pitch, because the capacitance contributed by the vertical fields is
smaller.

© 2003 by CRC Press LLC

2-8 Analog Circuits and Devices

FIGURE 2.10 An interdigitated capacitor.

FIGURE 2.11 A woven structure.

2.3 Spiral Inductors

More than is so with capacitors, on-chip inductor options are particularly limited and unsatisfactory.
Nevertheless, it is possible to build practical spiral inductors with values up to perhaps 20 nH and with
Q values of approximately 10. For silicon-based RF ICs, Q degrades at high frequencies due to energy
dissipation in the semiconducting substrate.8 Additionally, noise coupling via the substrate at GHz
frequencies has been reported.9 As inductors occupy substantial chip area, they can potentially be the
source and receptor of detrimental noise coupling. Furthermore, the physical phenomena underlying the
substrate effects are complicated to characterize. Therefore, decoupling the inductor from the substrate
can enhance the overall performance by increasing Q, improving isolation, and simplifying modeling.
Some approaches have been proposed to address the substrate issues; however, they are accompanied
by drawbacks. Some10 have suggested the use of high-resistivity (150 to 200 W-cm) silicon substrates to
mimic the low-loss semi-insulating GaAs substrate, but this is rarely a practical option. Another approach
selectively removes the substrate by etching a pit under the inductor.11 However, the etch adds extra
processing cost and is not readily available. Moreover, it raises reliability concerns such as packaging yield
and long-term mechanical stability. For low-cost integration of inductors, the solution to substrate
problems should avoid increasing process complexity.
In this section, we present the patterned ground shield (PGS),23 which is compatible with standard
silicon technologies, and which reduces the unwanted substrate effects. The great improvement pro-
vided by the PGS reduces the disparity in quality between spiral inductors made in silicon and GaAs IC
technologies.

Understanding Substrate Effects

To understand why the PGS should be effective, consider first the physical model of an ordinary inductor
on silicon, with one port and the substrate grounded, as shown in Fig. 2.12.8 An on-chip inductor is

© 2003 by CRC Press LLC

RF Passive IC Components 2-9

FIGURE 2.12 Lumped physical model of a spiral inductor on silicon.

physically a three-port element including the substrate. The one-port connection shown in Fig. 2.12
avoids unnecessary complexity in the following discussion and at the same time preserves the inductor
characteristics. In the model, the series branch consists of Ls, Rs, and Cs. Ls represents the spiral inductance,
which can be computed using the Greenhouse method12 or well-approximated by simple analytical
formulas to be presented later. Rs is the metal series resistance whose behavior at RF is governed by the
eddy current effect. This resistance accounts for the energy loss due to the skin effect in the spiral
interconnect structure as well as the induced eddy current in any conductive media close to the inductor.
The series feedforward capacitance, Cs, accounts for the capacitance due to the overlaps between the
spiral and the center-tap underpass.13 The effect of the inter-turn fringing capacitance is usually small
because the adjacent turns are almost at equal potentials, and therefore it is neglected in this model. The
overlap capacitance is more significant because of the relatively large potential difference between the
spiral and the center-tap underpass. The parasitics in the shunt branch are modeled by Cox, CSi, and RSi.
Cox represents the oxide capacitance between the spiral and the substrate. The silicon substrate capacitance
and resistance are modeled by CSi and RSi, respectively.14,15 The element RSi accounts for the energy
dissipation in the silicon substrate.
Expressions for the model element values are as follows:

rl
R s = ---------------------------
t
- (2.6)
– --
dw Ê 1 – e ˆ
d
Ë ¯

2 e ox
C s = nw ◊ ------------------- (2.7)
t oxM1 – M2

e ox
C ox = -------- ◊l◊w (2.8)
2t ox

1
C Si = --- ◊ l ◊ w ◊ C sub (2.9)
2

2
R Si = ------------------------ (2.10)
l ◊ w ◊ G sub

where r is the DC resistivity of the spiral; t is the overall length of the spiral windings; w is the line width;
d is the skin depth; n is the number of crossovers between the spiral and center-tap (and thus n = N – 1,
where N is the number of turns); toxM1–M2 is the oxide thickness between the spiral and substrate; Csub is

© 2003 by CRC Press LLC

2-10 Analog Circuits and Devices

the substrate capacitance per unit area; and Gsub is the substrate conductance per unit area. In general,
one treats Csub and Gsub as fitting parameters.
Exploration with the model reveals that the substrate loss stems primarily from the penetration of the
electric field into the lossy silicon substrate. As the potential drop in the semiconductor (i.e., across RSi
in Fig. 2.12) increases with frequency, the energy dissipation in the substrate becomes more severe. It
can be seen that increasing Rp to infinity reduces the substrate loss. It can be shown that Rp approaches
infinity as RSi goes either to zero or infinity. This observation implies that Q can be improved by making
the silicon substrate either a perfect insulator or a perfect conductor. Using high-resistivity silicon (or
etching it away) is equivalent to making the substrate an open circuit. In the absence of the freedom to
do so, the next best option is to convert the substrate into a better conductor. The approach is to insert
a ground plane to block the inductor electric field from entering the silicon. In effect, this ground plane
becomes a pseudo-substrate with the desired characteristics.
The ground shield cannot be a solid conductor, however, because image currents would be induced
in it. These image currents tend to cancel the magnetic field of the inductor proper, decreasing the
inductance. To solve this problem, the ground shield is patterned with slots orthogonal to the spiral as
illustrated in Fig. 2.13. The slots act as an open circuit to cut off the path of the induced loop current.
The slots should be sufficiently narrow such that the vertical electric field cannot leak through the
patterned ground shield into the underlying silicon substrate. With the slots etched away, the ground
strips serve as the termination for the electric field. The ground strips are merged together around the
four outer edges of the spiral. The separation between the merged area and the edges is not critical.
However, it is crucial that the merged area not form a closed ring around the spiral since it can potentially
support unwanted loop current. The shield should be strapped with the top layer metal to provide a low-
impedance path to ground. The general rule is to prevent negative mutual coupling while minimizing
the impedance to ground.
The shield resistance is another critical design parameter. The purpose of the patterned ground shield
is to provide a good short to ground for the electric field. Since the finite shield resistance contributes
to energy loss of the inductor, it must be kept small. Specifically, by keeping the shield resistance small
compared to the reactance of the oxide capacitance, the voltage drop that can develop across the shield
resistance is very small. As a result, the energy loss due to the shield resistance is insignificant compared

FIGURE 2.13 A close-up photo of the patterned ground shield.

© 2003 by CRC Press LLC

RF Passive IC Components 2-11

to other losses. A typical on-chip spiral inductor has parasitic oxide capacitance between 0.25 and 1 pF,
depending on the size and the oxide thickness. The corresponding reactance due to the oxide capacitance
at 1 to 2 GHz is of the order of 100 W, and hence a shield resistance of a few ohms is sufficiently small
not to cause any noticeable loss.
With the PGS, one can expect typical improvements in Q ranging from 10 to 33%, in the frequency
range of 1 to 2 GHz. Note that the inclusion of the ground shields increases Cp , which causes a fast roll-
off in Q above the peak-Q frequency and a reduction in the self-resonant frequency. This modest
improvement in inductor Q is certainly welcome, but is hardly spectacular by itself. However, a more
dramatic improvement is evident when evaluating inductor-capacitor resonant circuits. Such LC tank
circuits can absorb the parasitic capacitance of the ground shield. Since the energy stored in such parasitic
elements is now part of the circuit, the overall circuit Q is greatly increased. Improvements of factors of
approximately two are not unusual, so that tank circuits realized with PGS inductors possess roughly the
same Q as those built in GaAs technologies.
As stated earlier, substrate noise coupling can be an issue of great concern owing to the relatively large
size of typical inductors. Shielding by the PGS improves isolation by 25 dB or more at GHz frequencies.
It should be noted that, as with any other isolation structure (such as a guard ring), the efficacy of the
PGS is highly dependent on the integrity of the ground connection. One must often make a tradeoff
between the desired isolation level and the chip area that is required to provide a low-impedance ground
connection.

Simple, Accurate Expressions for Planar Spiral Inductances

In the previous section, a physically based model for planar spiral inductors was offered, and reference
was made to the Greenhouse method as a means for computing the inductance value. This method uses
as computational atoms the self- and mutual inductances of parallel current strips. It is relatively straight-
forward to apply, and yields accurate results. Nevertheless, simpler analytic formulas are generally pre-
ferred for design since important insights are usually more readily obtained.
As a specific example, square spirals are popular mainly because of their ease of layout. Other polygonal
spirals have also been used to improve performance by more closely approximating a circular spiral.
However, a quantitative evaluation of possible improvements is cumbersome without analytical formulas
for inductance.
Among alternative shapes, hexagonal and octagonal inductors are used widely. Figures 2.14 through
2.16 show the layout for square, hexagonal, and octagonal inductors, respectively. For a given shape, an
inductor is completely specified by the number of turns n, the turn width w, the turn spacing s, and any
one of the following: the outer diameter dout, the inner diameter din, the average diameter davg = 0.5(dout
+ din), or the fill ratio, defined as r = (dout – din)/(dout + din). The thickness of the inductor has only a
very small effect on inductance and will therefore be ignored here.
We now present three approximate expressions for the inductance of square, hexagonal, and octagonal
planar inductors. The first approximation is based on a modification of an expression developed by
Wheeler16; the second is derived from electromagnetic principles by approximating the sides of the spirals
as current sheets; and the third is a monomial expression derived from fitting to a large database of
inductors (whose exact inductance values are obtained from a 3-D electromagnetic field solver). All three
expressions are accurate, with typical errors of 2 to 3%, and very simple, and are therefore excellent
candidates for use in design and optimization.

Modified Wheeler Formula

Wheeler16 presented several formulas for planar spiral inductors, which were intended for discrete induc-
tors. A simple modification of the original Wheeler formula allows us to obtain an expression that is
valid for planar spiral integrated inductors:

© 2003 by CRC Press LLC

2-12 Analog Circuits and Devices

din

dout

FIGURE 2.14 Square inductor.

w
s

din

dout

FIGURE 2.15 Hexagonal inductor.

2
n d avg
L mw = K 1 m 0 ------------------ (2.11)
1 + K2 r

where r is the fill ratio defined previously. The coefficients K1 and K2 are layout dependent and are shown
in Table 2.1.
The fill factor r represents how hollow the inductor is: for small r, we have a hollow inductor (dout @
din), and for a large r we have a filled inductor (dout >> din). Two inductors with the same average diameter
but different fill ratios will, of course, have different inductance values; the filled one has a smaller
inductance because its inner turns are closer to the center of the spiral, and so contribute less positive

© 2003 by CRC Press LLC

RF Passive IC Components 2-13

w
s

din

dout

FIGURE 2.16 Octagonal inductor.

TABLE 2.1 Coefficients for Modified Wheeler Formula

Layout K1 K2

Square 2.34 2.75

Hexagonal 2.33 3.82
Octagonal 2.25 3.55

mutual inductance and more negative mutual inductance. Some degree of hollowness is generally desired
since the innermost turns contribute little overall inductance, but significant resistance.
Expression Based on Current Sheet Approximation
Another simple and accurate expression for the inductance of a planar spiral can be obtained by approx-
imating the sides of the spirals by symmetrical current sheets of equivalent current densities.17 For
example, in the case of the square, we obtain four identical current sheets: the current sheets on opposite
sides are parallel to one another, whereas the adjacent ones are orthogonal. Using symmetry and the fact
that sheets with orthogonal current sheets have zero mutual inductance, the computation of the induc-
tance is now reduced to evaluating the self-inductance of one sheet and the mutual inductance between
opposite current sheets. These self- and mutual inductances are evaluated using the concepts of geometric
mean distance (GMD) and arithmetic mean distance (AMD).17,18 The resulting expression is:

2
mn d avg
L gmd = ----------------- ( c 1 ( log c 2 § r ) + c 3 r ) (2.12)
p

where the coefficients ci are layout dependent and are shown in Table 2.2.

© 2003 by CRC Press LLC

2-14 Analog Circuits and Devices

TABLE 2.2 Coefficients for Current-Sheet Inductance Formula

Layout c1 c2 c3

Square 2.00 2.00 0.54

Hexagonal 1.83 1.71 0.45
Octagonal 1.87 1.68 0.60

A detailed derivation of these formulas can be found in Ref. 19. Since this formula is based on a current
sheet approximation, its accuracy worsens as the ratio s/w becomes large. In practice, this is not a problem
since practical integrated spiral inductors are built with s < w. The reason is that a smaller spacing
improves the inter-winding magnetic coupling and reduces the area consumed by the spiral. A large
spacing is only desired to reduce the inter-winding capacitance. This is rarely a concern as this capacitance
is always dwarfed by the under-pass capacitance.8
Data-Fitted Monomial Expression
Our final expression is based on a data-fitting technique, in which a population of thousands of inductors
are simulated with an electromagnetic field solver. The inductors span the entire range of values of
relevance to RF circuits. A monomial expression is then fitted to the data, which ultimately yields:

a2
a1 w d a3 n s a4 a5
L mon = bd avg avg (2.13)

where the coefficients b and ai are layout dependent, and given in Table 2.3.
Of course, it is also possible to use other data-fitting techniques; for example, one which minimizes
the maximum error of the fit, or one in which the coefficients must satisfy given inequalities or bounds.
The monomial expression is useful since, like the other expressions, it is very accurate and very simple.
Its real value, however, is that it can be used for the optimal design of inductors and circuits containing
inductors, using geometric programming, which is a type of optimization method that requires monomial
models.20,21
Figure 2.17 shows the absolute error distributions of these expressions. The plots show that typical
errors are in the 1 to 2% range, and most of the errors are below 3%. These expressions for inductance,
while quite simple, are thus sufficiently accurate that field solvers are rarely necessary.
These expressions can be included in a physical, scalable lumped-circuit model for spiral inductors
where, in addition to providing design insight, they allow efficient optimization schemes to be employed.

2.4 On-Chip Transformers

Transformers are important elements in RF circuits for impedance conversion, impedance matching, and
bandwidth enhancement. Here, we present an analytical model for monolithic transformers that is
suitable for circuit simulation and design optimization. We also provide simple expressions for calculating
the mutual coupling coefficient (k).
We first discuss different on-chip transformers and their advantages and disadvantages. We then
present an analytical model along with expressions for the elements in it and the mutual coupling
coefficient.

TABLE 2.3 Coefficients for Monomial Inductance Formula

Layout b a1 a2 a3 a4 a5

Square 1.66 ¥ 10-3 -1.33 -0.13 2.50 1.83 -0.022

Hexagonal 1.33 ¥ 10-3 -1.46 -0.16 2.67 1.80 -0.030
Octagonal 1.34 ¥ 10-3 -1.35 -0.15 2.56 1.77 -0.032

© 2003 by CRC Press LLC

RF Passive IC Components 2-15

FIGURE 2.17 Error distribution for three formulas, compared to field solver simulations.

Monolithic Transformer Realizations

Figures 2.18 through 2.23 illustrate common configurations of monolithic transformers. The different
realizations offer varying tradeoffs among the self-inductance and series resistance of each port, the
mutual coupling coefficient, the port-to-port and port-to-substrate capacitances, resonant frequencies,
symmetry, and area. The models and coupling expressions allow these tradeoffs to be systematically
explored, thereby permitting transformers to be customized for a variety of circuit design requirements.
The characteristics desired of a transformer are application dependent. Transformers can be configured
as three- or four-terminal devices. They may be used for narrowband or broadband applications. For
example, in single-sided to differential conversion, the transformer might be used as a four-terminal
narrowband device. In this case, a high mutual coupling coefficient and high self-inductance are desired,
along with low series resistance. On the other hand, for bandwidth extension applications, the transformer
is used as a broadband three-terminal device. In this case, a small mutual coupling coefficient and high
series resistance are acceptable, while all capacitances need to be minimized.22
The tapped transformer (Fig. 2.18) is best suited for three-port applications. It permits a variety of
tapping ratios to be realized. This transformer relies only on lateral magnetic coupling. All windings can
be implemented with the top metal layer, thereby minimizing port-to-substrate capacitances. Since the
two inductors occupy separate regions, the self-inductance is maximized while the port-to-port capaci-
tance is minimized. Unfortunately, this spatial separation also leads to low mutual coupling (k = 0.3–0.5).
The interleaved transformer (Fig. 2.19) is best suited for four-port applications that demand symmetry.
Once again, capacitances can be minimized by implementing the spirals with top level metal so that high
resonant frequencies may be realized. The interleaving of the two inductances permit moderate coupling
(k = 0.7) to be achieved at the cost of reduced self-inductance. This coupling may be increased at the
cost of higher series resistance by reducing the turn width (w) and spacing (s).
The stacked transformer (Fig. 2.20) uses multiple metal layers and exploits both vertical and lateral
magnetic coupling to provide the best area efficiency, the highest self-inductance, and highest coupling
(k = 0.9). This configuration is suitable for both three- and four-terminal configurations. The main
drawback is the high port-to-port capacitance, or equivalently a low self-resonant frequency. In some
cases, such as narrowband impedance transformers, this capacitance may be incorporated as part of the
resonant circuit. Also, in multi-level processes, the capacitance can be reduced by increasing the oxide
thickness between spirals. For example, in a five-metal process, 50 to 70% reductions in port-to-port
capacitance can be achieved by implementing the spirals on layers five and three instead of five and four.

© 2003 by CRC Press LLC

2-16 Analog Circuits and Devices

FIGURE 2.18 Tapped transformer.

FIGURE 2.19 Interleaved transformer.

The increased vertical separation will reduce k by less than 5%. One can also trade off reduced coupling
for reduced capacitance by displacing the centers of the stacked inductors (Figs. 2.21 and 2.22).

Analytical Transformer Models

Figures 2.23 and 2.24 present the circuit models for tapped and stacked transformers, respectively. The
corresponding element values for the tapped transformer model are given by the following equations
(subscript o refers to the outer spiral, i to the inner spiral, and T to the whole spiral):

2 2
9.375m 0 n T AD T
L T = ------------------------------------- (2.14)
11OD T – 7AD T

© 2003 by CRC Press LLC

Exploring the Variety of Random
Documents with Different Content
standing in mathematics he was alarmed. He had made only 1.1 on
the examination, and was unsatisfactory, having but 2.38 for the
month.
“I’ll bilge sure,” said Ralph to Creelton, “unless I take a brace.” And
he did study hard.
The month of January was spent in reviewing the work already gone
over, and here Ralph’s good work in previous studying rules and
formulas helped him considerably and he did fairly well in his
recitations. At odd times he endeavored to prove in his own way the
problem in geometry at which he had so signally failed in the
December examination, and by the end of January, when the much
dreaded semi-annual examinations were to begin, Ralph felt he was
well prepared. After this examination the midshipmen who fail to
make 2.50 for the term’s average are required to resign, and
between twenty and thirty fourth classmen are generally found to be
unsatisfactory each year.
“I’m on the Christmas tree,”[5] exclaimed Ralph to his roommate
before the examination commenced. “I’ve only got 2.57 to go into
the examination. Now let’s see. The examination mark has one-
fourth weight. Three times 2.57 is 7.71. This subtracted from 10.00
leaves 2.29. And that’s what I’ve got to make on the exam; I ought
to do that.”
“Of course you ought to, Os, and I’m sure you will,” replied Creelton.
“You are all right in French and rhetoric, aren’t you?”
“I think so, and I have so thoroughly reviewed the math and worked
out so many problems this month that I expect to make much more
than a 2.50 on the exam.”
On the examination Ralph worked rapidly and he had a happy
feeling he was doing everything right. Two hours were spent on
algebra and two on geometry. After the examination he was
confident he had made more than the requisite 2.29, but he was
feverishly hungry for a sight of the marks.
On a Friday Bollup came into his room and said: “Let’s go down to
the bulletin-board, Os; the math marks ought to be posted by this
time.”
“All right,” said Ralph, and they went down together. A crowd of
midshipmen were eagerly looking at the bulletin-board. On the
board was posted a large sheet with the names of midshipmen in
two columns, they being graduated according to their excellence.
Ralph and Bollup crowded in.
“You’re number two, Bollup,” called some one in the crowd; “Himski
is number one.”
Ralph looked up and down the right-hand column, containing the
names of the lower half of the class, looking for his own name, as
had been his wont. He could not find his name. He glanced up and
down again and failed to see “Osborn” anywhere in the column.
Then he became worried; he could not imagine why his name should
not be there. That it was possibly over in the first column, in the
upper half of the class, never occurred to him.
“Good gracious, Os,” suddenly called out Bollup, “but you did
everlastingly thump that geometry exam, didn’t you?”
“I can’t find my name,” cried Ralph excitedly; “where is it?”
“Number 35, Os, left-hand column. You made 3.82 on your
geometry and 3.26 on your algebra; your average for the
examination is 3.54, and for the term 2.81.”
Ralph gave a wild “hurrah,” and feasted his eyes over these marks.
Never before had anything ever looked so beautiful to him. Now he
felt all his worries were over.
Two days later he was called to the office of the officer in charge.
“Osborn, sir,” he reported, saluting.
“Report to the superintendent’s office immediately, Mr. Osborn,”
directed Lieutenant Wilson.
“Very well, sir,” replied Ralph in great surprise, wondering what in
the world the superintendent could want with him. He was soon
admitted to the superintendent’s presence.
“Good-morning, Mr. Osborn,” said the latter, fixing his penetrating
gray eyes upon Ralph.
“Good-morning, sir. I was directed to report to you, sir.”
“Yes. I want you to read a letter I have just received.”
He picked up a paper from his desk and handed it to Ralph. It was
as follows:
“To the superintendent of the Naval Academy:
“I desire to call your attention to the fact that Midshipman
Osborn of the fourth class made but 1.1 on his December
examination in mathematics, and is credited with having
made 3.54 on the semi-annual examination in the same
subject. The two marks are incompatible. The explanation
is that Midshipman Osborn had an algebra inside his coat,
left-hand side, and a geometry on his right-hand side;
during the examination I saw him use them. Osborn stole
Bollup’s watch. This matter seems to have been hushed
up. It is an outrage to his classmates and to all
midshipmen that such a character should be retained at
the Naval Academy.
“Indignant Fourth Classman.”
 CHAPTER X
“The Osborn Demonstration”

R alph read the letter, which was written in printed characters,

through slowly a second time. Then he looked up at the
superintendent with a troubled expression on his face.
“You needn’t say anything about the letter, Mr. Osborn,” the
superintendent remarked in a kindly tone. “It contains nothing but
lies and the writer is a contemptible coward. But have you any idea
as to who the writer may be?”
“Not the slightest, sir,” replied Ralph, much relieved at the
superintendent’s words. “Had you heard about Mr. Bollup’s watch
being stolen and of how it was found on my watch-chain, sir?”
“Oh, yes, I have the letters you four young gentlemen wrote before
me now. Do you think this letter was written by a midshipman or
somebody else?”
“I have no idea, sir; I can’t imagine any midshipman would wish to
hurt me. I have never had any trouble that amounted to anything
with anybody here, except Mr. Short; you know about that, sir.”
“Yes, and Mr. Short is a long ways off. I’ll keep this letter carefully
and perhaps something may turn up——”
“Sir, may I offer a suggestion?”
“Certainly, Mr. Osborn; what is it?”
“I would request that that letter be published to the battalion with
your order that the writer of it, if a midshipman, should report to
you.”
The superintendent thought a moment and then said: “I won’t
publish the letter, that could do no good, but I will have an order
read requiring the writer of a letter to me signed ‘Indignant Fourth
Classman’ to report to me. Now, Mr. Osborn, whenever a charge of
any kind is made against any person in the Navy it is always
investigated. So I have directed Professor Scott to go over your
papers himself, and then to come here with them. I expect him here
in a few moments—here he is now. Good-morning, professor.”
“Good-morning, admiral. I have been over Mr. Osborn’s papers, and
——”
“One minute, professor; just read this letter and you will know why I
had you go over Mr. Osborn’s semi-annual examination papers in
mathematics.”
The professor read the letter, and then indignantly threw it down on
the desk. “That’s contemptible, sir; in his work Mr. Osborn has
shown thorough comprehension. In his algebra questions Mr. Osborn
stumbled somewhat on a few of the problems but in every case
displayed a good knowledge of the principles involved. A number of
answers he obtained by original methods; this has pleased me very
much. In spite of his low marks last month—I looked into that—he
has shown a real knowledge, and has not made his good marks by
means merely of a good memory. But his geometry paper is
magnificent, admiral,” continued Professor Scott, enthusiastically.
“Had I been the one to have first marked his paper I would have
called attention to a beautiful piece of original work. In the
December examination he stumbled over the problem in geometry of
proving the square of the hypotenuse of a right-angled triangle is
equal to the sum of the squares of the other two sides. He clean
forgot how to do it; the same problem was given in the semi-annual,
and Mr. Osborn proved it in his own way by a method I have never
before seen or heard of. I have examined every book we have in the
department and can find no mention of this method. I talked with
every one of my assistants and all were delighted with Mr. Osborn’s
method. I suppose the method must be known; it’s not possible that
Mr. Osborn could be the original discoverer of it, but I’ve never seen
the method before nor can I find any one who has; admiral, here it
is——” and Professor Scott took one of the sheets of Ralph’s paper
on which was written the following:
Question:
Prove the square of the
hypotenuse of a right-angled
triangle, is equal to the sum of
the squares of the other two
sides.
Demonstration:
Let ABC be a right-angled
triangle.
To prove (AB)2 = (AC)2 + (BC)2.
On AB erect the square ABED.
Draw BM parallel and equal to
AC. From A erect a
perpendicular through M.
By inspection triangle AMB = triangle ABC.
From point E drop a perpendicular to the line BM. The triangle thus
formed, ENB, having a side and angles equal to a side and angles of
triangle AMB, is seen by inspection to be equal to triangle AMB, and
therefore to triangle ABC. Hence BN is equal to BC.
In a similar way construct the triangles ADH and DKE. By inspection
each of these is seen to be equal to triangle ABC.
The square erected on AB is thus equal to four times the triangle
ABC plus the rectangle HMNK.
Rectangle HMNK = MN × MH.
MN = BM - BN = AC - BC.
MH = AH - AM = AC - BC.
Four times area of triangle ABC = 4 × (1/2) AC × BC.
Hence (AB)2 = 4 × (1/2) AC × BC + (AC - BC) (AC - BC) = 2 AC ×
BC + (AC)2 - 2 AC × BC + (BC)2. Or, (AB)2 = (AC)2 + (BC)2. Q. E. D.
“Now, admiral,” continued the delighted professor, “I’m going to
send Mr. Osborn’s demonstration to some of the colleges and
mathematical societies. Although it is original with Mr. Osborn, at
least I imagine that it is, I really cannot believe that it is possible
that he is the first discoverer of this method. If it should prove that
Mr. Osborn is the original person who has ever used this method it
will go down in the books as ‘The Osborn Demonstration.’”
“How did you happen to fall on that method, Mr. Osborn?” asked the
admiral.
“Why, sir, I failed miserably on this question in the December
examination and afterward I was determined to get it without
referring to the book. One time when I was working at it, wondering
why I couldn’t do it, I happened to erect the square on the
hypotenuse and somehow drew in the triangles. Then when I looked
at the figure I started to add up the areas of the different triangles
and the square in the center and it all worked out naturally.”
“It’s an algebraic rather than a geometrical proof, or rather a
combination of both,” remarked Professor Scott, “and Mr. Osborn
deserves much credit. And as for the statement that Mr. Osborn
cheated by carrying books in the examination with him, why that is
as ridiculous as it is false and contemptible.”
“That is just my notion,” assented the superintendent. “Now, Mr.
Osborn, don’t worry about this letter and don’t talk with anybody
about it. There is undoubtedly somebody determined to do you
terrible injury, but I think we can take care of you. Keep your eyes
wide open, say nothing, not even to your closest friend, and if you
learn anything whatever come to me immediately.”
Ralph left the superintendent’s office in a very happy and
comfortable state of mind. He was indeed perplexed at the
persistent hidden enmity that had been displayed against him, and
for which he could imagine no cause, but he felt that he had a
powerful friend who would protect him.
The next month, February, Ralph was in the fourth section in
mathematics. The regular instructor assigned to this section was sick
so that the head of the department, Professor Scott, took the
section. He displayed much interest in Ralph’s work; this was
apparent to all, and inspired by this Ralph devoted himself to
preparing his recitations with a zest he had never felt before. He
worked enough on his rhetoric and French to get satisfactory marks
in these subjects, but in most of his study hours and much of his
leisure after drill and on Saturdays and Sundays he devoted himself
to his algebra. Before going to recitations he had always studied the
principles carefully and worked out most, if not all of the problems.
At the end of February the monthly examinations were held.
“How did you do, Os?” asked Creelton, after they had returned to
their rooms.
“I feel I hammered it hard. How did you do, Creel?”
“Oh, I biffed it. I’ve good recitation marks and hope to stand number
one this month. I’d like to cook Himski and Bollup this month.”
“I hope you did well,” said Ralph heartily. “I suppose you fellows in
the first section will all stay there, but I hope I may pull up into the
second.”
“That would be a good rise for you, Os; I hope you will. You’ve been
working hard at math this month and will probably land in the third
section if you don’t make the second.”
While Ralph, Creelton, Bollup and Streeter were returning together
from drill a few days later, Bollup said: “Hello, there’s a crowd at our
bulletin-board; I guess our math marks are posted.”
They all ran up to the board, Bollup leading. As soon as he had
looked at the bulletin-board he gave a yell and cried:
“Jumping Jehoshaphat! Ralph Osborn! Just look at those marks. By
the tall American green-eyed prophet, you made a 4.0 on every daily
recitation in the month, and to make matters worse, knocked a cold
4.0 on the exam!”
Ralph looked with staring eyes. He had the sensation of the man
who has won the capital prize in a lottery. Many were the
exclamations of surprise from his classmates when they saw what
Ralph had done. Most of the fourth section had risen in class rank,
and much credit was given to Professor Scott’s illuminating
instruction by the young men who had been in his section; and now
all of these declared they had known that Osborn had been doing
excellent work and they were not at all surprised he had landed first
in the class. But Ralph in his secret heart felt that Professor Scott
had been very generous to him in his daily marks.
“And only a month ago I was in danger of being bilged,” remarked
Ralph to Creelton when they entered their room.
Creelton did not answer, but slammed things around in a very angry
way.
“What’s the matter with you?” asked Ralph in surprise.
“Do you think I like being cooked by everybody?” snapped Creelton.
“You and Bollup and Himski all came out ahead of me; I stood
number seven; I ought to have stood one.”
“If you can only make a 3.32 on such an easy exam you’ve no right
to stand even number seven,” returned Ralph with spirit. “As you
didn’t deliver the goods and other people did, I fail to agree that you
should have stood number one or any number higher than the one
given you.”
“You talk mighty big for a man whom I saved from bilging in French
last term,” retorted Creelton.
“You offered to help me; I didn’t ask it. And you did help me a great
deal and I thanked you then and I thank you now. But that has
nothing whatever to do with the matter we’re talking about.”
“Great heavens! Will you shut up? I wish I had never seen you. Oh, I
can’t stand it!” And Creelton burst into tears, and dropping heavily
into a chair by the study table, he flung his head down on his arms
and sobbed convulsively.
“Why, Creel, don’t feel badly, old fellow; I’m awfully sorry,” and
Ralph, much touched as well as astonished, went to Creelton and
tried to comfort him, but to no avail. Then, much perplexed, he left
the room and went off to see Bollup. Later when he returned,
Creelton, now entirely over his sad feelings, said: “Os, please excuse
and forgive my words. I cannot tell you how disappointed I was; I
had counted so much on standing number one; and getting class
rank of seven was a bitter blow to me; I just gave way to my
feelings.”
“Don’t speak of it—it’s all right; let’s talk of something else,” returned
Ralph. “It seems glorious to stand number one, but I’ll never keep it.
You may get it next month; cheer up, Creel.”
 CHAPTER XI
Third Classman Osborn

“H ow the time has passed, Os; we’ve finished our an exams,

and it seems as if it were only yesterday when we were
worrying about our semi-ans.”
“You mean when I was worrying, Bollup,” replied Ralph Osborn. “You
never got out of the first section in math and have stood well up in
French and rhetoric, while four months ago I was worrying about
bilging in math.”
“Wasn’t that remarkable? And now you’re the math fiend of the
class! How in the world was it that you did so poorly the first three
months?”
“I didn’t know how to study for one thing. Another thing the lessons
were long and I was more afraid of French and rhetoric and slighted
math. I put in all of my time on learning principles and rules and
didn’t try to work out probs till I got to the section room, and then I
always took too long. I know better now. But these three months
have gone quickly, haven’t they? And we’ll be third classmen in ten
days; won’t that be glorious?”
“You bet, Os, and we’ll teach some of the plebes who enter how to
stand on their heads, sing songs, climb on top of wardrobes, dance
jigs and so forth. We’ll know how to teach them all right, won’t we,
old chap?”
“Not I, Bollup,” replied Ralph, determinedly.
“Why not? Good gracious, man! Aren’t you going to have a little fun
and give the newcomer a few points on naval discipline, rocks,
shoals, and hazards? We had our share of it and none of us is the
worse for it; all plebes need a little good running and the new ones
will feel slighted if they don’t get some; and besides the upper
classmen will expect us to do it. That’s part of the Academy training;
if we don’t start the new plebes right they’ll be too cheeky and fresh
to live with. We’ve got to do it, old man, and you’ll have to do your
share.” Bollup spoke earnestly.
“Your ideas are all right, Bollup, but I’m not going to do any running
whatever,” remarked Ralph quietly.
“Why not, Os; are you afraid of being spotted?”
“Just so. I wouldn’t dare to.”
“It seems to me you’re not worrying about the rest of your
classmates,” said Bollup with a sneer.
“You forget about your watch being stolen and then found on my
watch-chain.”
“Well, what on earth has that got to do with your doing a little
running?” cried Bollup in evident surprise.
“A great deal. There’s somebody here, I have never been able to
imagine who, that wants to get me into trouble. If I should run
anybody I’d be sure to be reported for hazing, and that would mean
certain dismissal. I’m going to walk a straight line and never so
much as speak to a plebe.”
“By George! That watch affair was a most remarkable thing. I don’t
blame you, Os. And you have no notion whatever who might have
done it?”
“Not the slightest. It must have been a corridor boy or a
midshipman; that’s as close as I can get to it.”
“I don’t blame you. Hello! Here’s Creel. Say, Creel, how did you
come out on the exams?”
“Pretty well, I think. But I guess Himski will stand number one in the
class for the year. But if Os keeps up his record in math I bet he’ll
give him a close run for it next year. Say, fellows, we’re going to
start the new plebes right, aren’t we?”
“Well, I should hope so, all of us except Os.”
“What’s the matter, Os? Aren’t you going to do your duty by them?”
“Not I, Creel; I’ll talk to you about that later.”
The time between the events of the last chapter and the above
conversation had simply flown by for the midshipmen of Ralph’s
class. For Ralph it had been an uneventful time. Each day had its
hard work of studies, recitations and drills, and the end of his first
year was now upon him. The second term was most satisfactory to
him. He had developed a remarkable ability of quickly solving
mathematical problems and in this subject he was now easily first in
his class. Sometimes, with great regret, he thought of his watch;
and whenever he thought about it he was always tremendously
puzzled. He could not even imagine a solution to the mystery, but no
further acts of hostility had developed against him by his unknown
foe. Ralph did not worry about this unknown enemy but sometimes
he wondered. The only man he could imagine who would harbor ill
feelings against him was Short, but the latter was far away and
Ralph had never heard of him since his dismissal.
Ralph’s average for the two terms in mathematics was 3.30, which
gave him class rank of 17 in that subject. In rhetoric he was number
61, and in French number 73. His final rank in his class was 41. But
in the other remaining years mathematics would become more and
more important and Ralph had a feeling that by the time he
graduated he would have high class rank.
Graduation happened on a bright June morning. The battalion was
marched to the tune of: “Ain’t I glad to get out of the Wilderness,” to
the chapel where the ceremonies were held. And each midshipman
felt with joy he was getting out of the wilderness. At the Naval
Academy, this tune has for many years been sacredly kept for that
one day, and all midshipmen love it. Ralph and his classmates
emerged after the graduation as third classmen, feeling far more
important with their promotion than did the young men who had just
been graduated. They immediately sat in the seats and walked in
parts of the grounds that, as fourth classmen, they had been
debarred from. And they enjoyed the great boon of addressing the
now second and first classmen by name without the prefix of
“mister.” And these young men were delighted to be “plebes” no
longer, but “youngsters,” as third classmen are called at Annapolis.
On this night occurred the beautiful graduation ball. Ralph went but
proved to be a wall-flower. He did not know any young ladies and
would not have dared to dance even if he had, but he enjoyed the
beautiful scene. “But I’ll go next year and dance too,” he remarked
to his roommate, as they stood in a crowd of midshipmen, watching
the dancers.
The next morning the midshipmen embarked aboard different ships
for the summer practice cruise. Several ships had been detailed for
this purpose, and Ralph with Bollup, Creelton, Himski and others of
his class, was assigned to the monitor Puritan.
This was Saturday morning. On the night before not all midshipmen
had been at the graduation ball, or at least had not spent the whole
evening there, for shortly after ten o’clock a midshipman might have
been seen to enter the Maryland Hotel. He did not stop at the desk
to make inquiries but immediately ran up-stairs, then down the long
corridor, and then knocked at the door of a room.
“Come in,” was heard from the inside, and the midshipman entered.
“Hello, Short!” he cried out. “Gracious, man, what a mustache you
are wearing; I wouldn’t have known you. I’m glad to see you.”
“I doubt that. And don’t call me Short; I’ve registered here as
Johnson, so call me Tom. I’ve just got here and I’m going to leave
by the midnight special. I don’t care to have anybody who knew me
a year ago know I’ve been in town.”
“I suppose not; not if you’re still on that lay of hurting Osborn.”
“Of course I’m still on that lay,” said Short in sudden passion, “and
I’ll continue on that lay until that fellow gets just as nasty a turn as
he did me. When that account is squared I’ll forget him. I’ve come
down for the particular reason of telling you I’m not satisfied with
the way you’ve handled your part of the job. I’ve come to tell you
that you’ve got to take a brace.”
“None could have done it better, Short. If it hadn’t been that he
voluntarily took the watch out to show it he never could have
explained away his possession of it. I wrote you all about that. I did
my part well.”
“Yes, but I planned it,” growled the other; “and it is only success
that proves a thing nowadays.”
“You only planned part of it; you didn’t know anything about his
uncle sending him the watch as a present, nor of the letter.”
“Neither did you. That should have made things easier for you. I
believe you’re welching, that’s my opinion; and look here, if you are,
and I don’t get Osborn, why I’ll get you good and hard. And you’d
better believe I mean business.”
Short spoke savagely, his temper strongly aroused.
“Now look here, Short,” interposed the other, “I’ve not welched, and
you ought to know it. But I’ll admit I’m sick of my job and I’m going
to ask you to let me out of it.”
“Why are you sick of it?” inquired Short in a sneering tone.
“For one reason because I like him. He’s a fine, generous, good
fellow and he looks upon me as one of his best friends. I’ve not a
thing against him; he’s never done me a single ill turn and I’ve no
reason to dislike him. This thing is on my mind all the time and I’m
sick of the job. Now I want you to let me out of it. I’ll repay you the
money you’ve advanced to me——”
“I thought you were a welcher,” cut in Short contemptuously, “and I
know what you’ve done is not from any love of me; you’re my man,
bought and paid for; do you understand that? And if you fail me I’ll
send you to jail, just as sure as I’m sitting here.”
“Sh, Tom, don’t talk so loud; some one may hear.”
“They’ll hear a good deal about you before long if you don’t stand
up to your job. Now look here; I’ll be a good boss but you’ve got to
do what I tell you to do. You’re my man, now don’t forget that. I
suppose I’m a villain; I don’t care anything about that. I don’t want
any physical harm to come to Osborn; that isn’t what I’m after. But
he had me dismissed in disgrace and I intend that he shall have a
dose of the same medicine; you’ve got to do the work, that’s all
there is about it.”
“It’s mighty dirty work, Tom,” said the other bitterly.
“Not a bit dirtier than when you deliberately stole two hundred
dollars from me. And you’ve taken my money right along without
any kicking; it’s too late for you to get tender about the work you’re
doing.”
The other turned pale and looked troubled. His voice shook as he
replied: “Well, Tom, there’s no use whatever of trying to put Osborn
in the soup while the present superintendent and commandant are
here. They know somebody is after Osborn—I wrote you all about
that. After the letter I sent in signed ‘Indignant Fourth Classman’
Osborn was called to the superintendent’s office. What occurred
there none of us know; he has kept mum about it, and of course I
couldn’t afford to be inquisitive. Then after that came the
superintendent’s order directing the person who signed that letter to
report to him; you see there’s no use for us to put up any job on him
now. We’d simply defeat our own ends, that’s all. You’d better drop it
for the time, Tom.”
“Perhaps you’re right; later on it would come harder to him than
now. But that fellow must be dismissed. Look here, can’t you get
him on hazing?”
“I could easily if he would haze, but he knows the man that tried to
have him accused of stealing and of cheating would report him if he
hazed; I’ve heard him say so and he’s not going to do any.”
“I’m not particular about having him go for hazing because that isn’t
considered dishonorable, though that would be better than having
him graduate. There’s no chance of his bilging in his studies?”
“Not the slightest; he’s a regular math fiend.”
“How about the cruise? Couldn’t you arrange for something to
happen there?”
“Look here, Tom, I’m not going to do anything that will fall back on
top of me. If I can fix him to your satisfaction and not to be
suspected I will. Now if that doesn’t suit you, you had better call for
a policeman and have me put in jail. That’s all I’ve got to say.”
“If you don’t do what I tell you to do I most certainly shall put you in
jail, depend on that. I won’t force you as to time, and if you can’t do
anything while the present superintendent and commandant are
here, because of their interest in Osborn, I won’t force you. You
must make and take your time. Here’s a couple of hundred dollars
——”
“I won’t take any more money from you!” vehemently exclaimed the
midshipman.
“Oh, drop that kind of talk. Take the money and go. That’s all; we
understand each other. If you welch you are going to be jammed
and will be kicked out of the Academy in the same way your friend
Thomas G. Short was.”
The midshipman stood irresolute. His eyes glittered; he approached
the table where the roll of bills lay; then suddenly grabbing the
money, he bolted out of the room.
Short gave a low, harsh laugh as his visitor left. “He’ll stay bought,”
he muttered, as he packed his grip preparing to leave.
 CHAPTER XII
Chief Water Tender Hester

“A ll hands up anchor! Turn out everybody, lash and carry! Bear a

hand, show a leg there, out you go!” were the rude cries
aboard the Puritan at a little after five o’clock Monday morning. The
Puritan was getting under way and left early, her captain wanting to
take advantage of the high tide that existed at that hour. The
midshipmen had slung their hammocks in a confined space inside
the superstructure, and first classmen were turning them out. They
bawled and yelled; Ralph Osborn was sleeping soundly at that hour
and didn’t fully comprehend what it was all about until one of the
first classmen stooping directly under Ralph’s hammock, having
noticed that the occupant had made no move toward turning out,
suddenly raised himself and Ralph was instantly spilled out of his
hammock. He lit feet first, and now wide awake started to lash his
hammock. Everything was in confusion on the deck, for a number
had been turned out in this same unceremonious fashion.
Cries of: “Bear a hand, get your hammocks on deck,” hastened him
and soon his hammock was neatly lashed and was in its netting. For
two hours after that, as far as Ralph was concerned, nothing
whatever happened. The old monitor steamed out the narrow-
dredged channel leading from the Severn River to Chesapeake Bay.
On the bridge were the captain and several other officers navigating
the ship, and forward an officer in charge of the anchors walked up
and down.
Ralph longed for the good old days of the previous summer when he
would have been busily engaged hauling on different ropes; but
now, longing to do something, and there being nothing whatever for
him to do, he walked about listlessly.
“If they won’t let us work why didn’t they let us sleep? What was the
good of dumping us out in that style?” he complained to Bollup.
“Custom, Os, custom. When a navy ship gets under way everybody
has a station and must be there, no matter whether he has anything
to do or not. Same thing happens when a ship comes to anchor.
Everything in the Navy is run by regulation or custom. Why, there
was an old regulation years ago that required a ship to let go her
anchor if she went aground. Well, a lieutenant named Percival one
time was officer of the deck of a ship that went aground. ‘Let go
both anchors!’ he shouted. ‘Can’t do it, sir,’ yelled back the
boatswain’s mate on the forecastle; ‘they’re not bent to the chains.’
“‘Bother the difference,’ shouted back Percival. ‘Let ’em go, I say; if
we lose the ship, it’ll be logged we went ashore according to the
rules, regulations and customs of the service,’ and the anchors were
dropped, though they were not attached to the chain cables. And so,
Os, we were turned out not for any useful exercise, but just because
it is the custom for everybody to be up when the ship gets under
way.”
“Stuff,” remarked Ralph disdainfully. “Do you believe that yarn?”
“Of course I do. Anderson of the first class just told me, Captain
Waddell told him, Admiral Farragut told Waddell just before he said,
when they were running by the forts at New Orleans, ‘Damn the
torpedoes, go ahead,’ and years before that Lieutenant Percival told
Admiral——”
“Hold on there, Bollup, Admiral Farragut said that at Mobile Bay, not
at New Orleans. How in the world did you ever pass your history
entrance exam? and as for that yarn about Percival, pshaw, I don’t
believe it ever happened. Hello, there is the bugle call for breakfast.
Goodness, I’m glad we’re going to get something to eat.”
After breakfast the midshipmen were divided into different sections
for instruction. The first prescribed lesson in seamanship was: “How
many anchors are there aboard? Tell the difference between bower,
sheet, steam and kedge anchors. Tell what each anchor aboard
weighs. Name the different parts of an anchor. How secure an
anchor for sea; how secure for letting go?”
The prescribed lesson in steam engineering was: “What kind of
boilers and engines are installed aboard this ship? What pipes and
valves does the steam pass through in going from the boilers to the
engines? What valves do you open and shut to pump water into a
boiler?”
In electricity the lesson was: “Tell what you find on the switchboard,
and the use of each.”
In gunnery: “Go into the turret, mention the different mechanisms
you find, and tell how and for what purpose each is used.” These
were for the third classmen. The first classmen had more advanced
lessons, and were also given responsible duties with the navigator
and chief engineer, and as officer of the deck.
“We’ll be busy this cruise,” remarked Ralph to Creelton, as the third
classmen were copying their prescribed lessons in the various
subjects from the bulletin-boards. “We work at our seamanship from
eight-thirty until nine-thirty then study, and then at our gunnery
from eleven until noon. Then from one until two we are in the
engine and fire rooms, and from two until three in the dynamo
room. Officers are to go around with us and explain things and
answer questions, and we put things down in our note-books. Then
each night we have to hand in our note-books with the answers to
the prescribed lessons written out. By gracious! But this will keep us
busy, and the officers, too. But we ought to learn a lot.”
The lessons were changed each day, and at different times the
instruction periods were changed to practical drills; and whenever
the ship was at anchor the midshipmen were always exercised at
rowing and sailing. Whenever the Puritan was under way the
midshipmen at all times were to be seen going about the different
parts of the ship, asking questions of enlisted men and officers,
jotting down notes and making sketches. Much knowledge was
absorbed of the different mechanisms in the ship and their
manipulation; all were being fitted to familiarity with them, which
after long years of experience makes the competent officer.
In a few days the Puritan was anchored off the ship-building works
at Newport News. Here parties of midshipmen were sent ashore on
tours of inspection under charge of different officers.
Before starting ashore on Thursday morning, Ralph Osborn noticed a
group of enlisted men on the quarter-deck. These men had made
requests for extra leave, more than had been allowed them by the
executive officer. The latter was Lieutenant-Commander Graham
who was considered to be a very efficient officer but one especially
severe with the enlisted men.
“You men can’t have forty-eight hours’ liberty,” Ralph heard him say.
“We leave Saturday morning for the North and I’ll not have anybody
out of the ship later than six o’clock to-morrow evening. Those of
you who are on the first conduct grade and want that may give in
your names to the ship’s writer. That’s all you’ll get and you needn’t
ask for anything more. And if any of you are not on the first conduct
grade you needn’t ask for that. Now clear out, all of you.”
All of the men but one touched their caps and moved forward. This
one saluted and in a voice full of suppressed emotion said: “Sir, I
request special permission to speak to you. My wife lives in this town
and she is sick with typhoid fever. I haven’t had any liberty, I’m
classed—but I’ve just received word she is very bad; could you, sir,
could you let me go over to see her for just a couple of hours? I’ll
promise you to be back on time, sir!”
The speaker was a tall, neatly-dressed man, about thirty years old.
He was smooth shaven, and his face was what would be called a
strong one; strong for good, or perhaps for evil if led in a wrong
way. Such a face betokened an impulsive, warm-hearted character.
To Ralph the anguish of his face, and the trembling of his voice were
most appealing.
“Poor fellow! I do hope Mr. Graham will let him go,” he observed to
Creelton.
Lieutenant-Commander Graham looked fixedly at the man before
him. There was no hope of kindness in his cold gray eyes. “Your
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